Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

Staff Data Scientist -  Experimentation & Measurement 

Overview:

As a Staff Data Scientist on the Decision Science team at PlayStation, you will take a leading role in designing and interpreting experiments that evaluate the impact of key initiatives and programs. You’ll help shape how millions of players around the world experience PlayStation by bringing statistical rigor, clear measurement strategies, and deep causal inference expertise to some of the most critical initiatives across the company. This highly visible role will advance our experimentation practices and ensure that data-driven insights inform the way we build, market, and evolve our products.

What You’ll Be Doing:

• Design, execute, and interpret A/B tests and quasi-experiments, and apply advanced causal inference methods when experimentation isn’t feasible.
• Partner with cross-functional teams (product, engineering, marketing) to embed experimentation into development and iteration cycles and communicate results with the company’s senior leadership.
• Mentor and guide other Data Scientists, providing thought leadership and technical direction.
• Serve as a thought leader on best practices for hypothesis development, metric selection, test structure, and results communication.
• Help define and contribute to centralized experimentation frameworks, tools, and documentation to scale best practices across the company.
• Independently extract, transform, and analyze data from complex systems using SQL, Python, and other analytics tools.
• Communicate findings clearly to technical and non-technical stakeholders, helping drive business decisions with rigor and clarity.
• Stay current on new methodologies in experimentation and causal analysis, and bring fresh perspectives to the team’s work.
• Your insights will directly influence how PlayStation builds, markets, and evolves products across our ecosystem.

asic Requirements:

• Bachelor’s degree or equivalent.
• 6+ years of experience in a data science experimentation/causal inference-focused role (4+ with PhD).
• Deep expertise in A/B testing and causal inference, including quasi-experimental methods.
• Proficiency in SQL and Python for data extraction, transformation, and analysis.
• Broad and applied knowledge of statistical techniques.
• Experience with machine learning modeling is a plus.
• Proven ability to influence product and business decisions through clear, actionable insights.
• Experience contributing to or developing experimentation frameworks, best practices, or internal tooling.
  
  Preferred Requirements:
  • Master’s or PhD in Statistics, Economics, or Econometrics. Other degrees in quantitative disciplines may be considered.
  • Bonus: Interest in or knowledge of video games, gaming platforms, or player behavior.

#LI-KC

Anduril’s Electrical Engineering Team is seeking a Wireless Systems Principal Engineer with a strong background in modulation/demodulation, forward error correction, multiple access, duplexing schemes used in wireless communications. In this role, you design, adapt, and optimize wireless communication waveforms for use by autonomous vehicles to communicate with each other and with human operators.  Familiarity with tradeoffs concerning performance, resiliency and range is necessary.  You will also work with embedded SW and FPGA engineers to optimize capability while maintaining the big picture mission and system view with an eye to both verification and validation of the end system. Additionally, you will guide the SW and FW engineers to develop SW/FW/HW to integrate wireless systems with autonomous vehicles and their controllers.  The preferred person for this role has a strong background in the effects of signal processing, communication systems architectures upon the users that rely upon them. Additionally, experience in providing technical approach to System Engineers, FPGA and SW engineers, and schedule status including work estimates and staff resource estimates to program management is preferred.  Substantial experience in the use of Matlab for waveform, network, and traffic design and simulation is highly preferred.

WHAT YOU’LL DO

• Guide embedded SW engineers and FPGA engineers in trade studies, implementation and optimization of waveforms to the autonomous applications.
• Collaborate with a multidisciplinary team of systems, software, firmware and hardware engineers to support integration activities.

REQUIRED QUALIFICATIONS

• Strong, demonstrated leadership of DSP engineers in the comms sector to include technical and programmatic leadership aspects - demonstrated ability to understand simple and innovative algorithms and work with program management, software and firmware groups to deliver compelling capabilities
• Familiarity with design of Modulation, Demodulation, Error Correction Schemes, Symmetric and Asymmetric Encryption and their affects on systems that use them.
• Familiarity with CSMA, CDMA, TDMA, FDMA, FDM, TDM, DAMA and similar communications protocols and their affect on throughput, system capacity, jitter, latency, and link integrity
• Familiarity with DSSS, FHSS, Chirp Spread Spectrum, OFDM, PSK, FSK, and similar modulation systems and their affects on links that use them.
• Experience with deceiver design parameters including: AGC, Frequency and Phase correction, DC and I/Q offset compensation, equalization, ACI and CCI mitigation
• Familiarity with MATLAB and/or Simulink.
• Experience with embedded devices for DSP, including FPGA, GPU, ASIC, and/or Software Defined Radios and the tradeoffs between which is best for what circumstances.
• Demonstrated algorithm design and implementation
• Ability to analyze and simulate algorithm performance and present findings to audience without deep technical knowledge of subject
• Familiar with commercial and/or military wireless and satellite communication standards
• Enthusiastic about both working with a team and executing DSP work individually
• Some travel required especially for review prep, reviews and integration activities, roughly 25% on average
• Must be able to obtain and hold a U.S. security clearance

PREFERRED QUALIFICATIONS

• BSEE or higher with an emphasis on Digital Signal Processing and/or information theory and practical experience
• MIMO, phased array, and beamforming experience
• Strong experience with DSP implementation for embedded devices and/or software defined radios
• Demonstrated technical task leadership of embedded SW and FPGA engineering and interfacing with program management
• Systems Engineering and mission analysis experience

We are seeking a Technical Marketing Senior Manager to join our System LSI - Custom SoC Sales and Business Development Team in San Jose, CA.  In this role, you will be responsible for identifying new opportunities for custom SoC (ASIC) business, conducting pre-shaping activities including technical requirements review and commercial discussions with potential customers, and building relationships with customers across the US market. This customer-facing role is highly cross-functional, where you will also manage day-to-day account management activities on both the technical and business sides with internal and external teams. We are seeking a high- energy professional with strong communication skills towards internal stakeholders and customers, as well as the ability to lead and develop new processes and ideas.  The successful candidate will thrive in a fast-paced, dynamic environment and be able to develop strategic relationships with customer teams. 

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy

Job ID: 42912

What You’ll Do

• Support the design-in activities and business operations by working with cross-functional teams across Engineering, Sales and Marketing teams to secure customer engagements.
• Act as local support interface for US customers for existing accounts and ongoing programs.
• Engage in engineering & commercial discussions with customers.
• Market survey and developing new customers and applications.
• Act as local POC for engineering/commercial VOC collecting and leading issue resolving by circling back internally with right internal POC.
• On-going and future projects reporting to both US and Korea Executives.
• Build relationships with internal stakeholder teams such as Marketing, Sales, Product Planning and development teams to know and understand S.LSI’s differentiated offerings and strategies.
• Work with customer teams to map their requirements to S.LSI offerings, identify potential gaps, and champion their cause by driving internal development teams to address their needs and deliver technical solutions.
• Develop and build relationships with customers’ teams to understand their technology needs, application requirements and jointly define the best silicon/platform solutions to enable customer’s products.

What You Bring

• Highly Technical Background with deep business acumen and the ability to synthesize technical and business information into clear, compelling executive-level presentations that influence internal and external stakeholders.
• Bachelor’s Degree in Engineering, Business, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• Technical sales and/or Marketing experience, management experience, technical/customer program management, or field applications engineering experience.
• Both Pre and Post Sales Customer Support.
• Good understanding of Semiconductor Industry, especially in SoC (System on Chip).
• Understanding or past experience with ASIC design and manufacturing flow, including advanced packaging is a Plus.
• Ability to analyze customer’s problem and needs from the component to system and application level based on customer’s requirements and purpose the solution that maps out to Samsung LSI’s offering.
• Frequent work and meetings are required with Korea.
• Korean language proficiency is a plus but not required.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

What You’ll Do

As a seasoned Senior Technical Project Manager (ASIC) you will lead complex silicon development projects from specification definition through tape-out, fabrication, and post-silicon validation. You will be the primary face of Samsung’s (SLSI’s) ASIC design, verification, physical design, firmware, foundry and advanced packaging teams to the customer and ensure the timely delivery of all collateral. This role requires a strong technical background in semiconductors combined with exceptional program management skills to navigate risks and drive execution excellence.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Reports to: Team leader/Head of Custom SoC Solutions Team.

Job ID: 42809

Key Responsibilities

• End-to-End Program Ownership: Work with customers from initial concept and specification stage to silicon tape-out, bring-up, and production. This includes not only technical, but also spans commercial and legal domains.
• Project Planning & Scheduling: Develop and maintain detailed project plans, milestones, and resource allocation. Proactively identify and resolve bottlenecks and critical path issues.
• Cross-Functional Coordination: Collaborate with Architecture, RTL, Verification, Physical Design (PnR), DFT, Firmware, Emulation and Packaging teams to ensure aligned deliverables. Participate in cross functional meetings and identify and eliminate bottlenecks.
• Risk Management: Proactively identify risks and develop mitigation plans to avoid tape-out delays. Hold the development teams accountable for the scheduled quality deliverables.

 What you bring

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 15+ years or a Master’s degree with 13+ years.
• Experience: 10+ years in the semiconductor industry, with at least 5+ years in technical program/project management for ASIC/SoC products.
• Technical Knowledge: Deep understanding of the full ASIC design flow (RTL, Simulation, Synthesis, STA, PnR, DFT, Tape-out).
• Methodologies: Proven experience working with advanced process nodes and high-speed design.
• Tools: Proficiency in project management tools (Jira, Confluence, MS Project) and familiarity with EDA tools (Synopsys, Cadence).
• Experience with complex packaging (2.5D/3D IC, Si interposers, TSV).
• Knowledge of automotive functional safety and other automotive industry requirements
• Experience with hardware emulation platforms (Palladium, Veloce, ZeBu).
• Leadership: Strong ability to influence cross-functional teams without direct authority.
• Problem-Solving: Ability to analyze technical problems and drive solutions in a fast-paced environment.
• Communication: Excellent verbal and written communication skills, tailoring technical information for various stakeholders.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

Principal Engineer, SOC Design

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Job ID:  42866

Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy

• Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
• Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
• Reviews 3^rd party IPs including ARM cores, DDR controller, and UCIe PHY 
• Responsible for integrating the third part IPs and sub system at top level
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

What You Bring

• Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
• Highly motivated with good verbal and written communication skills.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
• Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
• Good understanding of PPA (performance, power, and area) trade-offs.
• Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
• Experience in interfacing 3^rd party service companies for DFT/PI/PD.
• Good knowledge and experience in AMBA bus fabric, ARM cores.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Responsibilities and Description: 

The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. 

Required Qualifications: 

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Minimum 5 years of experience in digital physical design and verification.
• Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff.
• Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification.
• Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
• Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
• Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell.

Preferred Qualifications: 

• Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. 
• Experience in DFT (Design For Test) flows and ATPG.
• Experience in I/O design flow in multi-voltage power domain.
• Experience in building chip floor-plan including pin placement, partitions and power grid.
• Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints.
• Experience with build tools such as CMake and Bazel.
• Experience with code coverage and regression setup.

Principal Post Silicon Validation Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Principal Embedded SW/FW Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Senior Embedded SW/FW Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Senior Post Silicon Validation Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Drive advancement of DV methodologies and improvements.
• Manage external IP providers and verification partners when needed.
• Take lead on large and/or complex systems. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
• Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
• Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
• Experience with developing and integrating reference models.
• Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
• Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
• Involvement in post-silicon validation planning and execution. 

Nice to Have

• Experience with low power verification.
• Experience with analog behavioral models.
• Familiarity with physical design flows.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $190,000 – $285,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role

We are seeking a Senior Embedded Firmware Engineer to develop and enhance low‑level embedded firmware for high‑performance mixed‑signal and digital SoCs. In this role, you will contribute to the bring‑up, validation, and production readiness of custom silicon by working closely with digital ASIC, mixed‑signal, RF, verification, and system engineering teams. You will help implement core firmware components, validate hardware functionality, and ensure reliable, scalable firmware foundations for next‑generation products.

Responsibilities

• Contribute to the design and implementation of embedded firmware architecture, including boot flows, HAL components, drivers, and system services.
• Develop low‑level firmware in C/C++ (and assembly when required) for CPUs, DSPs, and microcontrollers within custom SoCs.
• Implement and maintain bootloaders, secure boot flows, and early hardware initialization sequences.
• Develop device drivers for on‑chip peripherals such as DMA engines, memory controllers, interconnects, SerDes, ADC/DAC interfaces, timers, and GPIO.
• Participate in pre‑silicon firmware development and validation activities.
• Support post‑silicon bring‑up, including power‑on sequencing, clock/reset initialization, memory bring‑up, and peripheral testing.
• Debug hardware/firmware interactions using JTAG, logic analyzers, oscilloscopes, trace tools, and custom debug instrumentation.
• Collaborate with SoC architects and designers to refine register maps, memory maps, interrupt structures, DMA flows, and debug infrastructure.
• Provide firmware input during design reviews and silicon development milestones.
• Bring up and integrate RTOS or bare‑metal environments.
• Support integration with higher‑level system software or application processors.
• Implement robust error handling, logging, and recovery mechanisms.
• Contribute to manufacturing test firmware, production firmware, and field diagnostics.
• Help ensure long‑term maintainability and scalability of firmware across multiple SoC generations.

Qualifications

• 5+ years of experience in embedded firmware development for SoCs or complex embedded systems.
• Strong proficiency in C/C++ for embedded systems and a solid understanding of low‑level hardware interactions.
• Hands‑on experience with SoC bring‑up or board‑level bring‑up.
• Strong understanding of CPU architectures (ARM, RISC‑V, or similar), memory systems (SRAM, DRAM, DDR, caches), interrupts, DMA, and low‑power states.
• Experience collaborating with ASIC/SoC design or hardware engineering teams.
• Demonstrated ability to debug complex hardware/firmware issues.

Nice to Have

• Experience with secure boot, hardware security modules, or cryptographic accelerators.
• Familiarity with pre‑silicon environments such as RTL simulation, emulation, or FPGA prototyping.
• Experience with high‑speed interfaces (PCIe, Ethernet, JESD, SerDes).
• Background in satellite communication, networking, compute, automotive, or other high‑reliability systems.
• Experience developing firmware for radiation‑tolerant or mission‑critical systems.

Compensation and Benefits:

• Base salary range for this role is $160,000 – $220,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.  

Responsibilities 

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 
• Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 
• Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 
• Develop and maintain scripts and automation to improve flow efficiency and consistency. 
• Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 
• Assist in chip-level integration, ECOs, and tapeout preparation. 
• Contribute to methodology development, tool evaluation, and flow documentation. 
• Support your product through production and spaceflight.  

Required Qualifications  

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 
• 5–10 years of experience in ASIC physical design for complex SoCs. 
• Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 
• Strong understanding of timing analysis, power optimization, and physical verification flows. 
• Experience with hierarchical or flat SoC design methodologies. 
• Familiarity with FinFET technologies. 
• Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 
• Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications  

• Exposure to radiation-hardened or space-qualified ASICs. 
• Experience with chip-package co-design or advanced packaging (2.5D/3D). 
• Familiarity with physical design service vendor management or offshore collaboration. 
• Experience with sign-off through TSMC. 
• Experience with Gate-All-Around technologies.  
• Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role supports the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will collaborate with internal teams for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.  

Responsibilities 

• Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Establish package design standards, methodologies, and best practices.  
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces. 
• Support package-level SI/PI strategy, including high-speed digital interfaces, power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling. 
• Drive material selection, substrate technology choices, and assembly process optimization.  

Qualifications 

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 5+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies. 

Nice to Have

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates). 
• Background in high-speed digital or mixed-signal SoCs. 
• Familiarity with aerospace, space, or high-reliability electronics. 
  

Compensation and Benefits:

• Base salary range for this role is $180,000 – $260,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Contribute to advancement of DV methodologies and improvements.
• Engage external IP providers and verification partners when needed. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
• Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
• Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
• Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). 

Nice to Have

• Experience with developing and integrating reference models.
• Understanding of low power verification.
• Familiarity with gate-level simulation and analog behavioral models.
• Involvement in post-silicon validation planning and execution.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 
  

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are looking for a Principal ASIC Synthesis and Timing Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the constraints development and validation—from RTL handoff to synthesis —and collaborate closely with architecture, RTL design, DFT, and physical design team. This role also involves managing external physical design partners, driving convergence of schedule and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

• Own the complete RTL-to-Synthesis flow: Do synthesis at block and top level, Work with physical design team to integrate the floorplanning information for physical synthesis. 
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Own Lint, CDC and UPF checks and drive collaboration to close out issues. 
• Develop an end to end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the  post layout netlist.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.  

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with timing closure, IR drop analysis, low power implementation and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience in design convergence with offshore/outsourced PD teams or vendors.
• Able to resolve formal verification issues. 
• Able to analyze and fix VCLP issues regarding UPF.
• Experience with Logic equivalence check debug, Functional ECO development and implementation with minimal database disruption, Low power checker to validate UPF;
• Familiarity with DFT integration, STA sign-off with functional ECO implementation.
• Excellent communication, leadership, and cross-functional collaboration skills.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team. 

Nice to Have 

• Exposure to radiation-hardened or space-qualified ASICs.
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.  
• Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

• Base salary range for this role is $190,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
• Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.

Required Qualifications 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC physical design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
• Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
• Excellent communication, leadership, and cross-functional collaboration skills.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

• Base salary range for this role is $190,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
• Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
• Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Nice to Have

• Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
• Familiarity with developing and integrating reference models.
• Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI).
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $130,000 – $200,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role

We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

Responsibilities

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Serve as the primary technical interface to substrate vendors, assembly houses, and OSATs.
• Drive material selection, substrate technology choices, and assembly process optimization.

Qualifications 

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 10+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies.

Nice to Have

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
• Background in high-speed digital or mixed-signal SoCs.
• Familiarity with aerospace, space, or high-reliability electronics.
• Experience defining packaging strategy from early architecture through first silicon and volume ramp.
• Demonstrated history of building or scaling package design methodology within an organization.

Compensation and Benefits:

• Base salary range for this role is $200,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

ABOUT THE TEAM

The Air Dominance and Strike (AD&S) Electrical Engineering Team is responsible for developing high-reliability avionics, embedded processing, and power systems for Group 5 air vehicles and missile platforms. Working across hardware, software, and mission autonomy, the team delivers flight-critical electronics, PCB assemblies, and FPGA-based processing architectures that enable Anduril's next-generation autonomous air platforms to operate in complex and contested environments. AD&S Electrical Engineers drive end-to-end development, from system architecture and circuit design to verification, integration, and flight test, ensuring scalable, mission-ready solutions that meet the performance, reliability, and survivability demands of the U.S. Military and modern air warfare.

ABOUT THE JOB 

We are looking for an Senior Electrical Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be responsible for end-to-end avionics systems and subsystems development. You will also be working on design, integration, testing, and validation processes. This will require knowledge and experience in PCB design, harnessing, process management, and cross-functional teamwork. If you are looking to join a team in rapid avionics development, then this role is for you.

WHAT YOU’LL DO

• Develop high performance, high efficiency, and highly robust avionics solutions for air vehicle platforms
• Develop reliable on-board communication systems to exchange high bandwidth data across various air and ground assets
• Architect, design, and build high-speed digital PCBAs (schematic capture, simulation, board layout)
• Help decide what to do in-house and what to outsource, communicate design requirements with external vendors and help drive the progress
• Develop relationships with external vendors and communicate design requirements to external vendors and suppliers.
• Work cross-functionally between software, firmware and hardware teams
• Develop hardware validation test plans for sub-system and full system products.

REQUIRED QUALIFICATIONS

• Bachelor’s degree in Electrical Engineering, or a closely related field.
• 8+ years relevant experience in electrical hardware design.
• Experience designing high density PCB layouts with an understanding of cutting-edge PCB manufacturing technology.
• Deep understanding of thermal, mechanical, power and performance tradeoffs.
• Experience with creating test plans, benchmarking and performing validation tests to determine performance of complex hardware systems.
• Understanding of high-speed interfaces (PCIe, DDR, USB, MIPI, etc.), power integrity, and signal integrity.
• Knowledgeable of EMI/EMC susceptibility and emissions along with mitigation experience.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

PREFERRED QUALIFICATIONS

• Experience with high performance SOMs (System On a Module).
• Experience in developing FPGA and ASIC architectures.
• Experience with rapid, hands-on prototyping.
• Skilled at soldering and reworking microelectronic components.
• Knowledgeable in RF investigation and analysis with the use of specialized equipment (Spectrum analyzer, Network Analyzer, etc) and RF simulation tool suites.
• Knowledge of state-of-the-art hardware systems, software tools and algorithms for interfaces required for sensors, actuators, firmware development, and inter-communication bus protocols (CAN-FD, Ethernet, SFP, 1553, etc).
• Experience using Linux command line interface (CLI).

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day remote. 

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade-offs and verification. A background in electrical engineering, electronics or relevant fields is required. Must love all things high speed!

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above (e.g. 100GbE, GDDR6, PCIe Gen5+).
• You’re comfortable working with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT as well as knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards.
• You are proficient with PCB ECAD tools (ideally Cadence Allegro).
• You communicate clearly (written and verbal), think critically, and love solving complex signal integrity problems.
• You’re enthusiastic about all things high speed and enjoy collaborating across teams

What We Need

• Design, extract, and simulate complex breakout structures, including end-to-end simulations and validation against physical hardware. Perform simulation and extraction of board models for both SI and PI.
• Contribute to design and sign-off with internal and external ASIC packaging teams, ODMs, and internal layout teams. Create design specifications, work with external vendors, and drive adoption of new interconnect and packaging technologies.
• Actively participate in design reviews, providing insight from your SI/PI expertise and a broader system perspective.
• Support post-silicon bring-up and help troubleshoot production and field failures related to signal and power integrity. Document design processes and provide training/knowledge sharing to other team members.

What You Will Learn

• How to work at the cutting edge of high-speed interconnects, influencing the next generation of ASIC packaging and PCB architectures.
• Deep exposure to advanced ASIC packaging flows and collaboration models with internal and external packaging teams.
• Hands-on experience with emerging high-speed connector technologies and materials, including evaluating material trade-offs for performance and manufacturability.
• Best practices for end-to-end SI/PI validation, from simulation through to lab correlation, post-silicon bring-up, and field failure analysis.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will own end-to-end technical engagements, translating complex architectural advantages into customer wins while shaping our product roadmap through direct market feedback. If you combine deep technical expertise with exceptional customer engagement skills and want to drive the adoption of next-generation compute IP, join our team.

This role is hybrid, based out of the United States or Canada near one of our main office locations.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with proven success in CPU/GPU/NPU IP sales engagements.
• Technical expert who can articulate complex architectural benefits and conduct deep-dive analyses.
• Self-driven professional who independently manages multiple customer relationships from discovery to win.
• Strategic thinker who identifies customer pain points and positions solutions effectively.

What We Need

• 7+ years in the semiconductor industry with a degree in EE or related field including customer-facing roles in CPU IP.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Deep technical knowledge of CPU architectures, semiconductor technologies, and system-level design.
• Exceptional presentation and communication skills with ability to engage all organizational levels.
• Proven track record of technical wins and managing multiple simultaneous accounts.

What You Will Learn

• How to position cutting-edge RISC-V and AI accelerator IP against industry incumbents.
• Advanced customer engagement strategies for complex technical sales in the semiconductor industry.
• Direct influence on product development through customer feedback and market insights.
• The complete IP business cycle from evaluation through design win and production success.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with industry-standard tools (FusionCompiler, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
• Experience driving physical design requirements from early architecture through final signoff.

What You Will Learn

• How to implement cutting-edge AI accelerators, high-performance CPUs and the SOCs that host them on the most advanced process nodes.
• Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
• End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
• Direct impact on products that are redefining the landscape of AI and high-performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking  a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures.

This role is remote role open to any location in the U.S.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts.
• Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off.
• Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity).
• Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs.
• A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues.

What We Need

• Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout.
• Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off.
• Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS.
• Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure.
• Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug).
• Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification.
• Bring a solid academic foundation: B.S./M.S. in EE/CE or related field.

What You’ll Learn

• How to implement and close cutting-edge D2D interfaces in advanced multi-die/chiplet architectures.
• Advanced strategies for co-optimizing routing, power grid, and timing for high-speed links across dies.
• Deeper integration techniques working with analog PHY teams, including model handoff (LEF/LIB) and constraint-driven interface design.
• How to drive repeatable, scalable PD methodologies for high-speed interfaces that can be leveraged across future chiplets and products.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

We are looking for an ASIC Design Methodology Engineer to advance our design infrastructure and flows across RTL development, verification, and physical implementation. This role is ideal for engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate silicon success.

This role is hybrid, based out of Toronto, Ottawa, Austin, or Boston.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A strong advocate for design quality and productivity, with expertise in ASIC design flows.
• Skilled in RTL design and familiar with static and dynamic analysis tools.
• Comfortable automating design checks and improving methodology for scalability and reuse.
• A collaborative engineer who partners effectively across RTL, verification, and backend teams.

What We Need

• Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration.
• Own and evolve static code analysis (Lint, CDC, RDC, DFT) and RTL-netlist logic equivalency design methodologies
• Develop synthesis timing constraints (SDC) and low power design specifications (UPF)
• Support RTL-to-GDS flow enablement, ensuring clean handoffs and sign-off readiness.
• Collaborate with EDA vendors and internal tool owners to optimize performance, quality, and runtime.

What You Will Learn

• How large-scale AI SoCs are architected, integrated, and brought to silicon.
• How methodology choices directly impact design performance, power, and verification closure.
• How to build and scale ASIC design flows supporting cutting-edge compute architectures.
• How to integrate cross-functional workflows across design, DFT, DV, physical, and firmware teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Santa Clara, CA or Austin, TX

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM.
• You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
• You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams.

What We Need

• Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
• Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

What You Will Learn

• How to drive DFT for industry-leading AI/ML architectures, working on high-performance chips with aggressive performance and power targets.
• Practical strategies to reduce test cost while maintaining coverage, and to design DFT hooks that accelerate silicon bring-up and yield learning.
• How to minimize DFT intrusions while integrating cleanly with RTL, verification, physical design, and production test flows.
• How a senior, cross-functional ASIC team collaborates across design, PD, verification, and manufacturing to achieve first-pass silicon success on advanced nodes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Hudson River Trading (HRT) is hiring an AI Researcher to join the HAIL team. HAIL (HRT AI Labs) is the team at HRT responsible for developing and maintaining our most powerful models, which are used by our trading teams to drive a significant fraction of our trading. We are building and deploying "foundation models for markets", that ingest and train on vast amounts of market data, to make predictions about future market state. We are seeking experienced AI researchers to join our team to accelerate our efforts.

Researchers have great independence to pursue the research directions they think would be most impactful as part of a small focused team with minimal bureaucracy. They are enabled by state-of-the-art research clusters with very high GPU-to-researcher ratios, and supported by excellent engineering, hardware, and systems teams to realize their vision. Your work will be directly, clearly, highly impactful on the business, and it will be challenging: this is a field with no easy or obvious solutions. You'll be responsible for improving every part of our models: from featurization of data, to architecture design, to training dynamics, to how trading decisions are made.

Qualifications

• Must have two or more years work experience in deep learning research, for any domain: robotics, biology, chemistry, physics, audio, video, etc.
• Experience translating methods between areas of application is highly valued.
• LLM experience is valuable, but not necessary.
• Strong engineering skills valued, especially any of: GPU kernel development, lower-level Pytorch/JAX development, intermediate C++, FPGA/ASIC experience, HPC experience.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. 

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.

Responsibilities

• Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
• Investigate new technologies and tools
• Contribute to a nimble hardware development tech stack

Qualifications

• Ability to describe hardware designs at a high level, low level, or anywhere in between
• Brilliant design, optimization, debugging and problem solving skills
• Professional experience (2+ years) in RTL design for FPGA or ASIC
• Expert SystemVerilog development skills with a thorough understanding of the language 
• Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
• Skilled in network communications, processing pipelines, and/or machine learning
• Working knowledge of Python and/or C++
• Comfortable in a Linux environment
• Strong verification experience
• Familiarity with AMD Vivado is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Who we are

Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.

As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.

What you will be doing

As a Principal Electrical Engineer at Neros, you are the chief technical authority and visionary for our electrical systems. Your primary focus will be on high-level architecture, advanced simulation, and strategic oversight. You will work closely with upper management to define the long-term technical roadmap and collaborate with senior engineers to solve our most complex cross-disciplinary challenges. This role requires a unique blend of deep academic knowledge and practical applied expertise to ensure our designs are innovative, robust, and aligned with company goals.

Responsibilities

• Define the overall electrical architecture for new systems, translating stakeholder needs into actionable hardware requirements
• Lead the technical direction of the company through high-level analysis, simulation, and block diagramming
• Serve as the final technical sign-off authority on all major design decisions, V&V plans, and product releases
• Mentor and guide Electrical Engineers, fostering technical excellence and professional growth within the team
• Work with stakeholders and management to sign off on system requirements and ensure technical feasibility
• Provide expert-level technical solutions to complex, multi-disciplinary problems across the organization
• Clearly communicate architectural vision and technical strategy through comprehensive documentation and presentations

You should have the following

• Master of Science or PhD in Electrical Engineering or a related field
• 10+ years of distinguished experience in electrical hardware design and architecture
• Recognized expert in a relevant technical domain (e.g., power electronics, RF design, system architecture, high-speed digital design)
• Proven experience in defining system architecture from the ground up and translating high-level requirements into detailed technical specifications
• Experience with Design for Manufacturing (DFM), Design for Test (DFT), and EMC/EMI
• Exceptional leadership and mentoring abilities, with experience guiding senior-level engineers
• Strategic thinker with outstanding communication skills, capable of influencing both technical teams and executive leadership

Nice to have

• Deep expertise using Ansys or other multi-physics simulation tools to model complex system interactions and drive fundamental architectural decisions
• A background in IC design, verification, or architecture, with experience in the ASIC or FPGA development lifecycle
• System-level expertise in RF and wireless technologies, including architecting products using LoRa or similar technologies, considering antenna design, and overall system signal integrity of RF systems
• Mastery of high-speed digital design principles, with a history of architecting systems involving high-speed interfaces for digital video or data
• Experience developing technology roadmaps and making trade-off decisions between different silicon vendors and platforms
• Knowledge of system modeling languages or environments like MATLAB/Simulink

US Salary Range

$180,000 - $250,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.

We’re an equal opportunity employer. We welcome all applicants without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Who we are

Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.

As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.

What you will be doing

We are seeking a highly skilled CODEC Video Compression Engineer/Developer to build low cost FPV digital video, similar to DJI 04.

They will design, optimize, and implement low-latency advanced video compression algorithms while maintaining high visual quality, for real time video streaming application. You will work closely with cross-functional teams to deliver high-quality, low-latency wireless video. This role blends deep knowledge of video processing, mathematics, and software/hardware optimization to enable video transmission with minimum latency and reduced bandwidth usage.

Responsibilities

• Design and implementation of dual CPU/GPU hybrid video compression encoder architecture that can seamlessly combine SW and HW encoding engines
• Design, develop, and optimize video compression algorithms in C/C++, Assembly, Rust or similar languages
• Implement and optimize encoder/decoder pipelines for real-time applications
• Analyze and improve codec performance for speed, quality, and efficiency across CPU, GPU
• Perform error handling
• Conduct performance benchmarking, debugging, and quality assurance testing: Develop and use objective and subjective metrics to evaluate codec performance
• Collaborate with hardware and software teams to integrate CODEC solutions into products, using high-level synthesis, or FPGA/ASIC design flows
• Stay updated on emerging video standards, compression techniques, and industry trends

You should have the following

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field
• Solid understanding of video compression theory, motion estimation, transform coding, MC DCT, VBSMC, entropy coding, and rate control
• Codec implementation experience in developing actual software and hardware that encodes and decodes video data according to a specific compression format
• System Verilog experience (HLS/C++)
• Solid understanding of video compression standards (H.264, H.265/HEVC, H.266, VP9, AV1) and rate control algorithms
• Experience with hardware implementations using dedicated chips (FPGAs, ASICs, DSPs), and hybrid implementations using software for control logic with hardware accelerators GPUs (NVENC, NVDEC). Experience with GPU acceleration (CUDA, Vulkan, OpenCL)
• Strong proficiency in C/C++ and experience with SIMD optimizations (SSE, AVX, NEON)
• Front-end development for ****control of performance-critical code
• Experience with multithreaded programming and performance profiling tools, debugging, and performance optimization
• Excellent problem-solving skills and ability to work in a collaborative environment

Nice to have

• Backend development (FFmpeg framework, GStreamer)
• Knowledge of container formats (MP4, MKV, MPEG-TS)
• Experience with ML–based video enhancement or compression

US Salary Range

$120,000 - $220,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.

We’re an equal opportunity employer. We welcome all applicants without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Proto is accelerating the world's transition to an open economy with products that increase access and independence for everyone. We're building Bitkey, a simple and safe self-custody bitcoin wallet that will put customers in control, as well as hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We're developing these products in the open - you can read more about them at bitkey.build and mining.build. Within Proto, our Bitcoin Products team delivers the product and go-to-market strategy, software, firmware, and custom silicon needed to make Bitkey and our ambitious mining initiatives a reality. Come build the future of money with us!

The Role

We are looking for an ASIC Validation Engineer to help bridge the gap between custom mining silicon design and real-world operation. In this highly hands-on, lab-focused role, you'll work closely with ASIC designers and system engineers to debug issues, build test infrastructure, and generate the data needed to enable rapid design iteration and system-level development.

You Will:

• Bring up new silicon on bench platforms, evaluation boards, and system hardware
• Debug issues across ASIC, board, firmware, and system interactions
• Develop bench tests, scripts, and tools to exercise silicon features and collect data
• Build and maintain test setups (lab automation, instrumentation, fixtures, scripts)
• Partner with ASIC designers to validate functionality and root-cause failures
• Work with system engineers to ensure silicon performs correctly in target system environments, including mining systems
• Generate and analyze data to support design decisions, characterization, and bring-up
• Create lightweight, reusable test workflows and documentation for the broader team
• Support early manufacturing efforts with practical validation and debug, as needed
• Travel up to 20% to the labs in Oakland, CA or Toronto, Canada

You Have:

• Bachelor's degree in Electrical Engineering or related field
• 4+ years of experience in silicon validation, hardware test, or related roles
• Strong hands-on experience in a lab environment (bench bring-up, debugging, instrumentation)
• Solid understanding of digital systems and basic analog concepts
• Experience writing scripts or tools (Python preferred) for test and data analysis
• Comfortable debugging issues that span multiple layers (ASIC ↔ board ↔ system)
• Clear communication skills and ability to work closely with cross-functional teams

Preferred:

• Experience with ASIC or FPGA bring-up and validation
• Familiarity with common interfaces (SPI, I2C, JTAG, UART, etc.)
• Experience using lab equipment (oscilloscopes, logic analyzers, power supplies, etc.)
• Exposure to high-performance, power-dense systems (e.g., mining ASICs, accelerators, or similar)
• Experience building test automation or internal tooling
• Familiarity with data analysis and visualization

Nice to Have

• Experience working with early silicon / first bring-up environments
• Exposure to manufacturing test or ATE
• Experience working on systems with tight power, thermal, and performance constraints

Why This Role Matters

This role enables the team to move fast. By building the right test infrastructure and quickly turning hardware behavior into actionable data, you'll help both ASIC and system teams iterate faster and make better decisions across silicon and mining system development.

We're working to build a more inclusive economy where our customers have equal access to opportunity, and we strive to live by these same values in building our workplace. Block is an equal opportunity employer evaluating all employees and job applicants without regard to identity or any legally protected class. We will consider qualified applicants with arrest or conviction records for employment in accordance with state and local laws and "fair chance" ordinances.

We believe in being fair, and are committed to an inclusive interview experience, including providing reasonable accommodations to disabled applicants throughout the recruitment process. We encourage applicants to share any needed accommodations with their recruiter, who will treat these requests as confidentially as possible. Want to learn more about what we're doing to build a workplace that is fair and square? Check out our I+D page.

While there is no specific deadline to apply for this role, U.S. roles are typically open for an average of 55 days before being filled by a successful candidate. Please refer to the date listed at the top of this job page for when this role was first posted.

Role Overview 

Astera Labs is seeking a Director, Global Talent Acquisition to lead and scale our worldwide recruiting function during a pivotal period of hypergrowth. This is a high-impact leadership role responsible for building and executing the talent acquisition strategy that will fuel our expansion across North America, APAC, EMEA, and India. 

As a key member of the People team, you will own the end-to-end recruiting lifecycle, from executing on the workforce plan and employer branding to team development and operational excellence. You'll partner closely with executive leadership to ensure we attract and hire the world-class engineering and business talent needed to maintain our position as the leader in AI infrastructure connectivity. This role requires a hands-on leader who thrives in fast-paced environments, has deep semiconductor industry expertise, and has a proven track record of building high-performing global recruiting teams from the ground up. 

Key Responsibilities 

Global Talent Acquisition Strategy & Execution 

• Develop and execute a comprehensive global talent acquisition strategy aligned with Astera Labs' aggressive growth objectives and workforce plans 
• Partner with executive leadership and hiring managers to forecast hiring needs, prioritize roles, and deliver against ambitious recruiting targets 
• Build scalable recruiting processes, systems, and metrics to support a rapidly growing organization 

Team Leadership & Development 

• Lead, mentor, and scale a global team of recruiters and recruiting coordinators across North America, APAC, EMEA, and India 
• Establish clear performance expectations, provide ongoing coaching, and foster a culture of excellence, accountability, and continuous improvement 
• Identify and develop future recruiting leaders within the organization 

Semiconductor & Technical Recruiting Excellence 

• Leverage deep semiconductor industry knowledge and networks to source and attract top-tier engineering talent in a highly competitive market 
• Drive innovative sourcing strategies to build robust pipelines for critical technical roles across hardware, firmware, and software disciplines 
• Serve as a trusted advisor to hiring managers on market trends, compensation benchmarking, and competitive intelligence 

Operational Excellence & Employer Branding 

• Implement and optimize recruiting tools, processes, and analytics to drive efficiency and improve candidate experience 
• Partner with Marketing and People teams to strengthen Astera Labs' employer brand and position the company as a destination for top talent 
• Ensure compliance with global hiring regulations and maintain consistency in recruiting practices across all regions 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, or related field 
• 10+ years of progressive talent acquisition experience, including 5+ years in a leadership role managing global recruiting teams 
• Proven experience in the semiconductor or adjacent hardware technology industry 
• Demonstrated success scaling recruiting functions and building teams from scratch in high-growth environments 
• Experience leading distributed teams across multiple geographies (North America, APAC, EMEA, India) 
• Strong understanding of technical roles and the ability to effectively partner with engineering leaders 

Preferred Qualifications 

• Experience at a pre-IPO or recently public technology company during periods of rapid scale 
• Track record of recruiting for highly specialized semiconductor roles (analog/mixed-signal, ASIC, firmware, etc.) 
• Experience implementing or optimizing applicant tracking systems and recruiting analytics platforms 
• Strong executive presence with the ability to influence and build relationships at all levels of the organization 
• Data-driven mindset with experience using metrics to drive recruiting performance and strategic decisions 

Salary range is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

About the Position

We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking, and research infrastructure.

This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. 

If you've spent your career exclusively in PD, this probably isn't the right fit— but if you've worked across the stack, either because you started as an RTL designer and moved into PD, or because you were on a smaller team where you had to wear multiple hats, we'd love to talk.

We're big believers in the ability of tools to improve the productivity, reliability, and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• You have 8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis)
• You don't need to have optimized every last detail of every flow, but you should have broad enough experience across PD that you can own a flow end-to-end and know where the risks are
• Beyond PD, you can read and write RTL and understand how front-end design decisions affect physical implementation—and vice versa; You think about physical design in the context of the overall chip, not just as a downstream consumer of a netlist
• You're interested in using software engineering techniques to improve the hardware design process, and you have experience programming in a high-level language (Python, C++, Haskell, etc.)

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• Have 4+ years practical experience in RTL design and verification
• Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
  • Front-end RTL design and synthesis
  • Back-end physical design
  • Verification (including formal)
• Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

Why Apply Now?

Even if there’s no active posting for your expertise, we’re always on the lookout for exceptional talent to join our future product and team innovations. We are considering resume of all levels. 

• Early connection: Be on our radar for upcoming openings that match your skills
• Show your passion: Tell us how you can contribute to enterprise‑scale AI connectivity
• Stay informed: Receive priority updates on relevant job opportunities at Astera Labs

Who We Want to Meet

We welcome professionals across disciplines, including but not limited to:

• Hardware Engineering (ASIC, mixed‑signal, PCB)
• Firmware & Embedded Systems (CXL, PCIe, DDR)
• Software & Validation (Firmware QA, system validation, diagnostic SW)
• Product & Program Management
• Operations & HR
• Sales, Customer Programs, and Field Applications

Astera Labs champions diversity in technical expertise and career stages from senior engineers and managers to internship candidates across all functions.

Role Overview

Astera Labs is looking for a Senior Principal Engineering Program Manager to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale.

Key Responsibilities

• Program Ownership & Execution

  • Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM
  • Serve as the single point of ownership for assigned ASIC programs
  • Drive program planning, schedules, budgets, resources, and risk management

• Cross-Functional Leadership & Issue Resolution

  • Lead cross-functional teams across design, validation, product, test, firmware, software, and operations
  • Resolve complex pre-silicon and post-silicon issues through strong technical judgment

• Stakeholder Management & Alignment

  • Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders
  • Champion program execution while aligning engineering delivery with business and customer goals

Basic Qualifications

• BS or MS in Electrical, Electronics, or Computer Engineering
• 10+ years of ASIC product development experience in a semiconductor environment
• Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical Design
• Experience delivering ASICs in advanced nodes (<10nm)
• Proven ability to lead in a matrixed, high-pressure environment
• Strong program management skills; familiarity with MS Project, Jira, Atlassian tools, Scrum/WBS

Preferred Qualifications

• 5 or more years of experience as an ASIC Program Manager
• Experience with PCIe, memory, or high-speed data communication ASICs

Salary range is $205,000 to $250,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.

PsiQuantum’s mission is to build the first useful quantum computers—machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. 

Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportation, materials, and other foundational industries. 

Our architecture and approach is based on silicon photonics. By leveraging the advanced semiconductor manufacturing industry—including partners like GlobalFoundries—we use the same high-volume processes that already produce billions of chips for telecom and consumer electronics. Photonics offers natural advantages for scale: photons don’t feel heat, are immune to electromagnetic interference, and integrate with existing cryogenic cooling and standard fiber-optic infrastructure. 

In 2024, PsiQuantum announced government-funded projects to support the build-out of our first utility-scale quantum computers in Brisbane, Australia, and Chicago, Illinois. These initiatives reflect a growing recognition that quantum computing will be strategically and economically defining—and that now is the time to scale. 

PsiQuantum also develops the algorithms and software needed to make these systems commercially valuable. Our application, software, and industry teams work directly with leading Fortune 500 companies—including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical—to prepare quantum solutions for real-world impact. 

Quantum computing is not an extension of classical computing. It represents a fundamental shift—and a path to mastering challenges that cannot be solved any other way. The potential is enormous, and we have a clear path to make it real. 

Come join us. 

Job Summary:

Quantum computing promises to solve many important problems that could never be solved on any conventional computer. At PsiQuantum we’re building a general-purpose silicon photonic quantum computer to tackle these very problems.

PsiQuantum is looking for an experienced data platform engineer who can design, implement and maintain scalable data pipelines that extract, move and transform data across the Photonic Circuits organization. This role optimizes ETL workflows and integrates various data sources (APIs, DBs, streaming systems) and ensures data quality and observability. This role will work closely with the platforms team and the circuit designers, system engineers and validation engineers. The output will enable ease of producing analytics, scaling tape-out and providing well-structured data sets for reporting. Quantum computing requires breakthrough engineering innovations; we expect software solutions that are novel and custom while at the same time, leverage automation and other best practices from the semiconductor industry. Being a startup in an all-new engineering field, the role is expected to be highly collaborative and requires excellent technical skills to execute projects to meet milestones and technical scope.

An ideal Data Platform SW Engineer candidate combines strong SW engineering skills with deep appreciation for semiconductor and chip design EDA toolchains. They are experienced in building scalable data pipelines that ingest and transform data from simulation outputs, layout tools, verification systems, test benches, lab measurements, and manufacturing yield reports. Proficient in Python and SQL, they are comfortable working with large structured and unstructured datasets (netlists, GDS metadata, waveform data, logs) and integrating disparate systems across design, verification, and fabrication environments. They understand the importance of data integrity, traceability, and reproducibility in silicon development, and design pipelines with robust validation, versioning, and auditability. The ideal candidate collaborates effectively with circuit designers, CAD/EDA engineers, verification teams, and manufacturing operations, translating complex engineering workflows into reliable, automated data infrastructure that accelerates design iteration, improves yield analysis, and enables data-driven decision-making across the chip lifecycle.

Responsibilities:

• Key member of the software solutions team responsible for developing and deploying software for test systems, product platforms and manufacturing data management.
• Design, build, and maintain scalable data pipelines that ingest data from EDA tools, simulation frameworks, verification systems, lab equipment, and manufacturing test platforms.
• Develop robust ETL/ELT workflows to transform netlists, layout metadata, waveform data, logs, and yield data into structured, analysis-ready datasets.
• Integrate disparate engineering systems across design, verification, tapeout, and silicon validation environments.
• Ensure data integrity, traceability, and version control across the chip development lifecycle.
• Implement automated validation, monitoring, and observability for pipeline reliability and data quality.
• Optimize performance for large-scale simulation outputs and high-volume manufacturing datasets.
• Collaborate with photonic circuit designers, CAD/EDA/PDK engineers, verification teams, and silicon validation engineers to translate workflow requirements into scalable data solutions.
• Build data models and infrastructure that support yield analysis, failure analysis, PPA (power, performance, area) tracking, and design iteration metrics.
• Maintain secure and compliant data handling practices across on-prem and cloud environments.
• Contribute to internal tooling and automation frameworks to reduce manual data handling and accelerate design cycles.

Experience/Qualifications:

• Bachelors or other advanced degrees in Computer Science or related engineering fields.
• 3+ years of experience building and maintaining production-grade data pipelines or data platforms.
• Use programming languages (Python, SQL) and tools (DataBricks, Apache Kafka, Spark, Airflow) to ensure high-quality, scalable data flow.
• Understanding of software engineering best practices (version control, CI/CD, testing, code reviews).
• Experience working in semiconductor, ASIC/SoC, or photonics design environments.
• Knowledge of HPC environments or high-throughput compute clusters.
• Preference for experience in supporting ML or advanced analytic engineering workflows.
• Experience with complex software development projects for custom test solutions, hardware interfaces, and platform level firmware/software OR experience developing complex experimental systems in the case of recent college graduates.
• Proven team player with an ability to work effectively across departments, sites, time zones.
• Excellent verbal and written communication skills with an ability to communicate effectively to a variety of audiences.
• Strong critical thinking, creative, innovative, analytical, and detail-oriented problem-solving skills.
• Proven track record of impactful results.
• Ability to work independently with limited direction.
• Demonstrated ability to lead and juggle multiple priorities and deliver against a schedule.
• Demonstrated interest in quantum computing.
• Ability to contribute to a fast-paced start-up environment.

PsiQuantum provides equal employment opportunity for all applicants and employees. PsiQuantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.

Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to recruiting@psiquantum.com.

We are not accepting unsolicited resumes from employment agencies.

This role will be on-site 5 days a week in NW Austin.

**Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

Position Overview:

The Transaction Review Specialist (TRS) will be a member of the Transaction Services team. The TR Specialist will be primarily responsible for ensuring every approved consumer transaction is correctly documented in the ecoATM database and meets the required criteria for an approved transaction. The position requires the ability to remain focused while quickly and thoroughly reviewing ecoATM transactions. Accordingly, attention to detail is a must. 

Please note: This position is full time with a 40 hour work week. The role will require a flexible shift schedule with the ability to work nights/weekends. 

Hourly Pay Rate: $18.00 - $20.00/hr

Key Responsibilities: 

• Data entry and editing  
• Review daily customer transaction data to ensure accuracy of information, including but not limited to, state identification fields populated, authorized identification used by customer, IDV agent decision-making regarding customer approval  
• Generate reports for various law enforcement jurisdictions using local database, pdf process, or online forms 
• Review online documentation for potential fraudulent, utilizing provided tools to determine verification of information 
• Running weekly reports for law enforcement dissemination 
• Online article tracking for identified state jurisdictions 
• Review reports and flag suspicious activity; provide verification and communication of identified activity 
• Provide data review and product knowledge support to other departments to ensure optimal kiosk and online customer experience 

Additional Duties: 

• Approve or deny transactions with consumers based off of the requirements for conducting business with ecoATM (ID Verification) 
• Perform timely and accurate verifications, as requested 
• Review real-time devices and accurately detect device condition (PGV) 

Education & Experience 

• High School Diploma/GED or 1+ year experience in retail or fast-paced environment, to include 6+ months of data entry/verification experience required 
• Experience in a call center-type environment a plus 

Knowledge, Skills & Abilities 

• Strong attention to detail and efficiency 
• Ability to handle multiple tasks, ensuring timely completion 
• Must be self-motivated, resourceful  
• Proven ability to work autonomously 
• Proficient in data entry  
• Able to navigate through databases  
• Basic knowledge of MS Office (Word, Excel, Access, Outlook) 
• Effective oral and written communication skills  
• Proven ability to work both independently and as part of a team  
• Timely attendance 
• Able to work a flexible schedule, including evenings and weekends 

This job description is not intended to be all-inclusive. Employee may perform other related duties as assigned to meet the ongoing needs of the organization. 

Senior ASIC Front-End Design Engineer

Summary:

• As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
• Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
• Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
• You will be a trusted self-starter who can work with very little guidance or oversight.
• This position is located in: United States - Remote

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC RTL design and/or architecture experience
• Proven track record with the development of complex SoCs
• Strong understanding of digital design fundamentals and methodologies
• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:

Experience in any of the following areas:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• IP integration (SerDes, controllers, processors, etc.)
• Perl, TCL, C/C++, Make

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

#LI-Remote

Senior ASIC Design Verification Engineer

Summary:  

• As a Senior ASIC Design Verification Engineer, you will be responsible for all aspects of digital SoC verification.
• You will work the architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.
• You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics.
• This position is located in: United States - Remote

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC verification experience
• Strong understanding of ASIC verification fundamentals and industry standard methodologies
• Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
• Experience with the full verification flow, from spec to coverage analysis to gate level sim
• Debugging failures in simulation to root cause problems
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:
Experience in any of the following areas:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• Third party IP (SerDes, controllers, processors, etc.)
• Modular and Reusable Testbench architecture
• Design for re-use of pre and post silicon tests and infrastructure
• Automation of testbench creation, tests, regression, or EDA tools
• Knowledge of SystemC and/or DPI

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

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