At Tenstorrent, we’re redefining compute performance from the ground up by designing CPUs that power the future of AI and high-performance workloads. As a CPU Microarchitecture & Performance Modeling Intern, you’ll help analyze, model, and optimize real processor designs to push efficiency and speed to new limits. If you love figuring out how every cycle, cache, and pipeline stage adds up to performance, this role is for you!

This role is hybrid based out of Toronto, Boston, Austin or Santa Clara (preferred).

Who You Are

• A detail-oriented engineer who loves understanding how CPUs really work — from pipelines and caches to instruction flow and branch prediction.
• Excited to turn theoretical architecture concepts into measurable performance insights.
• Analytical, curious, and eager to explore the trade-offs between power, area, and performance in modern CPU design.
• Comfortable using data and modeling tools to drive real engineering decisions.
• Collaborative and motivated to learn from experienced hardware architects in a fast-paced, hands-on environment.

What We Need

• A co-op or PEY student pursuing a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong foundation in computer architecture and CPU microarchitecture (pipelines, caches, memory hierarchies, branch prediction, etc.).
• Experience or coursework in performance modeling, simulation tools, or workload analysis.
• Familiarity with CPU workloads and performance metrics (IPC, CPI, latency, throughput, etc.).
• Proficiency with Python or other scripting languages for data analysis and automation.

What You Will Learn

• Develop and run CPU performance models to explore architectural trade-offs and identify bottlenecks.
• Conduct CPU workload analysis using real benchmarks and synthetic tests to measure performance efficiency.
• Collaborate with microarchitecture and RTL teams to connect performance data with design decisions.
• Support validation and tuning of CPU pipelines, memory subsystems, and branch prediction logic.
• Automate data collection, visualization, and reporting workflows for performance experiments.
• Contribute to ongoing research on improving CPU design methodologies for next-generation compute architectures.

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is on-site based in Austin, TX; Santa Clara, CA; or Toronto, ON

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills

Join a team that’s redefining how cutting-edge AI silicon gets verified. At Tenstorrent, formal verification isn’t just a checkbox—it’s core to how we ensure correctness at the speed of innovation. As a Formal Verification Intern, help build confidence in hardware designs that power tomorrow's AI systems.

This role is on-site, based out of Austin, Texas

Who You Are

• Strong background in digital design fundamentals and computer architecture.
• Curious about how complex chips work—and how to prove that they do.
• Skilled in SystemVerilog or similar HDL, with exposure to formal tools a bonus.
• Detail-driven, persistent, and ready to tackle hard problems with a logical mindset.

What We Need

• Help write formal properties and assertions for critical hardware blocks.
• Assist with testbench development and automation flows for formal analysis.
• Run and debug formal tools to identify corner-case design issues.
• Collaborate with design and DV teams to integrate formal into the verification process.

What You Will Learn

• Real-world application of formal methods to cutting-edge processor architectures.
• How formal fits into the broader hardware verification strategy.
• Exposure to industry-standard EDA tools and flows (e.g., Jasper, Questa).
• Best practices for scalable, maintainable assertion-based verification.

Our team has built a high-performance RISC-V CPU from the ground up and is committed to building the best AI platform possible. We value collaboration, curiosity, and a passion for solving hard technical problems across software, compute, networking, and semiconductors.

As part of the Platform Architecture team, the Data Movement Architecture Intern will help shape the performance of our next-generation AI, CPU, and heterogeneous platforms. You’ll work closely with architects and software engineers to design, model, and analyze how data movement subsystems impact system behavior and application-level performance.

This role is remote, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO.

Who You Are

• A highly motivated student who enjoys deep technical exploration and performance analysis.
• Curious about how data moves across compute, memory, and networking in complex AI/CPU systems.
• Comfortable interpreting simulation data and evaluating architecture tradeoffs.
• A strong communicator who collaborates well across multidisciplinary teams.

What We Need

• Pursuing an MS/PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• Solid understanding of computer architecture topics such as interconnects, memory hierarchies, and caching.
• Proficiency in C/C++ and scripting languages like Python or Shell.
• Experience with RTL design and simulation.

What You Will Learn

• Designing and optimizing data movement subsystems including CPU controllers, DMA engines, and accelerators.
• Conducting performance exploration for CPU controller features and system-level data movement.
• Performing PPA analysis and developing reduced data movement kernels for modeling and emulation.
• Working with software, RTL, and architecture teams to understand real-world AI/CPU workloads.

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day remote. 

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is hybrid based in Austin, TX

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills

This role entails design and development of scalable infrastructure and software for the verification of high performance CPUs going into industry leading AI/ML architecture. The successful candidate will be responsible for development and automation of many aspects of the verification environment. The person coming into this role will have opportunities such as: writing low-level RISC-V assembly, building complex low-latency multithreaded testbenches, database programming, software testing and release automation, verilog coding and optimization of CPU components, and contributing to open source projects in the RISC-V ecosystem.

This role is on site, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

Responsibilities:

• Build software and scripts for high performance simulation and emulation of CPUs
• Improve verilog for optimal simulation performance and fpga emulation synthesis
• Maintain and enhance the Git infrastructure to support CI/CD, nightly regressions across multiple development platforms
• Build software tools and scripts for design flow automation

Experience & Qualifications:

• Currently working towards a Bachelors program
• Strong programming skills. C++, Python, SystemVerilog preferred.
• Solid experience with the Linux operating system
• Experience with version control. Git preferred.
• Interest in CPUs, hardware design, and/or programming
• Willing to learn and adapt

Join the team building high-performance RISC-V CPU cores at Tenstorrent. As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and performance engineers to ensure our designs meet real-world performance demands. This is a hands-on role that spans simulation, emulation, debug, and analysis.

This role is on-site, full-time (40 hours/week) in Santa Clara, CA or Austin, TX.

Who You Are

• Pursuing a BS, MS, or PhD in EE, ECE, CE, or CS with strong academic performance.
• Experienced with assembly, C/C++, and scripting in Python or Perl.
• Familiar with CPU architecture and performance concepts, including pipelines, memory systems, and branch prediction.
• Comfortable working through complex debug problems in a methodical, detail-oriented way.
  
  

What We Need

• Interns who can create performance test plans and write stimulus to stress real CPU scenarios.
• Engineers who can run simulations and emulations to validate performance metrics.
• Contributors who can bring up and debug workloads ranging from open-source benchmarks to industry-standard suites.
• Teammates who can investigate mismatches between RTL and performance models and help root-cause bottlenecks.
  
  

What You Will Learn

• How CPU performance is measured, validated, and optimized before silicon.
• How performance models, RTL implementations, and debug tools come together in a real chip development workflow.
• Techniques for balancing tradeoffs in microarchitecture to hit performance targets.
• What it takes to collaborate across architecture, design, and post-silicon teams in a high-performance CPU project.

In this role, you will learn Functional verification of high-performance CPUs going into industry leading AI/ML architecture. You will be mentored by and work alongside a group of highly experienced engineers across various domains of the AI chip.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester