Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Mar–May work term, Nov–Jan recruit.
• Summer Term: Aug–Oct work term, Jan–May recruit.
• Fall Term: Oct–Dec work term, Apr–May recruit.

Please note these timelines are for reference only. Actual timelines may vary.

At Tenstorrent, interns don’t just write code—they help shape the future of AI compute. As a Software Compiler Intern, you’ll work with a dedicated mentor and collaborate across software, firmware, hardware, and systems teams. This is a rare chance to work on performance-critical code and gain experience across the full AI stack.

This role is on-site based in Toronto, Canada.

Who You Are

• Pursuing (or recently completed) a degree in EE, CE, CS, or a related field.
• Solid foundation in C/C++ and algorithms; Python skills are a bonus.
• Curious about compilers, ML, parallel systems, or processor architecture.
• Problem-solver who enjoys working across abstraction layers

What We Need

• Contribute to the development of Tenstorrent’s ML graph compiler.
• Benchmark and optimize key ML workloads across hardware/software.
• Build performance analysis tools to inform compiler and runtime design.
• Collaborate with ML and systems teams to co-design across the stack.

What You Will Learn

• Compiler design for machine learning models and workloads.
• End-to-end co-design of software and cutting-edge AI hardware.
• Performance tuning and analysis in a high-performance runtime.
• Real-world ML integration with frameworks and low-level systems.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone. During this internship, you will bridge the gap between academic theory and industry practice  

This role is on-site, full time, based in Belgrade, Serbia.

Who You Are

• You are in your final year of undergraduate study, a recent graduate, or currently pursuing a master's degree in Computer Science or Electronics Engineering. 
• You enjoy tackling complex technical problems and naturally approach them with structured, analytical thinking. 
• You have written hardware in Verilog or VHDL and understand how HDL translates to physical logic. 
• You are genuinely curious about how processors and computer architectures work, not just in theory but at the implementation level. 
• You are comfortable working in C/C++ and can get things done with scripting languages such as Python, Perl, or Tcl. 
• Nice to have: experience in advanced digital hardware and system architecture (e.g., high‑frequency logic, processors/GPUs, SoCs and memory systems, real‑time hardware/firmware) and modern machine learning, including deep learning frameworks and models.

What We Need

• Architecture exploration and modeling.
• Implementation of Tenstorrent IP and SOC RTL logic in Verilog.
• Verification of Tenstorrent's IP and SOC logic using advanced verification methodologies.
• Low-level software development for hardware testing.

What You Will Learn

• Exposure to the complete RTL-to-GDSII flow. 
• Front-End Design & Logic Synthesis: Mastering Verilog/SystemVerilog to translate architectural specs into optimized hardware descriptions.
• Verification Methodologies: Developing robust testbenches and utilizing UVM (Universal Verification Methodology) and/or CocoTb to ensure "bug-free" silicon.
• Performance benchmark and optimizations
• Timing & Power Analysis: Performing Static Timing Analysis (STA) and power optimization to meet aggressive performance targets.
• Sign-off & Tape-out Readiness: Understanding the rigorous checks required to prepare a design for fabrication.

Hiring Timelines

This internship opportunity is available throughout our 2 terms with the following corresponding recruitment cycles:

• Summer/Fall Term: Aug-Jan work term, Apr–May recruit.
• Winter/Spring Term: Jan–June work term, Nov–Dec recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, die-to-die (D2D) interfaces are how we stitch chiplets together into scalable AI and RISC‑V systems, delivering the bandwidth, latency, and power efficiency our architecture demands. As these links push signaling, process, and packaging limits, we rely on robust analog design automation to explore architectures quickly, verify complex corners, and deliver reliable Silicon at scale.

In this role, you will help build and refine automation that our analog designers use every day to design, simulate, and validate D2D PHYs. Your work on flows, scripts, and analysis frameworks will directly impact how fast we can iterate on D2D interfaces, how confidently we can sign them off, and ultimately how Tenstorrent connects and scales its next-generation AI hardware.

This role is hybrid based out of Toronto, Boston, Austin or Santa Clara (preferred). 

Who You Are

• A flexible thinker who is excited by the future of AI and eager to work at the boundary between analog circuits and advanced packaging.
• Strong proficiency in Python code conventions
• A curious and motivated student eager to connect the dots between Analog IC design, Data Analytics, and AI/ML tools.
• Interested in how architectural ideas become silicon products and how automation can accelerate the design cycle.

What We Need

• A co-op or PEY student pursuing a BS/MS/PhD in Electrical Engineering with academic exposure to Analog IC design.
• Interest in or academic exposure to Machine Learning concepts (e.g., data analysis, basic model training, optimization).
• Interest in applying Open Source packages and tools to analog design automation problems.
• Strong analytical thinking and communication skills.

What You’ll Learn

• Analog design challenges and solutions in modern FinFET processes.
• Deploy SW for HW Design Automation
• Collaborate with senior Analog and Design Automation engineers to gain insight into the full ASIC design methodology and how automation drives product success.

Compensation for all interns at Tenstorrent ranges from $35/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We believe the future of computing must be open, which is why our interns don’t just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

The Project Management Office / Office of the CEO exists to improve organizational effectiveness so Tenstorrent can move faster and make better decisions. In practice, that means improving visibility into company priorities and execution, reducing friction in internal operations, and making important information easier to find, use, and act on across the company.

We are looking for an Applied AI Workflow Automation Intern to build AI-powered tools and automations that reduce manual work, connect fragmented systems, and help Tenstorrent operate more effectively at scale. In this role, you will work on real internal workflows across knowledge systems, productivity tools, and business processes, while exploring how LLMs, retrieval, and workflow automation can improve the way work gets done.

This role is hybrid, based out of Austin, TX,  Fort Collins, CO, Santa Clara, CA, or Toronto, ON offices.

Who You Are

• Pursuing a degree in Computer Science, Computer Engineering, Software Engineering, or a related field
• Comfortable building scripts, tools, or lightweight applications in Python or another programming language
• Interested in applied AI, LLMs, agentic systems, workflow automation, or retrieval systems
• Comfortable working with APIs and integrating across multiple tools and systems
• Able to turn ambiguous, messy workflow problems into practical technical solutions
• Excited to work with both technical and non-technical teams

What We Need

• Build and improve AI-driven workflow automation systems for internal teams
• Design and implement automation using Python, APIs, scripts, and LLM-based tools; experience with n8n or Glean is a plus
• Develop and maintain structured knowledge and retrieval systems that support automation and decision-making; experience with RAG is a plus
• Integrate automation into tools such as Slack, Jira, HR systems, ERPs and internal applications

What You Will Learn

• Own a workflow or process area end-to-end by identifying inefficiencies, designing solutions, building them, and iterating
• How to balance automation, reliability, and human judgment
• How to work with stakeholders across operations, engineering, and business systems
• How to implement guardrails, routing logic, and human-in-the-loop review so systems are reliable in real workflows
• How to measure impact through adoption, time saved, performance, and process improvement metrics

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.

We are seeking a candidate with expertise in silicon security engineering. This role involves critical tasks such as threat modeling to identify and mitigate potential vulnerabilities, and designing robust security processors. The ideal candidate will contribute to safeguarding our cutting-edge AI technology.

This role is onsite, based out of Santa Clara, CA.

Who You Are

• Currently pursuing a M.S or Ph.D. degree in Computer Science, Computing Engineering, Electrical Engineering, or a related field.
• Strong background in computer security, verification, or testing.
• Familiar with computer architecture, digital logic design or software development
• Proficiency in programming languages such as RTL or C/C++..

What We Need

• Conduct security analysis of Tenstorrent’s AI solutions.
• Participate in security processor design.
• Do research on advanced security technologies for chiplet based silicons.

What You Will Learn

• Security engineering of cutting edge security processor.
• Security engineering of chiplet based silicon.
• AI-assisted design.

At Tenstorrent, we’re redefining compute performance from the ground up by designing CPUs that power the future of AI and high-performance workloads. As a CPU Microarchitecture & Performance Modeling Intern, you’ll help analyze, model, and optimize real processor designs to push efficiency and speed to new limits. If you love figuring out how every cycle, cache, and pipeline stage adds up to performance, this role is for you!

This role is hybrid based out of Toronto, Boston, Austin or Santa Clara (preferred).

Who You Are

• A detail-oriented engineer who loves understanding how CPUs really work — from pipelines and caches to instruction flow and branch prediction.
• Excited to turn theoretical architecture concepts into measurable performance insights.
• Analytical, curious, and eager to explore the trade-offs between power, area, and performance in modern CPU design.
• Comfortable using data and modeling tools to drive real engineering decisions.
• Collaborative and motivated to learn from experienced hardware architects in a fast-paced, hands-on environment.

What We Need

• A co-op or PEY student pursuing a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong foundation in computer architecture and CPU microarchitecture (pipelines, caches, memory hierarchies, branch prediction, etc.).
• Experience or coursework in performance modeling, simulation tools, or workload analysis.
• Familiarity with CPU workloads and performance metrics (IPC, CPI, latency, throughput, etc.).
• Proficiency with Python or other scripting languages for data analysis and automation.

What You Will Learn

• Develop and run CPU performance models to explore architectural trade-offs and identify bottlenecks.
• Conduct CPU workload analysis using real benchmarks and synthetic tests to measure performance efficiency.
• Collaborate with microarchitecture and RTL teams to connect performance data with design decisions.
• Support validation and tuning of CPU pipelines, memory subsystems, and branch prediction logic.
• Automate data collection, visualization, and reporting workflows for performance experiments.
• Contribute to ongoing research on improving CPU design methodologies for next-generation compute architectures.

Join the team building high-performance RISC-V CPU cores at Tenstorrent. As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and performance engineers to ensure our designs meet real-world performance demands. This is a hands-on role that spans simulation, emulation, debug, and analysis.

This role is on-site, full-time (40 hours/week) in Santa Clara, CA or Austin, TX.

Who You Are

• Pursuing a BS, MS, or PhD in EE, ECE, CE, or CS with strong academic performance.
• Experienced with assembly, C/C++, and scripting in Python or Perl.
• Familiar with CPU architecture and performance concepts, including pipelines, memory systems, and branch prediction.
• Comfortable working through complex debug problems in a methodical, detail-oriented way.
  
  

What We Need

• Interns who can create performance test plans and write stimulus to stress real CPU scenarios.
• Engineers who can run simulations and emulations to validate performance metrics.
• Contributors who can bring up and debug workloads ranging from open-source benchmarks to industry-standard suites.
• Teammates who can investigate mismatches between RTL and performance models and help root-cause bottlenecks.
  
  

What You Will Learn

• How CPU performance is measured, validated, and optimized before silicon.
• How performance models, RTL implementations, and debug tools come together in a real chip development workflow.
• Techniques for balancing tradeoffs in microarchitecture to hit performance targets.
• What it takes to collaborate across architecture, design, and post-silicon teams in a high-performance CPU project.

Our team has built a high-performance RISC-V CPU from the ground up and is committed to building the best AI platform possible. We value collaboration, curiosity, and a passion for solving hard technical problems across software, compute, networking, and semiconductors.

As part of the Platform Architecture team, the Data Movement Architecture Intern will help shape the performance of our next-generation AI, CPU, and heterogeneous platforms. You’ll work closely with architects and software engineers to design, model, and analyze how data movement subsystems impact system behavior and application-level performance.

This role is remote, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO.

Who You Are

• A highly motivated student who enjoys deep technical exploration and performance analysis.
• Curious about how data moves across compute, memory, and networking in complex AI/CPU systems.
• Comfortable interpreting simulation data and evaluating architecture tradeoffs.
• A strong communicator who collaborates well across multidisciplinary teams.

What We Need

• Pursuing an MS/PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• Solid understanding of computer architecture topics such as interconnects, memory hierarchies, and caching.
• Proficiency in C/C++ and scripting languages like Python or Shell.
• Experience with RTL design and simulation.

What You Will Learn

• Designing and optimizing data movement subsystems including CPU controllers, DMA engines, and accelerators.
• Conducting performance exploration for CPU controller features and system-level data movement.
• Performing PPA analysis and developing reduced data movement kernels for modeling and emulation.
• Working with software, RTL, and architecture teams to understand real-world AI/CPU workloads.

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines – they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent’s next-generation RISC‑V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high‑performance computing roadmap.

We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.

This role is hybrid, based in our Boston, MA office.

Who you are

• Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification.
• Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
• Familiar with HDLs such as Verilog/SystemVerilog, and interested in learning Formal verification, Cocotb, and UVM‑based verification methodologies.
• Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl) to automate tasks.
• Detail-oriented problem solver who enjoys debugging complex issues, reasoning about corner cases, and working from specifications.
• Collaborative team member with clear communication skills, able to document work and discuss trade‑offs with RTL, architecture, and validation teams.

What We Need

• Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
• Write and refine verification test plans from architectural and micro‑architectural specifications, with a strong focus on corner cases and coverage.
• Develop constrained‑random and directed tests, run regressions, and triage failures by working closely with RTL designers to root-cause issues.
• Analyze functional and code coverage results, identify gaps, and propose additional tests or checks to drive coverage closure.
• Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time.
• Partner with cross‑functional teams (architecture, design, performance, validation) to align on expected behavior and sign‑off criteria for silicon.
• Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.

What You Will Learn

• End‑to‑end SoC design and verification flow for cutting‑edge RISC‑V and AI accelerator architectures.
• Industry‑standard verification methodologies (SystemVerilog/UVM), including testbench architecture, stimulus generation, and scoreboard/checker design.
• Hands-on experience with simulation, regression, and coverage tools used in large‑scale industrial verification environments.
• How to read and interpret hardware specifications, micro‑architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
• Exposure to high‑performance interconnects, memory controllers, and accelerators, and how they are verified at IP, subsystem, and SoC levels.
• Best practices for collaborating in a silicon development team, including code review, documentation, and cross‑site communication.

USA Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Jan–Apr work term, Sept–Dec recruit.
• Summer Term: May–Aug work term, Oct–Apr recruit.
• Fall Term: Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.

In this role, you will learn Functional verification of high-performance CPUs going into industry leading AI/ML architecture. You will be mentored by and work alongside a group of highly experienced engineers across various domains of the AI chip.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

This role entails design and development of scalable infrastructure and software for the verification of high performance CPUs going into industry leading AI/ML architecture. The successful candidate will be responsible for development and automation of many aspects of the verification environment. The person coming into this role will have opportunities such as: writing low-level RISC-V assembly, building complex low-latency multithreaded testbenches, database programming, software testing and release automation, verilog coding and optimization of CPU components, and contributing to open source projects in the RISC-V ecosystem.

This role is on site, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

Responsibilities:

• Build software and scripts for high performance simulation and emulation of CPUs
• Improve verilog for optimal simulation performance and fpga emulation synthesis
• Maintain and enhance the Git infrastructure to support CI/CD, nightly regressions across multiple development platforms
• Build software tools and scripts for design flow automation

Experience & Qualifications:

• Currently working towards a Bachelors program
• Strong programming skills. C++, Python, SystemVerilog preferred.
• Solid experience with the Linux operating system
• Experience with version control. Git preferred.
• Interest in CPUs, hardware design, and/or programming
• Willing to learn and adapt

Join a team that’s redefining how cutting-edge AI silicon gets verified. At Tenstorrent, formal verification isn’t just a checkbox—it’s core to how we ensure correctness at the speed of innovation. As a Formal Verification Intern, help build confidence in hardware designs that power tomorrow's AI systems.

This role is on-site, based out of Austin, Texas

Who You Are

• Strong background in digital design fundamentals and computer architecture.
• Curious about how complex chips work—and how to prove that they do.
• Skilled in SystemVerilog or similar HDL, with exposure to formal tools a bonus.
• Detail-driven, persistent, and ready to tackle hard problems with a logical mindset.

What We Need

• Help write formal properties and assertions for critical hardware blocks.
• Assist with testbench development and automation flows for formal analysis.
• Run and debug formal tools to identify corner-case design issues.
• Collaborate with design and DV teams to integrate formal into the verification process.

What You Will Learn

• Real-world application of formal methods to cutting-edge processor architectures.
• How formal fits into the broader hardware verification strategy.
• Exposure to industry-standard EDA tools and flows (e.g., Jasper, Questa).
• Best practices for scalable, maintainable assertion-based verification.

• Final-year BSc or MSc student in Computer Science, Software Engineering, Electrical Engineering, or a related technical field
• Strong programming fundamentals in Python, with familiarity in C++ considered a plus
• Interested in backend systems, API design, and how ML models are deployed in production environments
• Curious about performance optimization techniques such as batching, caching, and model parallelism
• Motivated to learn and contribute in a collaborative engineering environment

• Contribute to backend features and APIs that support AI inference workloads
• Assist in deploying, testing, and benchmarking models running on Tenstorrent hardware
• Analyze inference performance and help identify optimization opportunities
• Write clean, maintainable code with guidance from senior engineers
• Collaborate with the team to improve reliability, usability, and performance of the inference server stack

• How end-to-end ML inference is optimized on custom AI hardware
• How scalable backend systems are designed to serve real-world AI applications
• How APIs and infrastructure shape the developer experience for AI workloads
• Practical performance analysis techniques in production-like environments
• How modern AI software stacks integrate models, runtimes, and hardware

Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Mar–May work term, Nov–Jan recruit.
• Summer Term: Aug–Oct work term, Jan–May recruit.
• Fall Term: Oct–Dec work term, Apr–May recruit.

Please note these timelines are for reference only. Actual timelines may vary.

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

As an Intern on our AI Performance & Debugging Tools and Low Level Kernels teams, you will help build the software that reveals how our AI processors behave and how modern neural networks execute on our systems. You will work on runtimes, kernels, and tooling that ship with Tenstorrent hardware so customers can deploy real AI workloads with confidence. We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.

This role is onsite, based in our Belgrade, Serbia office.

Who You Are

• Currently pursuing a Bachelor’s or Master’s degree in Computer Engineering, Computer Science, or a related field.
• Proficiency in C++ or experience with system-level programming.
• Familiarity with Linux-based environments, including shell scripting and debugging tools.
• Basic understanding of computer hardware architecture and system-level programming.
• Interest in performance profiling, debugging, and AI-related workloads.

What We Need

• Build and optimize neural network execution and data movement in C, C++, and Python on our AI/ML chips, focusing on speed, efficiency, and low power.
• Develop and extend our SDK and tools in C++ and Python to provide clear APIs and simple views into performance, hardware use, placement, routing, and power.
• Build and improve developer tools for debugging, performance monitoring, and understanding system behavior, using feedback from engineers and developers.
• Work with hardware and compiler teams to tune system performance while learning low-level programming, and support testing, documentation, and other parts of the software lifecycle.

What You Will Learn

• How state-of-the-art neural networks are mapped, scheduled, and optimized on custom AI accelerators.
• How to design and tune low-level kernels and runtime firmware that directly drive AI-specialized engines and RISC-V cores.
• How to build and extend performance, profiling, and debugging tools used by AI and compiler engineers.
• How to work in Linux-based, system-level environments using C++, Python, shell scripting, and hardware debug tools.
• How to incorporate user and developer feedback into next iterations of performance and debugging tooling.

Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Mar–May work term, Nov–Jan recruit.
• Summer Term: Aug–Sep work term, Jan–May recruit.
• Fall Term: Oct–Dec work term, Apr–May recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The IP Product Team is where deep tech meets big-picture strategy. We’re the bridge between engineering brilliance and real-world impact — defining how our core IP comes to life and gets delivered to customers.

We’re looking for an Intern who loves technology and wants to learn how world-class intellectual property (IP) gets transformed into world-changing products. You’ll collaborate with engineers, product managers, and cross-functional teams to help shape the future of Tenstorrent’s RISC-V CPU and AI IP portfolio.

This role is remote, based out of the U.S. or Canada.

Who You Are

• Currently enrolled in an Engineering, Computer Science, Business, or related undergraduate program.
• Have exposure to engineering concepts or environments — you can follow (and enjoy!) a technical conversation, even if you’re not an engineer yourself.
• Have experience or a strong interest in program management, operations management, especially where technology and strategy intersect.
• A clear and confident communicator who loves translating technical detail into actionable insight.
• Highly organized, curious, and ready to take initiative in a fast-moving environment.
• Excited by semiconductors, RISC-V, AI, and the process of turning cutting-edge ideas into products that scale.
• Skilled in applying AI technology to automate, generate, analyze data.

What We Need

• Support in defining and maintaining product documentation, roadmaps, planning and release materials for Tenstorrent IP.
• Coordinate with engineering and product management teams to ensure alignment on milestones and deliverables.
• Assist in gathering and analyzing data to support product decisions and reporting using AI tools.
• Help manage internal tools and processes for IP lifecycle management and customer documentation.
• Participate in cross-functional meetings to capture action items and help drive follow-up execution

What You Will Learn

• How semiconductor IP is developed, tracked, and released at scale.
• The art and science of program management and operations in the world of RISC-V CPUs, AI and hardware innovation.
• Best practices and applying AI in documentation, communication, and product lifecycle management.
• Deep insights into RISC-V architecture, AI accelerators, and the technology shaping the future of compute.

What You Will Learn:

• Real-world ML benchmarking workflows from model to hardware.
• Performance tuning and optimization techniques.
• How ML applications are tested, validated, and productized.
• Collaboration across software, hardware, and research teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day remote. 

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

As an intern at Tenstorrent, you will experience working on a carefully defined and real engineering project, guided by a dedicated mentor and a manager, and as a part of a team. This role focuses on model training pipelines on the Tenstorrent compiler stack and how neural networks are brought up and optimized on our hardware. We are looking for a minimum of 3 months for this role with the potential for extension to 6 months. 

This role is on-site based in Belgrade, Serbia.

Who You Are

• Possessing or currently pursuing a Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field.
• Strong understanding of neural network fundamentals.
• Proficiency in Python; experience with C++ is a plus.
• Ability to learn and work effectively within a team environment.

What We Need

• Participate in the implementation and validation of model training pipelines on Tenstorrent compiler stack, specifically using PyTorch and JAX.
• Support benchmarking, analysis, and performance optimization of various model architectures.
• Contribute to efforts in scaling out distributed model training under guidance and participate in discussions related to the co-design of Tenstorrent's hardware and software stack.
• Assist in the integration of Tenstorrent software with widely used tools in the machine learning community.

What You Will Learn

• The process of getting neural network models to train correctly and efficiently on our hardware.
• Techniques for benchmarking, analysis, and performance optimization of various model architectures.
• How to scale out distributed model training and participate in hardware–software co-design discussions.
• How Tenstorrent software integrates with widely used tools in the machine learning community and how a cross‑functional engineering team collaborates on real projects.

Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Mar–May work term, Nov–Jan recruit.
• Summer Term: Aug–Oct work term, Jan–May recruit.
• Fall Term: Oct–Dec work term, Apr–May recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

• Enrolled in a Mechanical Engineering or related program (PEY/internship term).
• Comfortable using MCAD tools and standard mechanical lab equipment.
• Organized, hands-on, and ready to learn fast in a lab environment.
• Communicates clearly and pays attention to the details that matter.

• School experience with MCAD software.
• School experience using standard mechanical lab equipment.
• Exposure to thermal or fluid modeling software is an asset.
• Excellent verbal and written communication skills.
• Strong attention to detail and organization skills.

What You Will Learn

• How mechanical design integrates into real-world AI hardware systems.
• Testing techniques for thermal, acoustic, and structural performance.
• Collaboration across electrical, mechanical, and validation teams.
• Best practices in documentation, lab workflows, and system bring-up.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone. 

In this role, you will implement state of art ML models on Tenstorrent hardware using Python and C++, focusing on pushing both accuracy and inference speed. You will work hands-on with Tenstorrent’s open-source software stack (tt-metalium, tt-nn, tt-llk), taking models from framework to silicon and iterating on performance. You will own a well-defined engineering project under the guidance of a dedicated mentor, with direct impact on how real workloads run on our chips. We are looking for a minimum of 3 months for this role with the potential for extension to 6 months. 

This role is onsite, based in our Belgrade office.

Who You Are

• Enrolled in the final year of BSc or MSc studies in Computer Science, Computer Engineering, Software Engineering, Electronics, Math, or a related field.
• Solid coding skills in Python and C++, with a basic understanding of machine learning concepts and frameworks.
• You have a passion for programming, are eager to learn, and enjoy solving complex performance and optimization problems.
• You are collaborative, open to feedback, and excited to work closely with experienced engineers and a dedicated mentor.

What We Need

• Implement functional ML models on Tenstorrent hardware using Python and popular ML frameworks like PyTorch.
• Benchmark, analyze, and optimize the performance of the implemented model's inference using existing tools and coding in C++ and Python.
• Collaborate with experienced engineers to validate the accuracy of implemented models and iterate on improvements.
• Contribute to performance optimization efforts where success is measured by achieving both high accuracy and fast execution (inference) of ML models on Tenstorrent hardware.

What You Will Learn

• How to implement state-of-the-art ML models on Tenstorrent hardware using Python, C++, and popular ML frameworks like PyTorch.
• Techniques for benchmarking, analyzing, and optimizing the performance of ML model inference using existing tools and code in C++ and Python.
• How to use (and potentially debug and fix) Tenstorrent’s open-source software libraries, such as tt-metalium, tt-nn, and tt-llk.
• How to collaborate with experienced engineers, apply various problem-solving techniques, and drive a well-defined engineering project under the guidance of a dedicated mentor.

Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Mar–May work term, Nov–Jan recruit.
• Summer Term: Aug–Oct work term, Jan–May recruit.
• Fall Term: Oct–Dec work term, Apr–May recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Join our Models Infra team, where we build the systems that enable reliable development, testing, and release of AI models on Tenstorrent hardware. This team focuses on automation, CI/CD pipelines, infrastructure, and tooling that power large-scale model validation, benchmarking, and release workflows. We are looking for a minimum of 3 months for this role with the potential for extension to 6 months. 

This role is hybrid based in Belgrade, Serbia.

You will work on real-world infrastructure problems under the guidance of experienced engineers and a dedicated mentor.

Who You Are

• Final-year BSc or MSc student in Computer Science, Software Engineering, Electrical Engineering, or a related field
• Comfortable with Python and scripting; familiarity with Bash is a plus
• Interested in infrastructure, automation, CI/CD systems, and developer tooling
• Basic understanding of Docker and containerized environments
• Curious about how large-scale systems are built, tested, and deployed
• Motivated to learn, take ownership, and contribute in a collaborative environment

What We Need

• Contribute to CI/CD pipelines used for building, testing, and releasing AI software and models
• Help automate workflows around model validation, benchmarking, and reporting
• Work with Docker and containerized environments to improve reproducibility and efficiency
• Assist in maintaining and improving infrastructure used by engineers (e.g. runners, build systems, test environments)
• Write clean, maintainable scripts and tools with guidance from senior engineers

What You Will Learn

• How CI/CD systems are designed and scaled for complex AI workloads
• How infrastructure enables reliable model development and release processes
• Best practices for automation, observability, and system reliability
• How containerization and orchestration are used in production environments

Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Mar–May work term, Nov–Jan recruit.
• Summer Term: Aug–Oct work term, Jan–May recruit.
• Fall Term: Oct–Dec work term, Apr–May recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Join a team shaping the performance of next-gen CPUs and AI/ML chips. As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating with top engineers to optimize some of the most advanced silicon in the world. 

This role is onsite, based out of Austin, TX or Santa Clara, CA.

Who You Are

• Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS
• Solid understanding of logic design, VLSI, and transistor-level concepts
• Familiar with PnR tools, timing analysis, and power optimization techniques
• Comfortable scripting in Tcl, Perl, Shell, or Python

What We Need

• Support key physical design tasks—synthesis, floorplanning, PnR, clocking, timing closure
• Analyze and improve design PPA (Power, Performance, Area)
• Collaborate with front-end, PD, and architecture teams to influence early design decisions
• Explore and implement new flows, tools, or RTL experiments to optimize designs

What You Will Learn

• End-to-end physical design flow—from RTL handoff to final tapeout
• Deep dive into timing, power, EM/IR, and area trade-offs
• Industry-standard tools and techniques for modern chip development
• How top-tier silicon teams operate at scale

Tenstorrent’s Metal Infra team is all about developer happiness—internal and external. As a Release Engineer Intern, you’ll help automate, maintain, and improve the systems behind our open-source Metal stack (tt-metal on GitHub). From CI pipelines to dashboards and build systems, your work will help teams ship faster and smarter.

This role is hybrid, based out of Toronto.

Who You Are:

• Working toward a CS or Engineering degree (or equivalent experience).
• Comfortable writing clean, reusable Python or C++ code.
• Familiar with CI/CD tools and container tech like Docker.
• Detail-oriented, team-minded, and eager to automate the boring stuff.

What We Need:

• Build and maintain automation tools for build, test, and deploy pipelines.
• Collaborate with dev teams to improve delivery workflows and reliability.
• Support monitoring, dashboards, and metrics to drive better decisions.
• Troubleshoot build and release issues and help prevent them long-term.

What You Will Learn:

• How modern CI/CD pipelines power high-performance hardware-software development.
• Infrastructure automation in a hybrid, multi-platform environment.
• Real-world incident response, debugging, and continuous delivery best practices.
• How open-source tools and internal systems come together in production environments.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

During your internship, you will partner with highly skilled engineers, experience many approaches to problem‑solving, and work on a carefully defined engineering project in relation to convolutions and their optimizations for Tenstorrent hardware, guided by a dedicated mentor. We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.

This role is onsite, based in our Belgrade office.

Who You Are

• Enrolled in the final year of BSc or MSc studies in Computer Science, Computer Engineering, Software Engineering, Electronics, Math, or a related field.
• Comfortable with one or more programming languages, including C++ and Python.
• You bring a solid foundation in algorithms and data structures and basic familiarity with machine learning frameworks and concepts.
• You are curious about kernel development, low‑level and tensor optimizations, and performance profiling, and want to deepen your skills in these areas.

What We Need

• Contribute to the design, development, and maintenance of Tenstorrent software components connected to our hardware platform, and implement and optimize kernels for convolution‑based operations.
• Analyze and optimize low‑level code to improve performance and efficiency with a strong emphasis on tensor optimization, and run performance profiling to identify and address bottlenecks.
• Collaborate with machine learning engineers and data scientists to integrate optimized kernels and low‑level routines into machine learning frameworks and pipelines.
• Write unit tests, debug kernel‑level code for stability and reliability, and present your project approach, accomplishments, and findings to the team at the end of your internship.

What You Will Learn

• How to take a well‑scoped engineering project related to convolutions and their optimizations on Tenstorrent hardware from idea to implementation with guidance from a dedicated mentor.
• Hands‑on experience building, optimizing, and profiling kernels for convolution‑based operations and tuning low‑level code for performance.
• Practical skills integrating optimized kernels and low‑level routines into machine learning frameworks and pipelines, and hardening them through testing and debugging.
• How to communicate technical work clearly by sharing your observations, approach, and results with the broader team.

Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Mar–May work term, Nov–Jan recruit.
• Summer Term: Aug–Oct work term, Jan–May recruit.
• Fall Term: Oct–Dec work term, Apr–May recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

As an intern, you will experience how we do engineering for 3-6 months, working on a carefully defined and real engineering project, guided by a dedicated mentor and a manager, and as a part of a team.

This role is on-site, based in our Belgrade office.

• You are a final-year BSc student or higher in Computer Science, Engineering, Math, or a related technical field.
• You have a strong passion for programming and a solid grasp of algorithms and data structures.
• You are proficient in programming languages, particularly Python and C++.
• You are passionate about neural networks and related deep-learning architectures.

• Design and implement Python/C++ APIs in our SDK for AI/ML developers.
• Extend the model-import pipeline to support new operators, tensor shapes, and graph patterns.
• Develop compiler passes (e.g., rewriting, tiling, optimization) using an MLIR-based infrastructure.
• Design logic for scheduling and executing compiled neural networks efficiently on our custom AI hardware.

• Gain practical experience in ML compiler development and MLIR infrastructure.
• Master high-performance programming in C++ and professional API design in Python.
• Understand hardware-software co-design principles for low-latency AI execution.
• Develop tools for performance analysis and visualization (e.g., hardware utilization, power consumption).

Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Mar–May work term, Nov–Jan recruit.
• Summer Term: Aug–Oct work term, Jan–May recruit.
• Fall Term: Oct–Dec work term, Apr–May recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is on-site based in Austin, TX; Santa Clara, CA; or Toronto, ON

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills

As an Acceleration Kernel Developer at Tenstorrent, you will play a crucial role in optimizing low-level workloads, kernel development, and enhancing our software's performance for machine learning applications. You will work closely with a team of highly skilled engineers to ensure that our software operates at peak efficiency, delivering high-quality results to our clients and users.

This role is hybrid, based out of Toronto, Ontario.

Responsibilities:

• Kernel Development: Participate in the design, development, and maintenance of kernel-level software components for our applications. develop and optimize kernels and kernel libraries for efficient machine learning and HPC applications.
• Implementation of tensor compute and tensor data movement optimizations kernels
• Heavy focus on optimizations.
• Low-Level Optimization: Analyze and optimize low-level code to improve the performance and efficiency of our software, with a strong emphasis on tensor optimization.
• Machine Learning Integration: Collaborate with machine learning engineers and data scientists to integrate optimized kernels and low-level routines into machine learning frameworks and pipelines.
• Performance Profiling: Identify performance bottlenecks, conduct performance profiling, and develop strategies to address and resolve them.
• Testing and Debugging: Write comprehensive unit tests, conduct thorough debugging, and ensure the stability and reliability of kernel-level code.
• Infrastructure: Develop infrastructure to analyze functional test and performance test data.
• Documentation: Create clear and concise documentation for code, APIs, and best practices to facilitate collaboration within the team.
• Research and Innovation: Stay up-to-date with the latest developments in kernel development, tensor optimization, and machine learning to propose innovative solutions and improvements.

Experience & Qualifications:

• Currently enrolled in a bachelors degree, or a masters or doctorate program in Computer Science, Software Engineering, Computer Engineering, Engineering Science or a related field.
• A strong understanding of algorithm implementation and low level algorithm optimization.
• Experience with parallel acceleration development, such as parallel algorithms on CPU, or GPU acceleration.
• High degree of proficiency in C/C++ and Python programming languages.
• Familiarity with machine learning frameworks and concepts.
• Strong problem-solving skills and the ability to analyze and debug complex issues.
• Experience with debug, performance profiling and optimization tools.
• Excellent communication and teamwork skills.
• Self-motivated, detail-oriented, and able to work independently as well as in a team.
• Familiarity with infrastructure built with cloud services is a plus (e.g. AWS).

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is hybrid based in Austin, TX

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills