What You Will Learn:

• Real-world ML benchmarking workflows from model to hardware.
• Performance tuning and optimization techniques.
• How ML applications are tested, validated, and productized.
• Collaboration across software, hardware, and research teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This role entails design and development of scalable infrastructure and software for the verification of high performance CPUs going into industry leading AI/ML architecture. The successful candidate will be responsible for development and automation of many aspects of the verification environment. The person coming into this role will have opportunities such as: writing low-level RISC-V assembly, building complex low-latency multithreaded testbenches, database programming, software testing and release automation, verilog coding and optimization of CPU components, and contributing to open source projects in the RISC-V ecosystem.

This role is on site, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

Responsibilities:

• Build software and scripts for high performance simulation and emulation of CPUs
• Improve verilog for optimal simulation performance and fpga emulation synthesis
• Maintain and enhance the Git infrastructure to support CI/CD, nightly regressions across multiple development platforms
• Build software tools and scripts for design flow automation

Experience & Qualifications:

• Currently working towards a Bachelors program
• Strong programming skills. C++, Python, SystemVerilog preferred.
• Solid experience with the Linux operating system
• Experience with version control. Git preferred.
• Interest in CPUs, hardware design, and/or programming
• Willing to learn and adapt

Our team has built a high-performance RISC-V CPU from the ground up and is committed to building the best AI platform possible. We value collaboration, curiosity, and a passion for solving hard technical problems across software, compute, networking, and semiconductors.

As part of the Platform Architecture team, the Data Movement Architecture Intern will help shape the performance of our next-generation AI, CPU, and heterogeneous platforms. You’ll work closely with architects and software engineers to design, model, and analyze how data movement subsystems impact system behavior and application-level performance.

This role is remote, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO.

Who You Are

• A highly motivated student who enjoys deep technical exploration and performance analysis.
• Curious about how data moves across compute, memory, and networking in complex AI/CPU systems.
• Comfortable interpreting simulation data and evaluating architecture tradeoffs.
• A strong communicator who collaborates well across multidisciplinary teams.

What We Need

• Pursuing an MS/PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• Solid understanding of computer architecture topics such as interconnects, memory hierarchies, and caching.
• Proficiency in C/C++ and scripting languages like Python or Shell.
• Experience with RTL design and simulation.

What You Will Learn

• Designing and optimizing data movement subsystems including CPU controllers, DMA engines, and accelerators.
• Conducting performance exploration for CPU controller features and system-level data movement.
• Performing PPA analysis and developing reduced data movement kernels for modeling and emulation.
• Working with software, RTL, and architecture teams to understand real-world AI/CPU workloads.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.

We are seeking a candidate with expertise in silicon security engineering. This role involves critical tasks such as threat modeling to identify and mitigate potential vulnerabilities, and designing robust security processors. The ideal candidate will contribute to safeguarding our cutting-edge AI technology.

This role is onsite, based out of Santa Clara, CA.

Who You Are

• Currently pursuing a M.S or Ph.D. degree in Computer Science, Computing Engineering, Electrical Engineering, or a related field.
• Strong background in computer security, verification, or testing.
• Familiar with computer architecture, digital logic design or software development
• Proficiency in programming languages such as RTL or C/C++..

What We Need

• Conduct security analysis of Tenstorrent’s AI solutions.
• Participate in security processor design.
• Do research on advanced security technologies for chiplet based silicons.

What You Will Learn

• Security engineering of cutting edge security processor.
• Security engineering of chiplet based silicon.
• AI-assisted design.

In this role, you will learn Functional verification of high-performance CPUs going into industry leading AI/ML architecture. You will be mentored by and work alongside a group of highly experienced engineers across various domains of the AI chip.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

Join a team shaping the performance of next-gen CPUs and AI/ML chips. As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating with top engineers to optimize some of the most advanced silicon in the world. 

This role is onsite, based out of Austin, TX or Santa Clara, CA.

Who You Are

• Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS
• Solid understanding of logic design, VLSI, and transistor-level concepts
• Familiar with PnR tools, timing analysis, and power optimization techniques
• Comfortable scripting in Tcl, Perl, Shell, or Python

What We Need

• Support key physical design tasks—synthesis, floorplanning, PnR, clocking, timing closure
• Analyze and improve design PPA (Power, Performance, Area)
• Collaborate with front-end, PD, and architecture teams to influence early design decisions
• Explore and implement new flows, tools, or RTL experiments to optimize designs

What You Will Learn

• End-to-end physical design flow—from RTL handoff to final tapeout
• Deep dive into timing, power, EM/IR, and area trade-offs
• Industry-standard tools and techniques for modern chip development
• How top-tier silicon teams operate at scale

At Tenstorrent, die-to-die (D2D) interfaces are how we stitch chiplets together into scalable AI and RISC‑V systems, delivering the bandwidth, latency, and power efficiency our architecture demands. As these links push signaling, process, and packaging limits, we rely on robust analog design automation to explore architectures quickly, verify complex corners, and deliver reliable Silicon at scale.

In this role, you will help build and refine automation that our analog designers use every day to design, simulate, and validate D2D PHYs. Your work on flows, scripts, and analysis frameworks will directly impact how fast we can iterate on D2D interfaces, how confidently we can sign them off, and ultimately how Tenstorrent connects and scales its next-generation AI hardware.

This role is hybrid based out of Toronto, Boston, Austin or Santa Clara (preferred). 

Who You Are

• A flexible thinker who is excited by the future of AI and eager to work at the boundary between analog circuits and advanced packaging.
• Strong proficiency in Python code conventions
• A curious and motivated student eager to connect the dots between Analog IC design, Data Analytics, and AI/ML tools.
• Interested in how architectural ideas become silicon products and how automation can accelerate the design cycle.

What We Need

• A co-op or PEY student pursuing a BS/MS/PhD in Electrical Engineering with academic exposure to Analog IC design.
• Interest in or academic exposure to Machine Learning concepts (e.g., data analysis, basic model training, optimization).
• Interest in applying Open Source packages and tools to analog design automation problems.
• Strong analytical thinking and communication skills.

What You’ll Learn

• Analog design challenges and solutions in modern FinFET processes.
• Deploy SW for HW Design Automation
• Collaborate with senior Analog and Design Automation engineers to gain insight into the full ASIC design methodology and how automation drives product success.

Compensation for all interns at Tenstorrent ranges from $35/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.