As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

Job Description:
Astera Labs is seeking a proactive and detail-oriented NPI Planner to join our supply chain team. In this critical role, you will coordinate the introduction of new products by collaborating with multiple stakeholders, including business units, engineering teams, and both internal and external customers. This position demands exceptional communication skills, strong project management abilities, and the capacity to excel in a fast-paced environment.

Responsibilities:

• Support New Product Introduction (NPI) for ASICs.
• Develop and maintain detailed product schedules, ensuring alignment with production goals, timelines, and customer delivery requirements.
• Collaborate with cross-functional teams to manage the end-to-end product lifecycle, from concept through launch.
• Monitor production readiness and proactively resolve potential roadblocks to ensure on-time product releases.
• Track hardware requirements and material orders, maintaining alignment with overall product schedules and milestones.
• Execute supply chain functions including material planning, capacity planning, vendor coordination, inventory management, and customer shipment logistics.
• Analyze vendor quotations, lead cost negotiations, and manage purchase order creation and execution.
• Prepare and present reports on project status, risk assessments, and opportunities for process improvement.

Requirements:

• Bachelor’s degree in Engineering, Science, Business, or a related field.
• Strong organizational skills with meticulous attention to detail and the ability to manage multiple tasks effectively.
• Experience in manufacturing operations.
• Excellent analytical, mathematical, and problem-solving capabilities.
• Background in data analysis or analyst roles.
• Proficiency in Microsoft Office Suite (Excel, PowerPoint, Word) or equivalent tools.

 Base salary range is $140,000 to $155,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Position Summary 

As a key member of the Sales team, you will be entrusted with strategic ownership of hyperscale customer accounts. This role is ideal for a results-driven professional who excels in dynamic environments and is motivated to expand their impact within a high-performing organization. You will drive revenue growth, build deep customer relationships, and act as a catalyst for scaling team success—taking initiative, anticipating needs, and executing with precision. In addition to delivering on current revenue goals, you will be responsible for proactively creating and building a robust pipeline of opportunities, ensuring we are well-positioned to capture future revenue targets and sustain long-term growth. Success in this role means not only achieving ambitious targets but also proactively expanding responsibilities and influence across the organization. 

Responsibilities 

• Take ownership of hyperscale customer accounts, driving strategic engagement and growth.
• Proactively identify opportunities to scale processes, expand responsibilities, and support the sales team’s vision for organizational growth.
• Operate with agility and a sense of urgency, consistently delivering results in fast-paced situations.
• Serve as a trusted partner to both customers and internal stakeholders, representing the highest standards of professionalism.
• Demonstrate exceptional accountability, initiative, and follow-through on complex projects.
• Collaborate cross-functionally to ensure seamless execution and alignment with company goals.
• Mentor and inspire peers, fostering a culture of achievement and continuous improvement. 

Traits & Competencies 

• Relentless drive for results and continuous improvement.
• Strategic thinker with the ability to anticipate challenges and opportunities.
• High emotional intelligence and adaptability.
• Strong sense of ownership and accountability.
• Ability to thrive in ambiguity and rapidly changing environments.
• Exceptional communication and influence skills.
• Entrepreneurial mindset with a bias for action. 

Qualifications 

• Bachelor’s degree (Engineering preferred); Master’s degree is a plus
• 8-15 years’ experience in semiconductor or datacenter/connectivity sales or field roles
• Proven track record of winning complex SoC/silicon design wins
• Strong network within cloud service providers and OEMs
• Exceptional leadership, communication, and project management skills
• Entrepreneurial mindset with a customer-first attitude 

Preferred Qualifications 

• Experience selling [specific products or services, e.g., SaaS, hardware, software].
• Knowledge of the Silicon Valley tech ecosystem and key players.
• Experience using CRM software (e.g., Salesforce). 

About the Role

As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.

Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams.

This position is required onsite in San Jose, CA.

Key Responsibilities

• Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms
• Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems
• Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning 
• Serve as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrations
• Interpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutions
• Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on schedule
• Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows
• Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral
• Represent the Leo team in customer technical reviews, design-in engagements, and industry forums

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
• 8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications
• Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
• Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!
• Authorized to work in the US and available to start immediately

Required Experience

• High proficiency in C for embedded firmware development in RTOS environments
• Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
• Proficiency in Python for scripting, test automation, and diagnostic tooling
• Deep hands-on knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
• Experience with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
• Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
• Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
• Experience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines

Preferred Experience

• Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
• Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
• Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
• Experience with server memory performance tuning — latency and bandwidth optimization
• Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus

Compensation

The base salary range for this role is $175,000 – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure?  

We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing and other cross-functional teams to define and deliver competitive silicon, hardware and software solutions. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of technical expertise and market insight within your product domain.  

This is a unique opportunity to play a pivotal role in the success of our Leo Smart Memory Controller. We are scaling our product team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team.   

Based in San Jose, CA or Vancouver, BC, this position requires an in-person presence with travel to customers.  

Key Responsibilities  

• Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback.  
• Lead customer technical engagement: Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design-wins throughout the product lifecycle.  
• Support go-to-market: Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning.  
• Lead product planning: Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch.  

Qualifications  

• Bachelor’s degree in engineering or compute science  
• 5-10 years of experience in product management, technical product marketing, applications or other customer-facing product roles within the semiconductor industry 
• Proven track record of defining and launching successful semiconductor products (switch products are a plus) 
• Deep understanding of high-speed protocols (PCIe/CXL and/or UALink are required; Ethernet and other protocols are a plus) and system architectures used in cloud and AI infrastructure  
• Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products  
• Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner  
• Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment  
• Results-oriented mindset with a focus on driving measurable impact and achieving business objectives  
• Experience working with customers and partners to understand their needs and drive product definition  
• Willingness to travel as needed for customer meetings, industry events, and trade shows  

If you are passionate about driving innovation and shaping the future of data center connectivity through world-class products, we encourage you to apply. Join Astera Labs in unleashing the potential of cloud and AI infrastructure!  

Compensation will be based on leveling and experience. Base Salary Range $210,000 - $255,000

Astera Labs is seeking a strategic and knowledgeable Benefits Manager to join our Human Resources team in San Jose, California. As we continue our hyper-growth trajectory as a leader in AI infrastructure connectivity, this role will be instrumental in designing, managing, and optimizing our global benefits programs that attract and retain world-class talent. 

This is a high-impact position that goes beyond day-to-day benefits administration. You'll serve as a strategic partner to HR leadership, analyzing market trends, ensuring compliance across multiple geographies, and driving initiatives that enhance the employee experience. The ideal candidate brings a global mindset, thrives in a fast-paced environment, and is passionate about building benefits programs that support our rapidly scaling workforce across the US, Canada, Asia, and EMEA. 

Key Responsibilities

Benefits Strategy & Program Management

• Develop and execute a comprehensive global benefits strategy aligned with Astera Labs' growth objectives and talent acquisition goals
• Evaluate and benchmark benefits offerings against industry standards and competitors to ensure market competitiveness
• Lead annual benefits renewal processes, including vendor negotiations and plan design recommendations
• Drive innovation in benefits offerings to support employee wellbeing and position Astera Labs as an employer of choice

Global Benefits Coordination

• Oversee end-to-end coordination of benefits programs across all operating regions, including the Canada, Asia, and EMEA, ensuring consistency, equity, and local compliance
• Serve as the primary point of contact for international benefits brokers, third-party administrators, and in-country HR partners
• Harmonize benefit plan designs across geographies while accommodating regional statutory requirements and cultural expectations
• Maintain a centralized benefits governance framework to ensure transparency, auditability, and scalability across all regions

Retirement Plans (401k) Administration

• Manage the full lifecycle of the company's 401(k) plan, including plan design, vendor management, compliance testing, and annual reporting (Form 5500)
• Partner with the 401(k) plan administrator and investment advisors to ensure the plan remains competitive, compliant, and aligned with employee financial wellness goals
• Oversee employer match programs, vesting schedules, and plan amendments in coordination with Finance and Legal
• Ensure compliance with ERISA, IRS regulations, and Department of Labor requirements; manage plan audits and non-discrimination testing
• Develop and deliver financial literacy and retirement readiness education to help employees maximize their retirement benefits
• Evaluate and expand retirement offerings for international employees, including country-specific pension and provident fund programs

Paid Time Off (PTO) Program Management

• Design, administer, and continuously improve the company's PTO programs, including vacation, sick leave, holidays, parental leave, and other leave of absence policies
• Ensure PTO policies comply with federal, state, and local regulations across all jurisdictions where Astera Labs operates (including California-specific requirements)
• Partner with Payroll and HRIS teams to ensure accurate PTO accrual, tracking, and reporting
• Benchmark PTO offerings against industry peers to maintain competitiveness and support talent attraction and retention
• Develop clear, accessible PTO communications and manager guides to promote consistent policy application across the organization
• Monitor PTO utilization trends and provide data-driven recommendations to HR leadership to support employee wellbeing and workforce planning

Global Benefits Administration & Compliance

• Manage day-to-day administration of health, welfare, retirement, and wellness programs across multiple countries
• Ensure compliance with federal, state, and international regulations (ERISA, ACA, COBRA, HIPAA, and country-specific requirements)
• Partner with external brokers, vendors, and legal counsel to navigate complex regulatory landscapes
• Develop and maintain benefits policies and procedures to support global scalability

Analytics & Communication

• Analyze benefits utilization data, cost trends, and employee feedback to inform strategic decisions and optimize program ROI
• Develop and deliver clear, engaging benefits communications and educational resources for employees
• Lead open enrollment planning and execution, ensuring a seamless employee experience
• Present benefits insights and recommendations to senior leadership

Cross-Functional Partnership

• Collaborate with Finance, Legal, and Payroll teams to ensure accurate benefits accounting and reporting
• Partner with Talent Acquisition to position benefits as a competitive advantage in recruiting top talent
• Support M&A activities and international expansion by assessing and integrating benefits programs

Basic Qualifications

• Bachelor's degree in Human Resources, Business Administration, or related field
• 10+ years of progressive experience in benefits administration and strategy
• Strong knowledge of US benefits regulations and compliance requirements (ERISA, ACA, COBRA, HIPAA)
• Demonstrated experience managing 401(k) plans, including compliance testing, vendor oversight, and employee education
• Hands-on experience administering PTO programs across multiple states, with working knowledge of California leave laws
• Experience managing relationships with benefits brokers, carriers, and vendors
• Proficiency with HRIS and benefits administration platforms
• Excellent analytical skills with the ability to translate data into actionable insights

Preferred Qualifications

• Experience coordinating global benefits across multiple countries, including international retirement and leave programs
• Experience in high-growth technology or semiconductor companies
• Strong project management skills with ability to manage multiple priorities simultaneously
• Exceptional communication and presentation skills with ability to influence stakeholders at all levels

Compensation

Salary range is $140,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

Job Overview

As a Firmware Engineering Director/ Manager, you will lead and scale firmware development efforts for Astera Labs’ SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development.

Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs.

This role supports two leadership levels:

• Firmware Engineering Manager
• Firmware Engineering Director

Key Responsibilities

• Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps.
• Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers.
• Provide technical oversight and architectural guidance without being the primary implementer.
• Partner closely with hardware architecture, RTL design, validation, and systems teams to define HW/SW interfaces, development milestones, and integration plans.
• Drive SoC bring-up readiness, firmware validation strategy, and risk mitigation across pre-silicon and post-silicon phases.
• Establish development processes, coding standards, and quality metrics to ensure predictable and scalable execution.
• Support customer engagements as needed, including escalation handling, technical reviews, and roadmap alignment.
• Communicate status, risks, and tradeoffs clearly to executive leadership and cross-functional stakeholders.
•  Director scope: own multi-team delivery, long-term roadmap planning, hiring strategy, and cross-org alignment across multiple product lines.

Firmware Domains Under Management

Teams under this role may span one or more of the following areas:

• PCIe Firmware: PCIe switch and controller firmware (Gen3+), including link training, enumeration, error handling, and performance optimization.
• Ethernet Firmware: Embedded firmware for high-speed Ethernet systems (100G–400G+), including PHY/MAC interaction and link bring-up.
• UCIe / Chiplet Firmware: Firmware for chiplet-based SoC architectures, including die-to-die interconnect initialization and advanced packaging enablement.

Required Experience

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of experience developing or supporting firmware for SoC, silicon, or systems products in compute, networking, or storage domains.
• 5+ years of experience in a people-management role, leading firmware or low-level software teams.
• Strong understanding of bare-metal firmware, RTOS environments, and firmware development lifecycles.
• Experience managing teams working on complex SoCs and high-speed interfaces such as PCIe, Ethernet, DDR, NVMe, or similar.
• Proven ability to lead execution across ambiguous, fast-moving environments with multiple stakeholders.
• Strong communication skills, executive presence, and customer-facing professionalism.
• Authorization to work in the U.S.

Preferred Experience

• Prior experience managing firmware teams delivering PCIe or Ethernet switch products.
• Experience with UCIe, chiplet architectures, or advanced packaging ecosystems.
• Track record of scaling teams through hiring, onboarding, and mentorship.
• Experience working with or supporting customers during bring-up, deployment, or escalations.
• Participation in industry ecosystems such as OCP or OpenBMC.
• Director level: experience owning multi-program delivery, long-term technical roadmaps, and cross-functional organizational planning.

Astera Labs’ firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems.

Job Description

• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance.
• Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic Qualifications 

• Strong academic and technical background in electrical or computer engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Required Experience 

• ≥3 Years experience leading a team in a “lead by example” manner—planning sprints, assigning tasks based on individuals’ strengths and career aspirations, providing constructive/encouraging feedback, maintaining a “dashboard” view of project status, chipping into shore up gaps in execution as needed.
• ≥5 Years hands-on experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Good understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred Experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Familiarity with PCIe compliance standards and the ability to follow and be involved in compliance and standard consortiums.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, clock recovery and SerDes link budgets.
• Experience with PAM4 SerDes is a huge bonus!

Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle. 

As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers. 

Location - San Jose, CA OR Israel 

Key Responsibilities 

• Product Technical Ownership 

• Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement 

• Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met 

• Lead development of large-scale chips (300-400mm²) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures 

• Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths 

• Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality.  

• Cross-Functional Technical Leadership 

• Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest 

• Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria 

• Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies 

• Work closely with physical design teams on timing closure, power optimization, and backend execution 

• Process Excellence & Organizational Development 

• Establish and reinforce scalable processes, documentation, and handoffs that support company growth 

• Provide structured, data-driven decision-making and maintain a crisp operational cadence across the product line 

• Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration 

• Model steady, calm leadership, particularly in high-stakes or ambiguous situations 

• Shape engineering culture and talent strategy to support Astera's rapid growth trajectory 

Basic Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 

• 15+ years of experience across architecture, silicon design, validation, systems, or related domains 

• Proven track record of developing large-scale chips (300mm²+) through successful tapeout 

• Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures 

• Strong understanding of RTL design, design verification, DFT, and physical design flows 

• Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures 

• Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership 

• Strong communication and executive presence with the ability to influence at all levels of the organization 

Preferred Qualifications 

• Master's degree in Electrical Engineering or Computer Engineering 

• Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures 

• Experience with advanced process nodes (7nm, 5nm, or below) 

• Background in power management, clocking architectures, or high-speed analog integration 

• Experience operating in fast-growing startups or hyper-scale environments 

Key Leadership Competencies 

• Systems Thinking: See the big picture while managing details 

• Emotional Intelligence: Calm under pressure, empathetic, and influential 

• Adaptability: Thrive in ambiguity and fast-changing environments 

• Execution Discipline: Deliver predictable results without sacrificing innovation 

Role Overview 

Astera Labs is seeking a Director, Global Talent Acquisition to lead and scale our worldwide recruiting function during a pivotal period of hypergrowth. This is a high-impact leadership role responsible for building and executing the talent acquisition strategy that will fuel our expansion across North America, APAC, EMEA, and India. 

As a key member of the People team, you will own the end-to-end recruiting lifecycle, from executing on the workforce plan and employer branding to team development and operational excellence. You'll partner closely with executive leadership to ensure we attract and hire the world-class engineering and business talent needed to maintain our position as the leader in AI infrastructure connectivity. This role requires a hands-on leader who thrives in fast-paced environments, has deep semiconductor industry expertise, and has a proven track record of building high-performing global recruiting teams from the ground up. 

Key Responsibilities 

Global Talent Acquisition Strategy & Execution 

• Develop and execute a comprehensive global talent acquisition strategy aligned with Astera Labs' aggressive growth objectives and workforce plans 
• Partner with executive leadership and hiring managers to forecast hiring needs, prioritize roles, and deliver against ambitious recruiting targets 
• Build scalable recruiting processes, systems, and metrics to support a rapidly growing organization 

Team Leadership & Development 

• Lead, mentor, and scale a global team of recruiters and recruiting coordinators across North America, APAC, EMEA, and India 
• Establish clear performance expectations, provide ongoing coaching, and foster a culture of excellence, accountability, and continuous improvement 
• Identify and develop future recruiting leaders within the organization 

Semiconductor & Technical Recruiting Excellence 

• Leverage deep semiconductor industry knowledge and networks to source and attract top-tier engineering talent in a highly competitive market 
• Drive innovative sourcing strategies to build robust pipelines for critical technical roles across hardware, firmware, and software disciplines 
• Serve as a trusted advisor to hiring managers on market trends, compensation benchmarking, and competitive intelligence 

Operational Excellence & Employer Branding 

• Implement and optimize recruiting tools, processes, and analytics to drive efficiency and improve candidate experience 
• Partner with Marketing and People teams to strengthen Astera Labs' employer brand and position the company as a destination for top talent 
• Ensure compliance with global hiring regulations and maintain consistency in recruiting practices across all regions 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, or related field 
• 10+ years of progressive talent acquisition experience, including 5+ years in a leadership role managing global recruiting teams 
• Proven experience in the semiconductor or adjacent hardware technology industry 
• Demonstrated success scaling recruiting functions and building teams from scratch in high-growth environments 
• Experience leading distributed teams across multiple geographies (North America, APAC, EMEA, India) 
• Strong understanding of technical roles and the ability to effectively partner with engineering leaders 

Preferred Qualifications 

• Experience at a pre-IPO or recently public technology company during periods of rapid scale 
• Track record of recruiting for highly specialized semiconductor roles (analog/mixed-signal, ASIC, firmware, etc.) 
• Experience implementing or optimizing applicant tracking systems and recruiting analytics platforms 
• Strong executive presence with the ability to influence and build relationships at all levels of the organization 
• Data-driven mindset with experience using metrics to drive recruiting performance and strategic decisions 

Salary range is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.

Job Description

• Seeking a strong technical leader who has delivered multiple SoC products.
• Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs.
• Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications.
• Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.
• Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.
• Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.
• Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness.
• Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions.
• The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.
• Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.
• Drive a culture of technical excellence, accountability, and continuous improvement.
• Manage resource planning, and vendor/partner relationships.

Basic Qualifications

• Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred.
• ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.
• ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• ≥5 years building high performance Engineering teams and validation methodologies.
• Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.
• Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.
• Strong background in debug methodologies, lab infrastructure, and automation frameworks.
• Excellent communication skills and ability to influence executives and cross‑functional partners.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Preferred Experience

• ≥8 years leading validation teams planning, execution and maintaining project visibility.
• ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.
• Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.

The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

About the Role

We are seeking a highly operational and systems-savvy Director of Accounting Operations to lead and scale our global accounting processes in a fast-growing semiconductor technology company. This leader will own the record-to-report (R2R) function (excluding technical accounting and SEC reporting), along with accounts payable, revenue accounting, and other related accounting operations responsibilities.

This role is ideal for a hands-on, process-driven accounting leader with deep experience in developing teams in large global enterprise environments, process scaling, Oracle ERP, and centers of excellence models. The successful candidate will play a critical role in building a scalable, efficient, and well-controlled accounting organization capable of supporting a dynamic, global business.

Key Responsibilities

• Lead the accounting operations organization, including General Ledger, Intercompany & Consolidation, Accounts Payable, Revenue Accounting, International coordination, and other related areas.
• Develop subject matter expertise and global process ownership disciplines
• Oversee the overall global consolidation process, and ensure preparation of consolidated financial statements are timely, accurate, and in accordance with US GAAP.
• Build and scale the global accounting organization through strategic initiatives aligned with the objectives of the Company and leveraging technology partnering closely with the Finance Transformation and Business Systems teams.
• Partner with external auditors to ensure successful completion of quarter reviews and annual audits.
• Establish and maintain strong internal controls over financial reporting, governance practices, and continuous refinement of policies and procedures.
• Drive a disciplined, predictable, and timely monthly, quarterly, and annual close process.
• Own the design, structure, scalability, and ongoing governance of the chart of accounts (COA).
• Maintain consistency, data integrity, and reporting alignment across legal entities and geographies.
• Drive automation, standardization, and process redesign initiatives across the organization.
• Collaborate with cross-functional business partners to optimize processes and anticipate accounting outcomes and resources to accommodate.
• Build scalable processes that support rapid growth, acquisitions, and evolving business needs.

Leadership & Communication

• Demonstrated leadership capabilities with experience managing direct reports and influencing cross-functional teams.  
• Excellent communication and stakeholder management skills, capable of engaging across all organizational levels.  
• Strong program management skills, including in-depth involvement with stakeholders to execute effectively and produce thoughtful and comprehensive plans
• Highly operational and detail-oriented with a passion for process excellence.
• A systems-forward leader who leverages technology and thinks “automation first”.
• Comfortable working in a fast-paced, evolving environment.
• A strong cross-functional collaborator and business partner.
• A leader capable of balancing control rigor with business agility.

Team Development

• Build, mentor, and develop high-performing accounting teams.
• Foster a culture of operational excellence, accountability, and continuous improvement.

Cross-Functional Collaboration & Stakeholder Management

• Serve as a trusted partner to senior finance and business leaders, communicating progress, risks, and decisions effectively; deliver proactive operational solutions aligned with business objectives.

Qualifications

• 10+ years of progressive accounting experience, including leadership roles in large enterprise or multinational corporations.
• Strong background in accounting operations and controllership functions.
• Deep expertise in Oracle ERP (GL, AP, AR/Revenue, Fixed Assets, etc.).
• Proven track record in system implementations, finance transformations, or ERP optimization initiatives.
• Experience managing global accounting teams and international operations.
• Demonstrated success establishing or managing offshore shared services (outsourced or captive models).
• Strong operational mindset with the ability to drive process discipline and scalability.

Role Overview

Astera Labs is seeking a Director, HR Operations to lead and scale our HR infrastructure during a pivotal period of hypergrowth. This role sits at the intersection of HR strategy, technology, and operational excellence—directing the teams and programs that manage our systems, data, employee services, and immigration functions. You'll lead a high-performing team while setting the vision for a best-in-class HR Operations function that delivers seamless employee experiences and drives efficiency through smart automation and AI-enabled solutions.

As a key leader on the HR team, you will oversee HRIS architecture and system implementations, people analytics, employee services, compliance, and global immigration programs. You'll serve as the Center of Excellence for global HR operations, establishing standards, best practices, and scalable processes across all regions. You'll partner cross-functionally with IT, Finance, Legal, and business leaders to ensure our HR infrastructure scales with the pace of our growth. This is an opportunity to shape how a high-growth semiconductor company operates—bringing strategic leadership, operational rigor, and innovation to the employee lifecycle.

Key Responsibilities

• Leadership & Team Development

  • Lead and develop a high-performing HR Operations team across systems, analytics, employee services, and immigration
  • Set strategic direction and priorities for the function, ensuring alignment with company growth objectives
  • Foster a culture of continuous improvement, accountability, and employee-centric service delivery
  • Partner with HR leadership and executives to shape HR strategy and operational roadmaps

• Center of Excellence for Global HR Operations

  • Serve as the Center of Excellence for HR operations, establishing global standards, policies, and best practices
  • Drive consistency and efficiency across all global locations while accommodating regional requirements
  • Provide guidance and support to regional HR teams on operational matters
  • Lead change management efforts to implement standardized processes and systems globally

• HR Systems & Technology

  • Direct the strategy, implementation, and optimization of HRIS platforms and the broader HR technology stack
  • Oversee system integrations across HR, Finance, and IT to create seamless data flows and reporting capabilities
  • Champion the evaluation and deployment of AI-powered tools to automate workflows, enhance self-service, and improve decision-making
  • Ensure maintenance and integrity of HR records and HRIS data

• HR Analytics, Dashboarding & Insights

  • Oversee the HR analytics function, ensuring leadership receives actionable insights on workforce trends, retention, and organizational health
  • Direct the development and maintenance of executive dashboards that provide real-time visibility into key HR metrics
  • Maintain data governance standards and ensure integrity across all HR systems
  • Guide the development of reporting frameworks that enable data-driven HR and business decisions

• Employee Services & Experience

  • Oversee end-to-end employee services including onboarding, offboarding, and HR support
  • Ensure efficient handling of routine employee queries about HR policies and programs
  • Drive the design and continuous improvement of employee-facing processes to deliver a frictionless, consumer-grade experience
  • Lead initiatives to scale operations globally while maintaining compliance and consistency

• Compliance & Employee Data Management

  • Ensure compliance with all applicable labor laws, regulations, and company policies across all locations
  • Oversee employee data management practices, ensuring accuracy, security, and privacy standards are maintained
  • Direct audits and compliance reviews to mitigate risk and maintain regulatory adherence
  • Partner with Legal to stay current on evolving employment law and implement necessary policy updates

• Immigration & Global Mobility

  • Direct the company's immigration program, ensuring timely and compliant visa processing, transfers, and renewals
  • Manage relationships with external immigration counsel and vendors
  • Optimize policies and processes that support the company's ability to attract and retain global talent

Basic Qualifications

• Bachelor's degree in Human Resources, Business Administration, Information Systems, or related field
• 10+ years of experience in HR Operations or HRIS roles
• 5+ years in a leadership capacity, managing and developing teams
• Proven track record leading end-to-end HRIS implementations (Workday, SAP SuccessFactors, or similar platforms)
• Experience overseeing HR analytics, reporting, dashboarding, and data management functions
• Deep understanding of HR compliance, labor laws, and employee data management best practices
• Experience scaling HR operations teams in high-growth or startup environments
• Familiarity with U.S. employment-based immigration programs (H-1B, PERM, green card processes)

Preferred Qualifications

• Experience in the semiconductor or technology hardware industry
• Hands-on experience deploying AI or automation tools within HR processes
• Background in employee services transformation and shared services models
• Strong program management skills with experience directing complex, cross-functional initiatives
• Experience supporting global workforce operations across multiple regions and establishing Centers of Excellence
• Excellent executive presence with ability to influence and advise senior leadership

Salary range is $170,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Overview

As a FP&A Business Unit Controller you will be primarily responsible for managing the business partnering relationships for the R&D business units including their annual budgets and quarterly forecast updates and actual performance. The ideal candidate has a strong understanding of financial processes and complex transaction flows with a desire to grow and contribute in a high-growth, fast-paced environment. This role must communicate and organize tasks well to be effective.

Primary Responsibilities

• Establish strong partnership with leadership to help business owners manage their business effectively
• Lead all forecasting and analysis activities for the business owners including: annual plan, quarterly forecast updates and strategic planning
• Develop, analyze, and interpret financial data to evaluate operating results against budget and profitability metrics
• Provide analytical insights, assess risks, and guide senior leadership in strategic decision-making
• Collaborate with Corporate Finance on various projects as needed
• Provide business analysis and support where needed

Qualifications

• 8+ years experience in FP&A and business partnering, preferably in semiconductor or other manufacturing
• Excellent financial modeling and business partnering skills
• Strong analytical and problem solving skills
• Great organization and communication skills, able to work effectively with the business to meet deadlines
• Familiarity with basic GAAP concepts (revenue recognition, accruals, capitalization vs expense)
• Advanced Excel skills
• Familiar with Oracle planning tools
• Strong understanding of financial transaction flows and financial reporting
• Strong feeling of ownership over business processes and desire to improve and make them more efficient
• Bachelor’s degree in Finance or related field

Salary range is $150,000 to $200,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.

Overview
This role will be reported to the Sr. Cost Accounting and Inventory Manager and will be primarily responsible for overseeing and managing Astera Labs’ cost accounting processes, ensuring accurate financial reporting and providing insights to support business decision-making. The ideal candidate has semiconductor experience and a strong understanding of GAAP and internal controls structures.

Responsibilities
• Develop, implement, and maintain product cost accounting frameworks, cost accounting systems, processes, and internal controls to support a growing and evolving product portfolio. 
• Own the month-end close process for cost accounting, including preparation of journal entries and reconciliations related to cost of sales, inventory, manufacturing variances, overhead absorption, accruals, reserves, and cost allocations. 
• Lead detailed analysis of product costs, including material costs, subcontractor manufacturing costs, and other direct and indirect manufacturing costs. 
• Analyze and monitor manufacturing and inventory variances, and partner with Business Operations to identify cost drivers, trends, and opportunities for improvement. 
• Manage and enhance the standard cost process, including cost roll-ups, BOM/routing validation, cost component review, and quarterly standard cost updates; ensure standard costs accurately reflect current product structures and manufacturing assumptions. 
• Partner cross-functionally with Operations, Supply Chain, Engineering, and FP&A to evaluate the cost impact of new products, manufacturing process changes, supplier changes, and manufacturing transitions.
• Support new product introduction (NPI) and lifecycle cost management by reviewing initial product cost assumptions, validating costed BOMs, and ensuring timely setup of standard costs in the ERP system. 
• Support gross margin analysis by providing product cost insights, variance explanations, and bridge analyses for forecast, close, and management reporting. 
• Drive cost improvement initiatives by partnering with cross-functional teams to identify and evaluate opportunities for cost reduction and optimization, efficiency improvements, yield enhancement, and supply chain savings.

Qualifications
• 7+ years of experience in Finance or Accounting, including 5+ years of direct experience in product costing, standard cost accounting, and inventory control, preferably in the semiconductor industry. 
• Strong expertise in standard costing, cost roll-ups, BOM/routing structures, inventory valuation, cost of sales, and manufacturing variance analysis. 
• Solid understanding of semiconductor supply chain and manufacturing flows, including subcontract manufacturing, wafer/test/assembly processes, and related cost structures strongly preferred. 
• Thorough knowledge of US GAAP and related inventory and cost accounting principles, including reserves, capitalization, and cost recognition. 
• Excellent organizational, communication, and cross-functional collaboration skills.

Base salary range is $150,000 to $180,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Role Overview

Are you passionate about driving strategic growth through impactful corporate development initiatives in the AI and cloud infrastructure space? Astera Labs is seeking a Manager of Corporate Development to lead and support strategic transactions including acquisitions, investments, and strategic partnerships that will shape the future of AI connectivity.

In this high-visibility role, you will report to the Head of Corporate Development and work closely with cross-functional teams including engineering, product management, and executive leadership to identify and evaluate opportunities that align with Astera Labs' long-term growth strategy. You will be at the forefront of emerging AI infrastructure technologies, developing new business models and driving transactions that accelerate our position as the leader in purpose-built connectivity solutions.

This is a unique opportunity to join a hyper-growth company at the intersection of semiconductors and AI infrastructure, where your work will directly influence strategic decisions and contribute to building the connectivity backbone powering the next generation of data centers.

Key Responsibilities

• Strategic Transaction Leadership

  • Lead and support corporate development transactions through all phases of the transaction lifecycle, from target identification through close
  • Partner with executive and engineering leaders to evaluate opportunities that address strategic gaps and conduct build/buy/partner analysis
  • Lead deal-oriented project management throughout the entire deal lifecycle, ensuring timely execution and stakeholder alignment

• Financial & Strategic Analysis

  • Conduct detailed financial analyses including valuation, pro forma modeling, and investment assessments to evaluate deal alignment
  • Develop executive presentation materials to provide recommendations to the leadership team and board
  • Research adjacent and new market opportunities, including opportunity sizing, target landscaping, and competitive analysis

• Cross-Functional Collaboration & Integration

  • Collaborate with cross-functional teams to drive diligence and validate key assumptions and value drivers
  • Oversee post-merger integration to ensure deals deliver long-term success and structural enhancement for the company
  • Define and continually enhance the company's strategy to acquire new business opportunities and partnerships

• Market Intelligence

  • Develop deep expertise in emerging AI infrastructure technologies, companies, and business models
  • Monitor industry trends and competitive dynamics to inform corporate development strategy

Basic Qualifications

• Bachelor's degree in Business Administration, Electrical Engineering, Computer Science, or related field
• 5+ years of experience in corporate development, investment banking, private equity, venture capital, or related roles
• Experience in the semiconductor, high-tech, or AI infrastructure industry
• Demonstrated experience leading strategic transactions and working with executive leadership
• Strong analytical skills with expertise in valuation, financial modeling, and strategic analysis
• Excellent communication and presentation skills with the ability to convey complex concepts clearly to diverse audiences

Preferred Qualifications

• MBA or advanced degree
• Direct experience with M&A transactions in the semiconductor or data center infrastructure space
• Knowledge of AI/ML infrastructure, PCIe, CXL, or Ethernet technologies
• Proven ability to collaborate effectively across engineering and business functions
• Experience with post-merger integration planning and execution
• Willingness to travel as needed for deals, company training, industry events, and conferences

Salary range is $140,400 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description: 

As an Astera Labs Early Career Product Application Engineer, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products. 

Basic Qualifications 

• Strong academic and technical background in electrical engineering.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!  

Required Experience  

• Technical ownership of issue resolution
• Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.  
• Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences. 

Preferred experience 

• Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment. 
• Development/support for PCIe or Ethernet Switch or Retimer products. 
• PCIe compliance testing methodology and troubleshooting. 
• Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages. 
• Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc. 

The base salary range is $104k USD - $150k USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Role Overview As a Sr. Principal DSP Architect, you will be the technical visionary leading the definition and development of next-generation Digital Signal Processing (DSP) architectures. Your focus will be on high-speed PAM4 (Pulse Amplitude Modulation 4-level) systems and coherent/direct-detect optical transceivers. You will bridge the gap between theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond.

Key Responsibilities

• Architectural Leadership: Lead the definition of DSP micro-architecture for high-performance ASICs, focusing on low-power, high-throughput data paths.
• Algorithm Development: Design, model, and simulate advanced DSP algorithms for:
• Adaptive Equalization (FFE, DFE, MLSE).
• Forward Error Correction (FEC).
• Clock and Data Recovery (CDR).
• Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) compensation.
• Modeling & Simulation: Develop bit-accurate and performance-accurate models using Python, MATLAB, or C++ to validate architectural choices against Bit Error Rate (BER) targets.
• Cross-Functional Collaboration: Work closely with Analog Mixed-Signal (AMS) designers to optimize the ADC/DAC interface and with RTL teams to ensure power-efficient hardware implementation.
• Performance Trade-offs: Conduct rigorous Power, Performance, and Area (PPA) analysis to balance complex DSP requirements with the thermal and size constraints of optical modules (e.g., QSFP-DD, OSFP).
• Standards Contribution: Represent the company in industry standards bodies (IEEE 802.3, OIF) to influence future optical communications protocols.

Required Qualifications

• Education: PhD or MS in Electrical Engineering, Communication Theory, or a related field.
• Experience: 12+ years of experience in DSP design, specifically for high-speed SerDes or optical communications.

Technical Deep Dive:

• Expertise in PAM4 signaling and the associated challenges (non-linearity, SNR requirements).
• Deep understanding of Digital Filter Design (FIR, IIR) and adaptive signal processing.
• Experience with high-speed ADC/DAC architectures and their impact on DSP performance.
• Tooling: Proficiency in MATLAB/Simulink, Python (NumPy/SciPy), and SystemC.
• Silicon Success: A proven track record of taking complex DSP architectures from concept through tape-out to high-volume production.

Preferred Skills

• Experience with Coherent Optical technologies (QAM, polarization multiplexing).
• Knowledge of Machine Learning applications in DSP for non-linearity compensation.
• Familiarity with hardware description languages (Verilog/SystemVerilog) and the synthesis flow

Role Overview 

Astera Labs is seeking a Senior HR Business Partner to join our People team in San Jose, CA. In this high-impact role, you will partner directly with engineering organizations—serving as a trusted advisor, coach, and strategic partner to engineering leaders, managers, and employees across our technical teams. 

You will bring deep HRBP/Generalist experience, strong employee relations expertise, and substantial knowledge of US labor and employment law to ensure our people practices are both effective and compliant as we scale. This role is critical to supporting the talent strategies, people leader development, and organizational health that enable our engineering teams to deliver world-class AI infrastructure connectivity products. 

Key Responsibilities 

1. Engineering Partnership & Coaching 

• Serve as a trusted partner to engineering people leaders, providing hands-on coaching on people management, team dynamics, and leadership effectiveness 

• Build strong relationships across all levels ensuring employees and managers have accessible, credible HR support 

• Coach engineering managers on performance conversations, career development discussions, feedback delivery, and navigating difficult team situations 

• Help translate the unique challenges of semiconductor product development into practical people strategies 

2. Employee Relations & Compliance 

• Serve as the primary point of contact for employee relations matters across supported engineering groups, handling investigations, performance issues, interpersonal conflict, and conduct concerns with professionalism and care 

• Apply strong knowledge of North America labor and employment law—including federal, state, and local regulations—to advise leaders and ensure compliant, defensible people decisions 

• Conduct thorough, fair, and well-documented workplace investigations, partnering with Employment Counsel and Legal on complex or high-risk matters 

• Proactively identify compliance risks and partner with HR Operations to ensure policies, practices, and manager actions align with legal requirements 

• Stay current on evolving employment legislation and regulatory changes, advising leaders on implications and necessary adjustments 

• Provide clear, empathetic, and legally sound guidance to managers navigating terminations, leaves of absence, accommodations, and other sensitive situations 

3. Talent Strategy & Organizational Effectiveness 

• Partner with engineering leaders on organizational design, role clarity, and team structure to support product roadmap execution 

• Lead talent reviews, retention planning, and succession planning for critical technical roles 

• Support headcount planning and workforce decisions, balancing near-term delivery needs with long-term capability building 

• Identify talent risks and hotspots early, working proactively with leaders to address retention and engagement challenges 

4. Performance Management 

• Guide leaders and managers through performance cycles, calibration sessions, and compensation reviews with fair, consistent, and well-reasoned recommendations 

• Ensure performance management practices are applied consistently and in compliance with company policy and legal standards 

• Partner with Compensation and HR Operations to support equitable pay decisions and address compensation-related concerns 

5. Operational Excellence & Scalability 

• Identify gaps in people processes or manager capability and proactively propose solutions 

• Partner with HR Ops and Centers of Excellence to simplify, standardize, and scale HR practices as the engineering organization grows 
• Operate with an owner's mindset—taking accountability for outcomes, not just recommendations 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, Organizational Development, or related field 

• 8+ years of HR Business Partner experience supporting engineering or technical organizations 

• Demonstrated experience in supporting engineering organizations 

• Strong knowledge of North America employment and labor law, including federal and California state regulations (wage and hour, leaves, accommodations, terminations, harassment/discrimination) 

• Proven track record handling complex employee relations matters, workplace investigations, and sensitive personnel issues 

• Demonstrated ability to coach managers and build trusted relationships with technical employees at all levels 

• Strong judgment and comfort operating in fast-paced, ambiguous environments 
• Clear, confident communicator who can influence and advise engineering leaders effectively 

Preferred Qualifications 

• PHR, SPHR, SHRM-CP, or SHRM-SCP certification 

• Experience supporting organizations through rapid scaling or hypergrowth phases 

• Background partnering with engineering teams 

• Strong analytical skills with experience using people data to inform talent decisions 

• Track record of developing manager capability and building coaching cultures within engineering organizations 
• Experience in AI, data center, or connectivity-focused technology companies 

Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Overview

Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
• Work closely with post-silicon teams to facilitate silicon bring-up and debug.
• Mentor junior engineers to develop their technical skills and expertise.
• Actively contribute to the development and improvement of silicon development processes.
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success.

Required Qualifications:

Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Architecture definition and micro-architecture development
• RTL coding, functional simulation, and synthesis
• Timing closure and gate-level simulation (GLS)
• Design for test (DFT) implementation
• Production experience with advanced CMOS nodes (≤7nm)

Protocols & Integration:

• Deep expertise in at least one high-speed protocol—PCIe , Ethernet, Infiniband, DDR, or similar
• Third-party IP integration and verification.
• Block-level design ownership from architecture through GDS

Tools & Methodologies:

• Proficiency with Cadence and/or Synopsys digital design flows
• Familiarity with UVM-based verification methodologies.
• Silicon bring-up, debug, and failure analysis expertise

Professional Attributes:

• Strong work ethic with the ability to balance multiple priorities in a dynamic environment
• Excellent communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements
• Customer-focused mindset with ability to translate business needs into technical excellence

Preferred Qualifications

• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality

Principal Power and Board Design Engineer 

Overview:
We are seeking a highly skilled and experienced Power and Board Design Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.

Key Responsibilities:

• Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.

• Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance mismatches.

• Develop and implement board-level designs, to meet electrical and mechanical requirements with a deep understanding of PCB layout rules and constraints.

• Implement thermal solutions to maintain optimal operating temperatures for components.

• Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also will be asked to do the same evaluation on overall system level design components.

• Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.

• Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.

• Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.

• Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.

Qualifications:

• Education: Bachelor’s or Master’s degree in electrical engineering or a related field.

• Experience: 8-10 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.

• Technical Skills:

  • Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.

  • Strong understanding of power integrity principles and techniques.

  • Experience with power component selection and vendor collaboration.

  • Hands-on experience with debugging power-related issues using lab equipment.

• Soft Skills:

  • Excellent problem-solving and analytical skills.

  • Strong communication and teamwork abilities.

  • Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Experience with high-speed interfaces such as PCIe, DDR, and USB.

• Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.

• Familiarity with Design for Manufacturability (DFM) considerations.

• Experience in thermal management and reliability analysis.

Why Join Us:

• Work on cutting-edge ASIC designs in a collaborative and innovative environment.

• Opportunity to influence power design strategies and contribute to product success.

• Access to state-of-the-art tools and resources to enhance your skills and career growth.

If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.

Base pay range for this role is $209,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description:

We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic Qualifications:

• Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)
• Experience in working with PCIe Gen3 and above
• Have gone through at least one cycle of full product development life cycle
• Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred
• Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
• Digital and analog circuit level understanding for DUT.
• Excellent team player with great communication skills
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required Experience:

• Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions
• Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.
• Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs
• Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions
• Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred Experience:

• Working with silicon validation teams to ensure device performance meets production requirements.
• Firmware development in C/C++, scripting in Python, or other equivalent programming experience.
• Hands on experience in product/package qualification

Are you passionate about driving business growth for the next generation of data infrastructure with hyperscale and AI platform providers – through customer intimacy, deal negotiation and commercial strategies?

We are seeking a highly proficient and experienced business manager to join our team at Astera Labs. As a key member of our business management team, you will work closely with customers, sales, product marketing, operations and other internal cross-functional teams to accelerate revenue and execute on our deal pipeline for critical opportunities. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of commercial expertise and customer insight across our product portfolio. 

Based in San Jose, CA, this position requires an in-person presence with travel to customers. 

Key Responsibilities 

• Lead customer deal pipeline: Work closely with sales and lighthouse customers secure strategic design-wins and progress pipeline towards design-in and conversion to contracts and purchase orders. 
• Own commercial frameworks: Set, align and approve pricing and commercial terms for key deals and establish consistent pricing strategies and methodologies across products in partnership with product marketing teams.
• Facilitate customer and segment playbooks: Leverage commercial, market and product expertise to support strategy definition and partner with sales to develop playbooks for key customers, segments and regions – covering key elements such as customer insights, relationship mapping, competitive analysis, win/loss analysis solution positioning and negotiation plans. 
• Support business process innovation: Work closely with business functions to enable the next phase of scale through identifying, prioritizing and executing key operational improvements such as new operating procedures, tools or organizational clarity. 

Qualifications 

• Bachelor’s degree in engineering, computer science or business/marketing
• 10+ years of experience in, product marketing, sourcing, supply chain, operations, sales or other customer-facing product roles within the semiconductor industry
• Strong strategic thinking and analytical skills, with the ability to translate customer pain points into innovative solutions (deals, partnerships, or product adoption)
• Proven track record of negotiating and influencing customers, leading to key agreements, contracts or purchase orders
• Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner 
• Broad understanding of high-speed protocols (PCIe is required; Ethernet, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure 
• Results-oriented mindset with a focus on driving measurable impact and achieving business objectives 
• Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment 
• Willingness to travel as needed for customer meetings, industry events, and trade shows 

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description:
At Astera Labs, we are looking for motivated Senior / Tech Lead Post-Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥3 years’ experience testing, supporting or developing complex SoC/silicon products and high-speed IO/SerDes electrical interface for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead.

Required Experience:

• Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3x Ethernet.
• Strong problem-solving skills, ability to solve problems independently.
• Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, and both NRZ and PAM4 signaling.
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
• Familiarity with PCIe or Ethernet especially Electrical Compliance sections
• Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
•  Working knowledge of C or C++ for embedded FW
•  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
•  Working knowledge of common serial data specifications such as I2C, SPI, etc
•  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $148,500 USD - $165,000 USD for Senior level, and $175,000 USD - $195,000 USD for Staff level.

Job Description:

As a Manager of Package Signal & Power Integrity (SIPI) at Astera Labs, you will lead and scale the SIPI engineering function responsible for developing high-performance IC packaging solutions that enable next-generation connectivity products. You will define technical strategy, build and mentor a high-performing team, and drive cross-functional execution from early definition through production. You will partner closely with silicon architecture, package design, PCB board team, hardware validation, manufacturing, and external suppliers (substrate vendors and OSATs) to ensure first-pass success while meeting electrical, cost, schedule, and production goals. You will also drive SIPI methodology evolution, modeling standards, and co-design frameworks across the chip–package–board ecosystem to enable scalable execution across multiple product lines.

Key Responsibilities

• Define and drive the company’s package SIPI strategy across multiple product generations. Ensure robust electrical performance for high-speed interfaces such as PCIe, CXL, Ethernet, and other SerDes protocols (200G/400G+).
• Lead packaging decisions impacting signal integrity, power delivery network (PDN) performance, and substrate design, including selecting packaging platforms, defining substrate stack-up, bump planning, and package architecture to meet high-speed and power integrity requirements.
• Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule.
• Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria.
• Build, mentor, and scale a high-performing SIPI engineering organization, establishing clear priorities, accountability, and technical excellence across concurrent programs while driving talent development and resource planning.
• Represent SIPI leadership in executive reviews and major program milestones, clearly communicating technical strategy, risks, tradeoffs, and execution status to senior leadership and cross-functional stakeholders.

Required qualifications:

• 10+ years of progressive experience in Signal and Power Integrity (SIPI) modeling, analysis, and optimization across the chip–package–board system.
• Demonstrated experience leading teams or technical organizations in IC packaging environments.
• Strong ability to translate business objectives into technical roadmaps and execution plans.
• Deep expertise in EM extraction and modeling tools (e.g., ANSYS HFSS, SIwave, 3DLayout, Keysight ADS, etc.).
• Proven track record delivering high-performance packages such as FCBGA, FCCSP, coreless substrate, chiplet-based, and 2.5D architectures.
• Experience supporting high-speed connectivity products (PCIe, Ethernet, or equivalent SerDes technologies).
• Extensive experience in high-speed S-parameter extraction and system-level SI/PI modeling.
• Expert-level knowledge of PDN design including DC IR drop, loop inductance, target impedance, AC transient behavior, and chip-package-model (CPM).
• Experience driving chip–package–board co-design and system-level validation (eye diagram, ERL, transient response, power-aware SI).
• Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope).
• Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability.
• Experience leading vendor engagements and managing technical execution through production ramp.

Preferred Qualifications:

• Exposure to system-level performance considerations such as skew optimization, channel budget allocation strategy, or power delivery tradeoffs at the package level.
• Background in early package platform evaluation, technology benchmarking, and roadmap trade studies for next-generation connectivity or AI infrastructure products.
• Experience implementing modeling automation, workflow optimization, or data-driven design review processes to improve team scalability and execution efficiency.
• Experience with advanced packaging architectures including chiplet-based designs, 2.5D/3D integration, silicon interposer, bridge-based interconnect (e.g., EMIB-style), and heterogeneous integration platforms.
• Familiarity with UCIe-based die-to-die interconnect integration and associated SI/PI challenges at the package and substrate level.

This position can be hired as a Manager Level or Director Level. The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.

Hardware Lab Assistant – Evening Shift – Contract

Start Date:

5/4/26

Duration:

3-4 months 

Compensation:

Salary will be $37 - $45 /hour. And this is a 3 Month contract position.

Hours:

5PM – 11PM

5 days per week – preferably 4 weekdays and 1 weekend day

We can be flexible around class schedules

Overview

Astera Labs Inc. is seeking a self-driven and proactive Hardware Lab Assistant to join our dynamic team in developing world-class connectivity products for AI infrastructure.

Job Description

This role combines hands-on hardware support for evening test operations with general lab maintenance and infrastructure projects. The ideal candidate is detail-oriented, enjoys working with hardware, and takes pride in maintaining an organized and efficient lab environment. This is an excellent opportunity for someone with an interest in hardware testing and development who is seeking part-time, flexible work hours.

Key Responsibilities

• Support our post-silicon electrical validation team by running remote tests during evening hours
• Collect and organize test data according to team protocols
• Swap hardware, adjust parameters, and initialize data collection for various test configurations
• Monitor test progress and troubleshoot basic hardware issues. Log test results, errors, or anomalies.
• Communicate test statuses and any issues to the engineering team
• Perform general lab cleanup and organization. Sort, label, and organize cables, components, and lab supplies.
• Support various lab infrastructure projects as assigned

Required Qualifications

• Basic understanding of hardware components such as cables, connectors, and PCBAs
• Ability to follow and execute technical procedures and instructions
• Strong organizational skills and attention to detail
• Self-motivated with ability to work independently
• Dependable and punctual with excellent communication skills
• Comfortable asking questions, escalating issues, and addressing errors as needed
• Ability to work evening hours to support test operations
• Ability to lift and transport up to 25 lbs

Preferred Qualifications

• Experience working in a hardware lab environment
• Familiarity with lab equipment (e.g., power supplies, multimeters, oscilloscopes)
• Presently enrolled in an electronics, electrical engineering, or related educational program
• Hands-on experience with soldering or hardware assembly

Why Join Us?

• Gain hands-on experience in a professional hardware lab environment
• Flexible off-hour shifts that work around your schedule
• Opportunity to learn and grow within the hardware development field

Role Overview

Astera Labs is seeking a Senior HR Business Partner to join our People team in San Jose, CA. In this high-impact role, you will partner directly with leaders across our Business and G&A functions—including Finance, Legal, Operations, and other corporate teams—serving as a trusted advisor on all things people strategy.

This is an exceptional opportunity for someone who thrives on working closely with senior stakeholders, navigating real complexity, and helping organizations scale thoughtfully during a period of hypergrowth. 

As a key member of our HR team, you will operate with support from HR Operations and Centers of Excellence while driving meaningful impact on organizational effectiveness, talent development, and leadership capability across the company.

Key Responsibilities

• Strategic Business Partnership
  • Act as a trusted partner to senior leaders, advising on organizational design, leadership effectiveness, workforce planning, and succession planning
  • Help leaders translate business priorities into clear people strategies and actionable plans
  • Build strong, credible relationships where leaders rely on your judgment—not just your availability
• Organizational Effectiveness & Talent Strategy
  • Support org effectiveness, role clarity, and succession planning for critical and leadership roles
  • Partner with leaders on headcount planning and trade-offs, balancing execution needs, and long-term capability building
  • Lead talent reviews, retention planning, and hotspot analysis, ensuring insights turn into action
  • Coach managers and senior leaders on performance management, development conversations, and leadership effectiveness
• Performance, Rewards & Employee Relations
  • Advise leaders through performance cycles, calibration, and compensation reviews, ensuring fair, consistent, and well-reasoned outcomes
  • Handle employee relations matters—including performance issues, conflict, and conduct concerns—using sound judgment and strong documentation
  • Partner closely with Employment Counsel, Legal, and HR Operations on complex or high-risk situations
  • Provide leaders with clear, empathetic, and practical guidance on sensitive people matters
• Operational Excellence & Scalability
  • Identify people or structural risks early and work with leaders to address them proactively
  • Help shape how HR practices scale by partnering with HR Ops and Centers of Excellence to simplify, standardize, or move work to the right owners
  • Take initiative to spot gaps, propose solutions, and drive progress—operating with an owner's mindset

Basic Qualifications

• Bachelor's degree in Human Resources, Business Administration, Organizational Development, or related field
• 8+ years of experience as an HR Business Partner supporting senior leaders in complex, fast-growing technology organizations
• Demonstrated experience partnering across both product/engineering and corporate functions
• Proven ability to operate in ambiguous environments where not everything is fully defined
• Clear, confident communicator who can influence at all levels of the organization

Preferred Qualifications

• Experience in semiconductor, hardware, or AI infrastructure industries
• Track record of supporting organizations through rapid scaling or hypergrowth phases
• Strong analytical skills with experience using people data to drive decisions

Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description:

We are seeking a results-oriented Senior Hardware NPI planner to coordinate with the cross-functions teams and manage cable level and paddle card level NPI planning, supply vs demand, etc. In this role, you will partner with cross-functional teams on the AEC cable and paddle card demand by each SKU, work with the contract manufacturers on the supply to meet our demand.

Key Responsibilities

• Manage consolidated view of demand, supply and build plan for each SKU.
• Interface w/ internal groups and external vendors to plan and procure material needed for the builds.
• Manage builds and FG&WIP at cable and paddle card CMs and coordinate the builds to meet our demand.
• Manage logistics for movement of materials, cable assemblies between involved parties as applicable.
• Identify and resolve any manufacturing/logistics hotspots/roadblocks impacting supply/delivery.

Basic Qualifications:

• Bachelor’s degree in Supply Chain, Business or related field.
• 5+ years of experience in NPI planning in cable/module area.
• Proven track record of cable/module NPI planning management.
• Good communication skills between cross-functions.
• Willingness to travel to suppliers in Asia as needed.
• Must be fluent in English and Mandarin.

Preferred Qualifications:

• Experience in Optics/Electrical modules/AECs is highly desirable.

Overview:
We are seeking a highly skilled and experienced Technical Lead Power Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.

Key Responsibilities:

• Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.
• Design high-efficiency, high-reliability power circuits including:
• Buck / boost / buck-boost converters
• Multiphase regulators
• Hot-swap, protection, and sequencing circuits
• Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance of mismatches.
• Perform power integrity, transient response, stability, and thermal analysis.
• Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also, will be asked to do the same evaluation on overall system level design components.
• Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.
• Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.
• Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.
• Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.

Basic Qualifications:

• Education: Bachelor’s or Master’s degree in electrical engineering or related field.
• Experience: 5-8 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.
• Technical Skills:
• Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.
• Strong understanding of power integrity principles and techniques.
• Experience with power component selection and vendor collaboration.
• Hands-on experience with debugging power-related issues using lab equipment.
• Proficiency with lab equipment (oscilloscopes, electronic loads, spectrum analyzers).
• Soft Skills:
• Excellent problem-solving and analytical skills.
• Strong communication and teamwork abilities.
• Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Familiarity with high-speed interfaces such as PCIe, DDR, and USB.
• Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.
• Familiarity with Design for Manufacturability (DFM) considerations.
• Experience in thermal management and reliability analysis.

Why Join Us:

• Work on cutting-edge ASIC designs in a collaborative and innovative environment.
• Opportunity to influence power design strategies and contribute to product success.
• Access to state-of-the-art tools and resources to enhance your skills and career growth.

If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.

Base pay range for this role is $170,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description

We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
  required, and a Maser’s is preferred.
• ≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in US and start immediately.

Required Experience

• Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
  environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
  generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
  writing assertions, cover properties and analyzing coverage data
• Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.
• Must have prior experience on verification with firmware to control and configure the SerDes and related components.

Preferred Experience

• SW debugging for Mix-Signal based designs.
• Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.
• Experience with FPGA-based verification/emulation.

We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation.  The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues.  The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.

Basic qualifications:

• Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.
• Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required experience:

• Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols.
• High level of proficiency in System Verilog and verification environments.
• Experience understanding software and hardware co-simulation limitations and debug methods.
• Experience in programming and scripting languages (like perl/python/C).
• Currently based locally or open to relocation.

Preferred experience:

• Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.
• Experience in modeling for emulation and prototyping, and/or non-UVM environments

Overview

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 10 + years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, executing validation plans for complex SoC designs. 

Required Experience:

• Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet.
• Familiarity with Electrical Compliance section of PCIe Base Spec and CEM Spec
• Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ, CDR, etc and concepts such as PAM4
• Experience in PRBS testing and optimization of high-speed PCIe data links over short, med, and long channels
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops
• Hands-on experience with signal integrity, especially as it relates to PCIe testing, Channel Loss budgeting, and de-embedding
• Working knowledge of C or C++ for embedded FW, experience using git-based version control such as github
• Familiarity with PCIe standards and both NRZ and PAM-4 signaling
• Working knowledge of common serial data specifications such as I2C, SPI, etc
• Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is $185,000 USD - $230,000 USD. Your base salary will be determined based on your experience and the pay of employees in similar positions. 

Job Description: As a Digital Designer in the DSP SerDes team, you will join a pivotal project to develop advanced high speed SerDes wireline and optical transceivers for AI systems. 

Basic Qualifications:

• Hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5-10 years of experience in digital design for high-speed DSP data path.
• Be proficient in coding System Verilog for complex design blocks.
• Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time.
• Have experience taking design blocks through the full design cycle, from micro-architecture to tapeout.
• Have experience with timing fixes, area and power optimizations, and resolving silicon issues.

Required Experience:

• Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery.
• Code and deliver high-quality RTL to the PD and DV teams.
• Collaborate with the DSP Architecture team to define new features and suggest optimizations for power, latency, and performance.
• Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations.
• Partner with the DV team to root-cause and fix design bugs.

Preferred Experience:

• Experience in digital design for high speed data path in 100G+ PAM4 DSP SerDes
• Experience in designing PAM4 DSP blocks for FFE, DFE, MLSD, and digital timing recovery.

As a Principal Electronics Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. 

Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products.

Key Responsibilities:

• Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.
• Develop comprehensive hardware electrical validation plans using correct test methods and processes.
• Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.
• Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.   
• Rework components on the PCBAs to unblock debugging activities.
• Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.
• Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.
• Support the new designs using knowledge of existing products to de-risk new features and requirements.
• Self-informed of new industry test standards and equipment to introduce modern testing methodologies.
• Specify test equipment, develop test fixtures, help improve hardware lab functions.

Required Skills:

• Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug
• Bachelor degree in EE with 10+ years of experience in hardware test or design
• Define/refine hardware test methodologies and identify appropriate test equipment
• Expert understanding of design and test for power regulators, PDNs, Bode, clock gens
• Ability to produce test description from a schematic design, and execute and document results
• Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM
• Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.
• Automating lab equipment to optimize test processes, Python preferred

Preferred Skills:

• Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.
• EMI/EMC compliance
• Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.
• PLM, Arena or equivalent
• Understanding of the ASIC/silicon product development process

Base salary range is $185,000 USD-$230,000 USD, and will be determined based on the candidate's capabilities and employees in similar positions.

Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.

Key Responsibilities

• Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
• Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
• Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
• Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
• Work with RTL designers to troubleshoot and resolve design issues.
• Drive verification strategy and methodology for SoCs in server and networking applications.

Required Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred).
• 8+ years of experience in SoC verification, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
• Familiarity with verification of switching architectures, including packet processing and forwarding engines.
• Excellent communication skills and ability to work independently with minimal supervision.

Preferred Qualifications

• Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
• Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
• Knowledge of Ethernet/PCIe switching and central buffer architectures.
• Experience with emulation platforms and hardware-software co-verification

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Role Overview

Join Astera Labs as a Technical Lead Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 5+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $160,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

Role Overview

As a Principal Package Thermal & Mechanical Engineer at Astera Labs, you will serve as a technical leader driving the development and modeling of advanced IC packaging solutions that enable next-generation AI and high-performance connectivity systems.

In this highly visible role, you will define and execute thermal and mechanical modeling strategies across the chip–package–board system, influencing package architecture, material selection, and reliability design. You will partner closely with package design, SIPI, silicon, system, and manufacturing teams to ensure robust thermal/mechanical performance and first-pass success.

You will also drive modeling methodologies, correlation strategies, and best-known methods (BKMs), while engaging directly with customers to translate complex simulation insights into actionable system-level solutions.

Key Responsibilities

• Thermal & Mechanical Modeling Leadership
• Define and drive thermal and mechanical modeling strategies for advanced packages (FCBGA, FCCSP, multi-die, and chiplet-based architectures)
• Perform detailed thermal simulations including steady-state and transient heat transfer (conduction, convection, and interface resistances such as TIM1/TIM2)
• Develop and deploy compact thermal models (CTM), reduced-order models (ROM), and DELPHI-based models for system-level integration
• Analyze power density, hotspot behavior, and package-to-system thermal interactions across air and liquid cooling environments
• Perform thermo-mechanical stress/strain analysis including CTE mismatch, viscoelastic material behavior, and deformation
• Predict package warpage across process and use conditions (reflow, underfill cure, board attach, field operation)
• Model solder joint reliability and fatigue using industry standard models
• Package Architecture & Thermal Design Strategy
• Drive package design decisions including material selection (EMC, substrate, TIM, lid/heat spreader), thermal path optimization, and early-stage architecture definition across air and liquid cooling solutions (air, cold plate, CPO/CPC)
• Conduct DOE, sensitivity studies, and worst-case analysis to guide tradeoffs across performance, cost, reliability, and manufacturability
• System Co-Design & Automation
• Partner cross-functionally to drive chip–package–board co-design and resolve system-level thermal/mechanical challenges, including system integration constraints
• Serve as a technical interface for customers and internal teams, translating modeling results into actionable insights and leading design reviews and issue resolution
• Develop and scale modeling methodologies, workflows, and BKMs; mentor engineers and improve efficiency through automation and scripting (Python, MATLAB)

Basic Qualifications

• M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field
• 8+ years of experience in semiconductor packaging with strong focus on thermal and mechanical modeling
• Deep expertise in thermal modeling and simulation, including steady-state and transient analysis, compact thermal modeling (CTM), DELPHI methodology, and system-level thermal integration using tools such as ANSYS Icepak, Flotherm, or equivalent
• Deep expertise in thermo-mechanical modeling and FEA simulation, including stress/strain analysis, warpage prediction, and reliability modeling (BLR/CLR), using tools such as ANSYS Mechanical, or equivalent
• Proven ability to correlate simulation results with lab measurements
• Experience influencing package design and delivering solutions to production
• Strong cross-functional collaboration across package design, SIPI, system, and manufacturing teams

Preferred Qualifications

• Experience with high-power AI / HPC packages and large FCBGA (>50mm)
• Familiarity with advanced packaging technologies:2.5D / 3D integration, Chiplet, CPO/CPC
• Experience with system-level cooling solutions: Liquid cooling, cold plates, immersion cooling
• Knowledge of JEDEC standards and reliability qualification methodologies
• Experience working with OSATs and substrate vendors on thermal/mechanical design optimization
• Proficiency in scripting (Python, MATLAB) for modeling automation
• Exposure to multi-physics coupling (electrical–thermal–mechanical interactions)

 The base salary range is $185,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.

Job Description:

As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products.  You will be working on projects from conception to the final production stage at contract manufacturer.

The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices.  At the same time we welcome candidates with deep experience in smaller areas with the desire to learn.  Depending on your experience, you may be focusing on design/validation or automation/manufacturing.

Key Responsibilities

• Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.
• Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product
• Bring-up newly manufactured boards and develop the first level of software.
• Isolate and perform root-cause analysis of reported failures
• Support new platform software and hardware features
• Coordinate with the hardware engineering team on bring-up schedules and feature delivery
• Participate proactively in design discussions, design review, and project management
• Work independently as well as in team roles, mentor younger team members

Basic Qualifications/Required Experience

• Bachelor’s in CS/CE or equivalent experience.
• 8+ years of Experience in subset of diagnostic, hardware bring-up, test or manufacturing automation
• Knowledge of modern software development 
• Proficiency in Python, C/C++

Preferred experience

• Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing
• Ability to read schematic/layout
• System debug experience
• Embedded programming and good knowledge of OS internals (Linux/Unix)
• Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.
• Experience with DDR5

The base salary range is $203,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we're revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution.

In this highly strategic role, you'll serve as Astera Labs' technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You'll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers exceptional scope for impact—your work will directly enable the rack-scale AI infrastructure that's transforming cloud computing and enterprise data centers worldwide.

Key Responsibilities

• Strategic Leadership & Methodology Development
• Define and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols
• Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality
• Represent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verification
• Drive cross-functional collaboration to influence technical direction across the organization
• Technical Execution & Innovation
• Develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications
• Identify key logic components and critical micro-architectural properties essential for ensuring design correctness
• Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs
• Apply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth
• Develop and maintain scripts to enhance FV productivity and streamline verification processes
• Team Development & Cross-Functional Partnership
• Mentor Principal and Lead Engineers across global sites in advanced formal verification techniques
• Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels
• Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback
• Prepare and deliver customer meetings and executive presentations with minimal supervision

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
• 15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization
• Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification
• Advanced scripting abilities with Python or Perl for automation and productivity enhancement
• Proven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision
• Strong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus
• Entrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards

Preferred Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification
• Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold
• Experience with both bug hunting and static proof verification techniques
• Familiarity with automating formal verification workflows within a CI/CD environment
• Deep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink
• Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)
• Patents or publications in formal verification or hardware verification methodologies
• Track record of recruiting, mentoring, and developing formal verification talent across distributed teams

Salary range is $230,000 to $285,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Education and Experience Requirements

• Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 8-12 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Desired Qualifications

• Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
• Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
• Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
• Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
• Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
• Experience with PAM4 SerDes validation (200G/100G/50G)
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
• Knowledge of Signal Integrity simulation tools
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

As a Senior/Staff Electronics Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. 

Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products.

Key Responsibilities

• Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.
• Develop comprehensive hardware electrical validation plans using correct test methods and processes.
• Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.
• Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.   
• Rework components on the PCBAs to unblock debugging activities.
• Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.
• Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.
• Support the new designs using knowledge of existing products to de-risk new features and requirements.
• Self-informed of new industry test standards and equipment to introduce modern testing methodologies.
• Specify test equipment, develop test fixtures, help improve hardware lab functions.

Required Skills

• Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug
• Bachelor degree in EE with 3+ years of experience in hardware test or design
• Expert understanding of design and test for power regulators, PDNs, Bode, clock generators
• Ability to produce test description from a schematic design, and execute and document results
• Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM
• Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.
• Automating lab equipment to optimize test processes, Python preferred

Preferred Skills

• Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.
• EMI/EMC compliance
• Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.
• PLM, Arena or equivalent
• Understanding of the ASIC/silicon product development process

Role Overview

Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

Job Description

We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
• Familiar with high-speed load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with using Advantest 93k ATE platform.
• Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.
• Experience in running External loopback at wafer sort.
• Familiarity with modern databases

At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite.

Basic Qualifications

• Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.
• 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
• Have a proven track record with defining hardware system constraints and high-speed technology roadmaps.
• Cross-functional design mentality with the electrical design community to develop systems.
• Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.
• Proven track record solving problems independently, preferably as a tech lead.
• Entrepreneurial, open-minded behavior, and can-do attitude.
• Authorized to work in the US and start immediately.

Required Experience

• Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects
• 2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets
• EM modeling of BGA and connector structures
• High-speed SERDES channel simulation, and equalization
• PI simulations with Ansys/Cadence toolsets
• Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
• Working knowledge of PCB fabrication limits and trade-offs
• Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections.
• Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome.

Role Objective

As the gatekeeper of IP Management, Methodology and Quality at Astera Labs, you will lead the strategic development of our AI-powered IP Lifecycle Management and IP Quality Assurance Platform. You won't just run tools; you will architect a scalable, user-friendly system that serves as the foundation for our "AI-first" IP ecosystem. Your mission is to ensure every IP, whether internal or external is easily accessible, physically, logically, and structurally "SOC-ready," preventing late-stage integration breaks that delay tape-outs. Our vision is to revolutionize IP Management and Quality Assurance with an AI-first approach.

The candidate will be responsible for developing the platform, auditing and qualifying internal and external IP (Hard/Soft Macros, PHYs, Memories and standard cells libraries among other IPs). The IPLM and IPQA tools will scale to cover SOC QA and be a key element of the tape out sign-out requirements. The successful candidate will have the right expertise to run all EDA tools, understand the results, challenge the false pass scenarios, and dig into the root cause of real errors. They will work with the vendors or with our internal IP teams to solve the issues.

They will be responsible for ensuring that all IP deliveries are integrable, timing-clean, and manufacturable, preventing "late-stage" SOC breaks caused by inconsistent IP views or structural violations. IPQA will cover all aspects of the design flow starting from Architecture coherence, PPA evaluation, Front-End integration, SDC, RDC, DFT, PD and PDV, Packaging, ESD, Waivers, IP-XACT; and be scalable from the technology foundations, FinFet and Gate-All-Around transistors’ properties, DK/PDK integrity and rule decks from foundries, Standard Cells, Memories, IP, Subsystems and SOC Quality.

Technical Responsibilities

• AI-Driven Automation: Architect and Lead the integration of agentic AI workflows into the IPLM and IPQA platform to automate IP Management, root-cause analysis of false pass scenarios and self-heal real issues.
• Chiplet Readiness: Verify IP compliance with high-speed and high-bandwidth interface standards for heterogeneous integration.
• Cross-View Consistency: Architect automated audits for logical-to-physical consistency across RTL, Liberty, LEF, GDSII, and CDL views, focusing on pin-naming, bus-integrity, and functionality.
• Physical & Sign-off Audits: Perform independent LVS, DRC, and Antenna signoffs using native runsets for 5nm/3nm and beyond nodes.
• Structural & DFT Verification: Validate DFT requirements, including scan-chain integrity, MBIST handshakes, and fault-coverage transparency.
• Power & Timing Integrity: Audit Power Domain (UPF/CPF) consistency and conduct deep-dive Liberty (.lib) audits to identify missing timing arcs or non-monotonic lookup tables. Audit IR-drop/EM (Electromigration) reports to ensure the IP won't cause localized power grid failures.
• Waiver Management: Develop rigorous, automated Waiver Audit Protocol to ensure that provider-cleared violations do not violate Astera Labs' internal sign-off deck requirements.
• Lessons learned from release to release, from generation to generation need to be tracked and checked. Responsible for making sure releases are complete; patches are integrated. Constraints are updated, and documentation reflects the updates including PPA impact.

Required Skills & Expertise

• IP & EDA Expert: Mastery of the full sign-off suite: PrimeTime, Fusion Compiler, Genus, Calibre, Innovus, IC Compiler, SpyGlass, Tessent, Liberate (/MX), PrimeSim. Cross-Tool Consistency expertise is a must.
• Advanced Scripting for Information Systems: Expert in Tcl for tool manipulation and Python for building AI-wrapper layers. Familiarity with SystemVerilog.
• Domain Depth: Deep understanding of FinFET/Gate-All-Around (GAA) properties, Electromigration (EM), and ESD rules. Deep knowledge of Liberty modeling and LEF/DEF physical formats.
• QA Philosophy: A "Detective" mindset with the ability to look past a "green" or “red” report to find false errors and rootcause real ones.
• Management skills: Ability to work with design teams and IP vendors to solve issues in a timely manner.

The base salary range is $175,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions

Role Overview

Astera Labs is seeking a Principal Product Applications Engineer to join our Aries PCIe Retimer team and serve as a critical technical bridge between our customers and engineering organization. As AI infrastructure demands explode, our Aries Smart Retimers are enabling the high-speed, low-latency PCIe connectivity that powers the world's most advanced data centers—and you'll be at the center of that growth.

In this high-impact role, you'll work directly with hyperscalers, OEMs, and system builders to drive successful adoption of our Aries PCIe products. You'll combine deep technical expertise with customer-facing skills to solve complex system-level challenges, create compelling technical documentation, and influence product direction based on real-world customer needs. This is an opportunity to shape how next-generation AI and cloud infrastructure connects and scales.

You'll collaborate cross-functionally with design engineering, validation, sales, and marketing teams while building strong relationships with customers who are defining the future of computing. If you thrive at the intersection of cutting-edge silicon and customer success, this role offers exceptional visibility and impact.

Key Responsibilities

Customer Technical Engagement

• Serve as the primary technical resource for customers during pre-sales evaluation and post-sales deployment of Aries PCIe retimers
• Deliver technical presentations, product training, and demonstrations to customer engineering teams
• Build trusted advisor relationships with key accounts and drive product adoption

System-Level Debug & Validation Support

• Lead root cause analysis and debugging of complex PCIe signal integrity and protocol issues in customer systems
• Support customer lab bring-up, characterization, and validation activities
• Develop and execute test plans to reproduce and resolve customer-reported issues

Technical Documentation & Enablement

• Create application notes, reference designs, and best practices guides for PCIe system implementation
• Develop collateral that accelerates customer time-to-deployment
• Contribute to product documentation including datasheets and user guides

Cross-Functional Collaboration

• Partner with product management and engineering to translate customer feedback into product requirements
• Support sales teams with technical expertise during customer engagements
• Represent the voice of the customer in internal roadmap and feature discussions

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in applications engineering, technical support, or system engineering roles
• Strong understanding of PCIe architecture, protocol, and electrical specifications (Gen4/Gen5/Gen6)
• Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BERT tools
• Experience debugging high-speed serial interfaces at both the physical and protocol layers
• Excellent written and verbal communication skills with ability to explain complex technical concepts
• Develop and modify firmware using C to implement features, optimize performance, and resolve technical issues
• Travel to customer sites worldwide to provide on-site technical support, conduct system integration, and drive issue resolution

Preferred Qualifications

• Experience with PCIe retimers, redrivers, or similar connectivity components
• Familiarity with server, storage, or GPU system architectures
• Background in signal integrity analysis and simulation tools
• Scripting proficiency (Python, TCL) for test automation and data analysis
• Prior experience working directly with hyperscale or enterprise data center customers
• Track record of creating high-quality technical documentation and application notes

Salary range is $158,400 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description

The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• Minimum 8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).
• Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience developing embedded firmware for PCIe products.
• MQX RTOS or ThreadX Development or enablement.
• High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
• High level of proficiency in Python for automating pre-processors/post-processors and FW QC.
• Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.
• Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).
• Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces
• Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc

Preferred Experience

• Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC)
• Experience with industry forums and collaboration workgroups such as OCP and OpenBMC

The base salary range is $203,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Overview

Astera Labs Inc. is seeking a proactive and self-driven Hardware Lab Technician to join our team in developing world class connectivity products for AI infrastructure.

Job Description

This role works closely with various teams within our lab, including SI/PI, validation, design, NPI, and more. You will also be responsible for organizing and managing an inventory of consumables and peripherals while providing comprehensive support for lab infrastructure and daily operations. The ideal candidate will have hands-on technical skills, a strong work ethic, and the ability to manage various responsibilities in a fast-paced, collaborative environment.

Key Responsibilities

• Operate a manual probe station (MPI TS600-PCB) to probe printed circuit boards and components
• Perform DC and signal integrity measurements on PCBs and evaluation hardware
• Manage critical inventories of Astera products, tools, consumables, and peripherals, including purchasing, organizing, monitoring, and forecasting
• Assemble, inspect, and test modules/subassemblies
• Optimize and maintain lab organization
• Monitor compliance with lab policies, including ESD, cleanliness, food/drink, etc.
• Assist engineers with various other hands-on tasks, including soldering and rework of SMDs on high-density PCBAs

Required Qualifications

• 1 year of experience in a hardware lab environment
• 1 year of manual probe station experience
• Associate’s degree or equivalent technical certification in electronics engineering, electrical engineering, computer engineering, or a similar field
• Self-starter with a bias towards action
• Strong organizational skills and attention to detail
• Effective and clear communication, both written and verbal
• Ability to lift and move up to 40lbs safely

Preferred Qualifications

• 2 years of manual probe station experience
• 2 years of inventory management experience
• Comfortable performing solder rework on 0201 components, micro-coax cables, and fly line/magnet wire
• Fluent in interpreting circuit schematics and board layouts
• Ability to troubleshoot and debug PCBAs using oscilloscopes, multimeters, power supplies, etc.
• Familiarity with Python, Bash, and/or Linux
• Ability to clearly document and communicate findings and measurement results