• Bachelor’s degree or advanced diploma in Electrical Engineering (EE)

• 8+ years of experience in high-speed analog IC layout using Cadence Virtuoso
• Prior experience with BiCMOS layout is strongly preferred
• Proven experience handling at least one chip top-level through tapeout
• Proficiency in layout extraction and parasitic analysis for high-speed circuits
• Awareness of EMIR and antenna DRC rule-compliant layout practices
• Experience with Cadence SKILL and TCL scripting is highly recommended

As an Integrated Circuit Designer, you will be part of a key team designing sophisticated advanced node CMOS products.

Key Job Duties:

• The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets].
• The management of manufacturing process of the products, including technology yield and performance of the products.
• The development of test programmes and procedures to ensure the products meet their performance specifications. This will include [working on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB].
• The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Basic Qualifications

• Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.
• 6+ years of experience supporting or developing complex analog IC designs.

Required Experience:

• Hands-on experience in designing high-speed mixed-signal circuits, including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution and other high-speed analog circuits is a must. 
• Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits.
•  Solid track-record for implementation of analog circuits high-speed data transmissions.
• Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must.
• Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
• Knowledge of TIA design and drivers for optical applications is highly desirable.
• Experience in RFIC design for wireless or wireline communication systems is highly desirable.
• Strong technical independent contributor with a proven ability to drive results.
• Excellent teamwork, presentation, and documentation skills.
• Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
• Strong experience in lab chip bring-up and debugging efforts.

Preferred Experience:

• Relevant research publications and/or patents in analog or RF IC design.
• Familiarity in programming/scripting languages such as Python, Matlab, or C.
• Experience with PCB design.
• Familiarity with Verilog RTL or DSP design concepts.
• Knowledge of optical transceivers.
• Expertise in ESD protection techniques and IC packaging methodologies.

Job Summary: 

We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. 

Key Responsibilities: 

• Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). 
• Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). 
• Support schematic, layout, simulation, and verification environments. 
• Collaborate with design teams to understand requirements and improve design productivity. 
• Integrate and validate PDKs (Process Design Kits) and technology files. 
• Provide documentation, training, and support for CAD tools and flows. 
• Interface with EDA vendors to evaluate and deploy new tools and features. 
• Monitor and resolve CAD tool issues, ensuring high availability and performance. 

Required Qualifications: 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 
• 3+ years of experience in analog/mixed-signal CAD or EDA tool development. 
• Strong knowledge of analog/mixed-signal IC design methodologies. 
• Proficiency in scripting languages such as SKILL, Python, Tcl, or Perl. 
• Experience with Cadence Virtuoso, Spectre, and AMS simulation environments. 
• Familiarity with PDK integration and technology file management. 
• Excellent problem-solving, communication, and teamwork skills. 

Preferred Qualifications: 

• Experience with digital-on-top (DoT) or mixed-signal verification flows. 
• Knowledge of version control systems (e.g., Git, Perforce). 
• Familiarity with Unix/Linux environments and shell scripting. 
• Exposure to advanced process nodes (e.g., 7nm, 5nm). 

• Bachelor’s degree or advanced diploma in Electrical Engineering (EE)

• 10+ years of experience in high-speed analog IC layout using Cadence Virtuoso
• Prior experience with BiCMOS layout is strongly preferred
• Proven experience handling at least one chip top-level through tapeout
• Proficiency in layout extraction and parasitic analysis for high-speed circuits
• Awareness of EMIR and antenna DRC rule-compliant layout practices
• Experience with Cadence SKILL and TCL scripting is highly recommended

Job Description: As a Digital Designer in the DSP SerDes team, you will join a pivotal project to develop advanced high speed SerDes wireline and optical transceivers for AI systems. 

Basic Qualifications:

• Hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5-10 years of experience in digital design for high-speed DSP data path.
• Be proficient in coding System Verilog for complex design blocks.
• Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time.
• Have experience taking design blocks through the full design cycle, from micro-architecture to tapeout.
• Have experience with timing fixes, area and power optimizations, and resolving silicon issues.

Required Experience:

• Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery.
• Code and deliver high-quality RTL to the PD and DV teams.
• Collaborate with the DSP Architecture team to define new features and suggest optimizations for power, latency, and performance.
• Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations.
• Partner with the DV team to root-cause and fix design bugs.

Preferred Experience:

• Experience in digital design for high speed data path in 100G+ PAM4 DSP SerDes
• Experience in designing PAM4 DSP blocks for FFE, DFE, MLSD, and digital timing recovery.

Job Summary: We are seeking a talented Senior Design Verification Engineer to join our team. The ideal candidate will play a key role in verifying the functionality and performance of our digital and mixed-signal designs. You will work closely with the design and development teams to create and execute comprehensive verification plans, ensuring the robustness and reliability of our products.

Key Responsibilities:

• Develop and implement test plans and testbenches for verification of sub-blocks in high-speed Ethernet, UALink, PCIE PHY (64b/66b Encoder/Decoder, FEC encoder/decoder, DSP, FFE, DFE, MLSD).
• Identify, document, and debug functional issues found during verification, collaborating with design engineers for resolution.
• Develop and apply coverage models to ensure thorough validation of the design.
• Work closely with architects, designers, and software teams to comprehend the design architecture and contribute to high-level verification strategy.
• Stay up-to-date with industry best practices and emerging tools for design verification.

Qualifications:

• Bachelor’s in Electrical Engineering, Computer Engineering, or a related field.
• 2+ year of experience in DV.
• Strong proficiency in verification languages such as System Verilog, UVM (Universal Verification Methodology).
• Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, or Mentor Graphics QuestaSim).
• Familiarity with scripting languages such as Python, Perl, or Shell scripting for automation purposes.
• In-depth understanding of digital design principles, verification methodologies, and industry-standard protocols.
• Excellent analytical, debugging, and problem-solving skills.
• Strong teamwork and communication abilities.

Pay and Benefits

• Competitive salary.
• Performance bonus each year.
• Flexible working time.
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips.

Role Overview As a Sr. Principal DSP Architect, you will be the technical visionary leading the definition and development of next-generation Digital Signal Processing (DSP) architectures. Your focus will be on high-speed PAM4 (Pulse Amplitude Modulation 4-level) systems and coherent/direct-detect optical transceivers. You will bridge the gap between theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond.

Key Responsibilities

• Architectural Leadership: Lead the definition of DSP micro-architecture for high-performance ASICs, focusing on low-power, high-throughput data paths.
• Algorithm Development: Design, model, and simulate advanced DSP algorithms for:
• Adaptive Equalization (FFE, DFE, MLSE).
• Forward Error Correction (FEC).
• Clock and Data Recovery (CDR).
• Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) compensation.
• Modeling & Simulation: Develop bit-accurate and performance-accurate models using Python, MATLAB, or C++ to validate architectural choices against Bit Error Rate (BER) targets.
• Cross-Functional Collaboration: Work closely with Analog Mixed-Signal (AMS) designers to optimize the ADC/DAC interface and with RTL teams to ensure power-efficient hardware implementation.
• Performance Trade-offs: Conduct rigorous Power, Performance, and Area (PPA) analysis to balance complex DSP requirements with the thermal and size constraints of optical modules (e.g., QSFP-DD, OSFP).
• Standards Contribution: Represent the company in industry standards bodies (IEEE 802.3, OIF) to influence future optical communications protocols.

Required Qualifications

• Education: PhD or MS in Electrical Engineering, Communication Theory, or a related field.
• Experience: 12+ years of experience in DSP design, specifically for high-speed SerDes or optical communications.

Technical Deep Dive:

• Expertise in PAM4 signaling and the associated challenges (non-linearity, SNR requirements).
• Deep understanding of Digital Filter Design (FIR, IIR) and adaptive signal processing.
• Experience with high-speed ADC/DAC architectures and their impact on DSP performance.
• Tooling: Proficiency in MATLAB/Simulink, Python (NumPy/SciPy), and SystemC.
• Silicon Success: A proven track record of taking complex DSP architectures from concept through tape-out to high-volume production.

Preferred Skills

• Experience with Coherent Optical technologies (QAM, polarization multiplexing).
• Knowledge of Machine Learning applications in DSP for non-linearity compensation.
• Familiarity with hardware description languages (Verilog/SystemVerilog) and the synthesis flow

About the Role

We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node.

In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures.

Key Responsibilities

• Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm.
• Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power.
• Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis.
• Handle advanced physical design topics:
• EM/IR analysis and power grid optimization
• Congestion analysis and mitigation
• Clock domain crossing and skew optimization
• RC extraction-aware placement and routing
• Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
• Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers.
• Perform ECO implementation and support tapeout signoff activities.
• Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools.
• Use industry-standard tools (e.g., ICC2, Innovus, Voltus, RedHawk, Calibre) for implementation and signoff.
• Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field.
• 4+ years of experience in physical design with advanced technology nodes (preferably ≤ 5nm).
• Strong experience with:
• Floor planning, placement, CTS, routing, and IR drop mitigation
• Signoff checks (DRC/LVS/ANT/ERC) and debugging
• Timing closure collaboration with STA team
• Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus.
• Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet environments.
• Experience in high frequence data path, DSP designs.
• Solid scripting skills for automation and productivity enhancement.

We are seeking an experienced Analog/Mixed-Signal (AMS) Circuit Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5/3nm technology node. In this role, you will design high-speed analog and mixed-signal circuits used in multi-gigabit transceivers, collaborating with layout, verification, and system teams to ensure robust performance, power efficiency, and successful silicon validation at advanced process nodes.

Key Responsibilities

• Design critical AMS blocks such as PLLs, CDRs, LDOs, bias generators, and ADC/DAC components for wireline transceivers. 
• Perform transistor-level design, simulation, and optimization for performance, power, and area across process, voltage, and temperature (PVT) corners.
• Work closely with layout engineers to guide floorplanning, matching-sensitive layout, and parasitic-aware design. • Perform design verification using pre- and post-layout simulations (transient, AC, noise, Monte Carlo, corner sweep).
• Ensure robust operation under variation, jitter, power supply noise, and crosstalk conditions.
• Create and maintain design documentation, design reviews, and specifications
• Collaborate with system architects, digital design, and firmware teams to define and optimize mixed-signal interface behavior.
• Support silicon bring-up, lab measurement correlation, and debug of design issues.
• Use industry-standard tools (e.g., Virtuoso, Spectre, HSPICE, ADE, MATLAB, Python) for design and analysis.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
• 5+ years of experience in analog/mixed-signal circuit design in deep-submicron or FinFET technologies.
• Strong experience with:
  • Transistor-level design and simulation in advanced nodes (≤ 5nm).
  • Designing analog blocks for high-speed transceivers (e.g., clocking, bias, analog front ends).
  • SPICE simulation tools and AMS verification environments.
  • Deep understanding of noise, jitter, linearity, bandwidth, gain, impedance matching, and power trade-offs.
• Familiarity with layout interaction and parasitic-aware circuit optimization.
• Solid debugging, problem-solving, and documentation skills.

Benefits

• Competitive salary
• 13th month salary
• Performance bonus each year
• Flexible working time
• Health check each year
• Insurance for engineer and family
• Lunch Allowance
• Company trips.

The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones

As an Integrated Circuit Designer - Layout, you will be part of a key team designing and developing sophisticated advanced node CMOS products.

Key Job Duties:

• The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS]
• The management of manufacturing process of the products, including technology yield and performance of the products. 
• The development of test programmes and procedures to ensure the products meet their performance specifications.
• The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Basic Qualifications:

• At least a bachelor’s degree in electrical engineering

Required Experience:

• 4+ years of experience in the development of layouts for highspeed analog IC designs in fin FET technology.
• Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.
• EMIR and antenna DRC rules aware layout practices.
• Experience writing SKILL and TCL scripts is highly recommended

Pay and Benefits

• Competitive salary.
• 13th month salary.
• Performance bonus each year.
• Long Term Incentive (LTI)
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips.

Job Description:

As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.
• 2+ years of experience supporting or developing complex analog IC designs.

Required Experience:

• Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
• Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
• Solid track-record for implementation of analog circuits high-speed data transmission.
• Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must
• Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
• Knowledge of TIA design and drivers for optical applications is highly desirable
• Experience in RFIC design for wireless or wireline communication systems is highly desirable.
• Strong technical independent contributor with a proven ability to drive results.
• Excellent teamwork, presentation, and documentation skills.
• Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
• Strong experience in lab chip bring-up and debugging efforts.

Preferred Experience:

• Relevant research publications and/or patents in analog or RF IC design.
• Familiarity in programming/scripting languages such as Python, Matlab, or C.
• Experience with PCB design.
• Familiarity with Verilog RTL or DSP design concepts.
• Knowledge of optical transceivers.
• Expertise in ESD protection techniques and IC packaging methodologies.

The base salary range is $150,000.00 USD – $200,000.00 USD.

The base salary range for this role in Canada is $110,000 CAD - $130,000 CAD

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Overview: 

As a Senior Principal Validation Engineer, you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets.

You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction.

This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives before production.

Key Responsibilities:

• Design, develop, and execute validation plans. Own end‑to‑end post‑silicon characterization and validation strategies, translating product requirements into measurable test objectives, pass/fail criteria, and schedules.
• Drive design reviews and specification alignment. Participate in architecture and design‑spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.
• Lead hands‑on test execution and bring‑up. Perform silicon bring‑up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time‑to‑data.
• Build and maintain automation frameworks. Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed‑signal test benches.
• Debug and optimize system performance. Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs.
• Root‑cause cross‑domain failures. Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system‑level tests; coordinate with design, package, and firmware teams to implement fixes.
• Collaborate with cross‑functional teams. Work closely with mixed‑signal design, firmware, system engineering, and manufacturing to deliver detailed results, root‑cause analyses, optimization recommendations, and formal validation/compliance reports.
• Document findings and improve methodologies. Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base.
• Develop test software and platform integrations. Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites.
• Measure and communicate impact. Define key validation metrics, track coverage and defect trends, and present data‑driven conclusions to stakeholders to influence product direction and release decisions.

Basic Qualifications

• Education — Bachelor of Science in Electrical Engineering required; Master’s degree preferred to demonstrate advanced technical depth and specialization.
• Experience — At least ten years of hands‑on experience in mixed‑signal, high‑speed lab environments, executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real‑time oscilloscopes, sampling scopes, TDRs, and VNAs.
• Software Skills — Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.
• Retimer Expertise — Practical experience bringing up and debugging retimers, including equalization tuning, pass‑through operation, clocking strategies, and reset and link sequencing.
• High‑Speed Signaling Knowledge — Deep understanding of NRZ and PAM4 architectures and the ability to investigate jitter sources, CDR and PLL behavior, equalization techniques such as DFE, CTLE, and FFE, as well as crosstalk and power integrity issues.
• Post‑Silicon Validation — Proven track record in post‑silicon validation and bring‑up of high‑speed PHYs or retimers, with experience developing characterization flows and validating silicon against specifications.
• Circuit Block Familiarity — Solid working knowledge of key high‑speed building blocks including PLLs, CTLE, DFE, transmitter equalization, and PAM4 signaling fundamentals.
• Analytical Problem Solving — Exceptional troubleshooting skills with the ability to isolate and narrow complex, multi‑layer failures across analog, digital, firmware, and package domains.
• Communication — Excellent written and verbal communication skills for clear documentation of findings, presentation of root cause analyses, and collaboration with cross‑functional teams.

Preferred Experience:

• Mixed‑signal system testing and validation — Demonstrated experience in end‑to‑end mixed‑signal system testing, characterization, validation, and compliance activities, including developing test plans, executing characterization flows, and producing formal compliance reports.
• Signal integrity instrumentation and techniques — Hands‑on proficiency with signal integrity test equipment and methodologies, including BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, and advanced probing techniques for channel and package analysis.
• Ethernet standards familiarity — Working knowledge of IEEE 802.3 family standards and practical experience validating Ethernet PHYs, link training, autonegotiation, and compliance testing across relevant speeds and media types.
• Serial protocol expertise — Practical understanding of common serial interfaces such as I2C, I3C, SPI, UART, and other control/status buses used for device bring‑up, firmware interaction, and system integration.
• Cross‑discipline collaboration — Proven ability to translate SI/PI simulation results into testable lab plans, collaborate with design and firmware teams to close the loop on issues, and document findings that drive design or process improvements.

Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.

The base salary range is USD 205,00 - USD 255,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job Description

We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
  required, and a Maser’s is preferred.
• ≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in US and start immediately.

Required Experience

• Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
  environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
  generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
  writing assertions, cover properties and analyzing coverage data
• Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.
• Must have prior experience on verification with firmware to control and configure the SerDes and related components.

Preferred Experience

• SW debugging for Mix-Signal based designs.
• Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.
• Experience with FPGA-based verification/emulation.

Job Description:

As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.
• 8+ years of experience supporting or developing complex analog IC designs.

Required Experience:

• Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
• Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
• Solid track-record for implementation of analog circuits high-speed data transmission.
• Design and tape out experience in advanced CMOS nodes (ex. 7nm, 5nm 3nmFinFET) is a must.
• Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
• Knowledge of TIA design and drivers for optical applications is highly desirable
• Experience in RFIC design for wireless or wireline communication systems is highly desirable.
• Strong technical independent contributor with a proven ability to drive results.
• Excellent teamwork, presentation, and documentation skills.
• Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
• Strong experience in lab chip bring-up and debugging efforts.

Preferred Experience:

• Relevant research publications and/or patents in analog or RF IC design.
• Familiarity in programming/scripting languages such as Python, Matlab, or C.
• Experience with PCB design.
• Familiarity with Verilog RTL or DSP design concepts.
• Knowledge of optical transceivers.
• Expertise in ESD protection techniques and IC packaging methodologies.

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.