Job Title: Director of Design Verification

Overview

We are seeking a seasoned Director of Design Verification with 15+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domains.

Key Responsibilities

• Own and drive the end-to-end verification methodology for a specific product line.
• Lead, mentor, and grow a team of engineers, fostering technical excellence and innovation.
• Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.
• Champion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficiency.
• Collaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.
• Represent verification in executive reviews, customer engagements, and industry forums.
• Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
• 15+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
• Deep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification IPs.
• Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
• Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.

Required Experience

• Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).
• Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
• Strong background in writing assertions, cover properties, and analyzing coverage data.
• Experience in developing VIP abstraction layers to simplify and scale verification deployments.

Preferred Experience

• Expertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC.
• Experience with buffering, queuing, and QoS in complex NoC-based SoCs.
• System-level performance analysis on switching fabrics.
• Familiarity with AI-driven verification methodologies and workforce transformation strategies.

• Bachelor’s degree or advanced diploma in Electrical Engineering (EE)

• 8+ years of experience in high-speed analog IC layout using Cadence Virtuoso
• Prior experience with BiCMOS layout is strongly preferred
• Proven experience handling at least one chip top-level through tapeout
• Proficiency in layout extraction and parasitic analysis for high-speed circuits
• Awareness of EMIR and antenna DRC rule-compliant layout practices
• Experience with Cadence SKILL and TCL scripting is highly recommended

Title: Lead Firmware QA Engineer, Astera Labs, Bengaluru, India. 
 
Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning.

Basic Qualifications:

• Bachelor’s degree in electrical engineering (EE) or Computer Science is required; a master’s or PhD in EE is preferred with minimum 4 years of experience.

Required Experience:

• Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol.
• Estimate work, identify dependencies and develop schedules.
• Responsible for designing and executing functional, performance, interoperability and stress tests.
• Work closely with  Silicon team, architecture team, FW development team to understand the design and develop test strategies.
• Responsible for manual and automation testing.
• Strong knowledge of scripting ( Python ) is must.
• Responsible for automation development and manual testing.
• Perform Signal integrity and protocol level validation.
• Closely work with development teams to triage and debug issues.
• Knowledge of collecting PCIe trace using PCIe analyzer and analyzing the trace to triage issues.
• Experience in PRBS testing, loopback and margining tests.
• Good understanding of OOB testing and Protocols like MCTP, I2C, SPDM etc.
• Experience is PCIe compliance testing is a plus.
• Regularly working with Hyperscale's and Tier 1 OEMs to communicate plans and status, address escalations, deliver on SLAs.
• Knowledge in validation of NIC controllers and storage controllers is preferred.
• Requirements management and traceability through software development phases.
• Mentoring and coaching team members to help them excel in their jobs.
• Power user of Git, Jira and Confluence.

As an Astera Labs’ Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs’ connectivity products that support the world’s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams.

Basic qualifications:

• Minimum of bachelor’s degree in computer engineering/ electrical engineering, Masters preferred.
• Minimum 10+ years of experience in a semiconductor company as a DFT engineer
• Must be local or willing to relocate

Required experience:

• Chip design, Verilog and System Verilog
• Verification, UVM methodology
• ATPG tools
• Scan insertion tools
• Gate-level simulations
• Static timing analysis
• Scripting (Perl/Tcl)
• Familiarity with ATE
• Hands-on expertise with commercial test generation tools for large complex designs
• Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression
• Experience running test compression software
• Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools

Preferred experience:

• Experience with defining and implementing SOC level verification on large designs.
• Working with 93k Tester

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

• Bachelor’s degree or advanced diploma in Electrical Engineering (EE)

• 10+ years of experience in high-speed analog IC layout using Cadence Virtuoso
• Prior experience with BiCMOS layout is strongly preferred
• Proven experience handling at least one chip top-level through tapeout
• Proficiency in layout extraction and parasitic analysis for high-speed circuits
• Awareness of EMIR and antenna DRC rule-compliant layout practices
• Experience with Cadence SKILL and TCL scripting is highly recommended