Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Summary

We are seeking a student intern to drive product quality improvements across both Astera Lab’s semiconductor and board-level products. In this role, the candidate will perform failure analysis for customer returns. The candidate will also compile 8D reports to communicate the analysis findings to the customers.

Key Responsibilities

· Perform system-level test for the customer returns on a bench in the lab.

· Review ATE test log files.

· Work with third-party labs to perform electrical FA (EFA) for more in-depth analysis.

· Log analysis results to the portal system daily.

· Work with internal teams and suppliers to drive product quality improvements.

· Write up analysis reports to provide updates to the customers. Participate in the meetings with customers to present the technical findings.

· Bring up and validate new test equipment in the lab. Update the lab inventory list.

· Perform additional tasks assigned by the Director of Field Quality Engineering.

Education & Experience

· Final year students from Bachelor’s degree are welcome to apply.

· Students from Master’s degree are preferred.

Technical Skills

· Good knowledge of IC fabrication, packaging, board assembly (SMT), and test processes

· Strong communication skills in English and Mandarin.

Working Conditions:

· May require occasional travel to customer sites within Taiwan.

· Must be flexible to work on-site and available during business hours for at least 3 days per week.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

Job Description:
Astera Labs is seeking a proactive and detail-oriented NPI Planner to join our supply chain team. In this critical role, you will coordinate the introduction of new products by collaborating with multiple stakeholders, including business units, engineering teams, and both internal and external customers. This position demands exceptional communication skills, strong project management abilities, and the capacity to excel in a fast-paced environment.

Responsibilities:

• Support New Product Introduction (NPI) for ASICs.
• Develop and maintain detailed product schedules, ensuring alignment with production goals, timelines, and customer delivery requirements.
• Collaborate with cross-functional teams to manage the end-to-end product lifecycle, from concept through launch.
• Monitor production readiness and proactively resolve potential roadblocks to ensure on-time product releases.
• Track hardware requirements and material orders, maintaining alignment with overall product schedules and milestones.
• Execute supply chain functions including material planning, capacity planning, vendor coordination, inventory management, and customer shipment logistics.
• Analyze vendor quotations, lead cost negotiations, and manage purchase order creation and execution.
• Prepare and present reports on project status, risk assessments, and opportunities for process improvement.

Requirements:

• Bachelor’s degree in Engineering, Science, Business, or a related field.
• Strong organizational skills with meticulous attention to detail and the ability to manage multiple tasks effectively.
• Experience in manufacturing operations.
• Excellent analytical, mathematical, and problem-solving capabilities.
• Background in data analysis or analyst roles.
• Proficiency in Microsoft Office Suite (Excel, PowerPoint, Word) or equivalent tools.

 Base salary range is $140,000 to $155,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Position Summary 

As a key member of the Sales team, you will be entrusted with strategic ownership of hyperscale customer accounts. This role is ideal for a results-driven professional who excels in dynamic environments and is motivated to expand their impact within a high-performing organization. You will drive revenue growth, build deep customer relationships, and act as a catalyst for scaling team success—taking initiative, anticipating needs, and executing with precision. In addition to delivering on current revenue goals, you will be responsible for proactively creating and building a robust pipeline of opportunities, ensuring we are well-positioned to capture future revenue targets and sustain long-term growth. Success in this role means not only achieving ambitious targets but also proactively expanding responsibilities and influence across the organization. 

Responsibilities 

• Take ownership of hyperscale customer accounts, driving strategic engagement and growth.
• Proactively identify opportunities to scale processes, expand responsibilities, and support the sales team’s vision for organizational growth.
• Operate with agility and a sense of urgency, consistently delivering results in fast-paced situations.
• Serve as a trusted partner to both customers and internal stakeholders, representing the highest standards of professionalism.
• Demonstrate exceptional accountability, initiative, and follow-through on complex projects.
• Collaborate cross-functionally to ensure seamless execution and alignment with company goals.
• Mentor and inspire peers, fostering a culture of achievement and continuous improvement. 

Traits & Competencies 

• Relentless drive for results and continuous improvement.
• Strategic thinker with the ability to anticipate challenges and opportunities.
• High emotional intelligence and adaptability.
• Strong sense of ownership and accountability.
• Ability to thrive in ambiguity and rapidly changing environments.
• Exceptional communication and influence skills.
• Entrepreneurial mindset with a bias for action. 

Qualifications 

• Bachelor’s degree (Engineering preferred); Master’s degree is a plus
• 8-15 years’ experience in semiconductor or datacenter/connectivity sales or field roles
• Proven track record of winning complex SoC/silicon design wins
• Strong network within cloud service providers and OEMs
• Exceptional leadership, communication, and project management skills
• Entrepreneurial mindset with a customer-first attitude 

Preferred Qualifications 

• Experience selling [specific products or services, e.g., SaaS, hardware, software].
• Knowledge of the Silicon Valley tech ecosystem and key players.
• Experience using CRM software (e.g., Salesforce). 

About the Role

As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.

Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams.

This position is required onsite in San Jose, CA.

Key Responsibilities

• Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms
• Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems
• Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning 
• Serve as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrations
• Interpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutions
• Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on schedule
• Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows
• Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral
• Represent the Leo team in customer technical reviews, design-in engagements, and industry forums

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
• 8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications
• Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
• Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!
• Authorized to work in the US and available to start immediately

Required Experience

• High proficiency in C for embedded firmware development in RTOS environments
• Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
• Proficiency in Python for scripting, test automation, and diagnostic tooling
• Deep hands-on knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
• Experience with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
• Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
• Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
• Experience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines

Preferred Experience

• Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
• Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
• Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
• Experience with server memory performance tuning — latency and bandwidth optimization
• Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus

Compensation

The base salary range for this role is $175,000 – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Role Overview

Astera Labs is seeking a Principal Product Applications Engineer to join our Taurus Ethernet Smart Cable Modules team and drive customer success at the forefront of AI infrastructure connectivity. As data centers scale to meet explosive AI workload demands, our Taurus products are enabling the high-bandwidth, low-latency Ethernet fabric connections that power next-generation GPU clusters and disaggregated computing architectures.

In this role, you'll be the technical expert customers rely on to successfully deploy Taurus Ethernet solutions in their most demanding environments. You'll work hands-on with hyperscalers, OEMs, and AI system builders to debug complex physical layer challenges, deliver technical enablement, and ensure seamless product integration. Your customer insights will directly influence how we evolve our products to meet the market's most pressing connectivity needs.

This is a unique opportunity to combine deep Ethernet and physical layer expertise with meaningful customer impact at a hyper-growth company defining the future of AI connectivity. You'll collaborate across engineering, sales, and product teams while building relationships with the world's most innovative technology companies.

Key Responsibilities

· Customer Technical Engagement

o Serve as the primary technical resource for customers evaluating and deploying Taurus Ethernet Smart Cable Modules

o Deliver technical presentations, product training, and hands-on demonstrations to customer engineering teams

o Build trusted relationships with key accounts and drive successful product adoption

· System-Level Debug & Validation Support

o Lead root cause analysis and debugging of complex Ethernet physical layer and link issues in customer systems

o Support customer lab bring-up, characterization, and system validation activities

o Develop and execute test plans to reproduce and resolve customer-reported issues

o Experience with firmware handling preferred

· Technical Documentation & Enablement

o Create application notes, integration guides, and best practices documentation for Ethernet system implementation

o Develop technical collateral that accelerates customer time-to-deployment

o Contribute to product documentation including datasheets and user guides

· Cross-Functional Collaboration

o Partner with product management and engineering to translate customer feedback into product requirements

o Support sales teams with technical expertise during pre-sales and post-sales engagements

o Represent voice of the customer in internal roadmap discussions and feature prioritization

Basic Qualifications

· Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

· 8+ years of experience in applications engineering, technical support, or system engineering roles

· Strong understanding of Ethernet physical layer specifications (100G/200G/400G/800G)

· Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BER test tools

· Experience debugging high-speed serial interfaces and signal integrity challenges

· Excellent written and verbal communication skills with ability to convey complex technical concepts

· Ability to travel within mainland China and Asia for customer debug

Preferred Qualifications

· Experience with optical modules, active cables, or similar high-speed connectivity components

· Familiarity with AI/ML system architectures, GPU clusters, or data center networking

· Background in signal integrity analysis and simulation

· Scripting proficiency (Python, TCL) for test automation and data analysis

· Prior experience working with hyperscale or enterprise data center customers

· Knowledge of Ethernet consortium specifications and industry standards

Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure?  

We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing and other cross-functional teams to define and deliver competitive silicon, hardware and software solutions. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of technical expertise and market insight within your product domain.  

This is a unique opportunity to play a pivotal role in the success of our Leo Smart Memory Controller. We are scaling our product team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team.   

Based in San Jose, CA or Vancouver, BC, this position requires an in-person presence with travel to customers.  

Key Responsibilities  

• Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback.  
• Lead customer technical engagement: Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design-wins throughout the product lifecycle.  
• Support go-to-market: Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning.  
• Lead product planning: Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch.  

Qualifications  

• Bachelor’s degree in engineering or compute science  
• 5-10 years of experience in product management, technical product marketing, applications or other customer-facing product roles within the semiconductor industry 
• Proven track record of defining and launching successful semiconductor products (switch products are a plus) 
• Deep understanding of high-speed protocols (PCIe/CXL and/or UALink are required; Ethernet and other protocols are a plus) and system architectures used in cloud and AI infrastructure  
• Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products  
• Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner  
• Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment  
• Results-oriented mindset with a focus on driving measurable impact and achieving business objectives  
• Experience working with customers and partners to understand their needs and drive product definition  
• Willingness to travel as needed for customer meetings, industry events, and trade shows  

If you are passionate about driving innovation and shaping the future of data center connectivity through world-class products, we encourage you to apply. Join Astera Labs in unleashing the potential of cloud and AI infrastructure!  

Compensation will be based on leveling and experience. Base Salary Range $210,000 - $255,000

Role Overview

As a Principal Product Applications Engineer at Astera Labs, you will be at the forefront of enabling the world's leading cloud service providers and server/network OEMs to successfully deploy connectivity solutions. This high-impact role sits at the intersection of cutting-edge silicon, firmware, and customer success—where you'll tackle complex technical challenges that push the boundaries of AI infrastructure connectivity.

You will serve as a trusted technical advisor to strategic customers, guiding them through design-in, bring-up, and optimization of Astera Labs products. With a strong firmware orientation, you'll dive deep into embedded systems, debug intricate firmware-hardware interactions, and drive issues to resolution across the full stack. Your insights from the field will directly influence product roadmaps and engineering priorities, making you a critical bridge between customers and our R&D teams.

This is an opportunity to work on industry-defining connectivity products that power next-generation data centers and AI platforms—all within a fast-paced, hypergrowth environment where your contributions have immediate and visible impact.

Key Responsibilities

• Customer Technical Engagement
  • Provide expert technical guidance to tier-1 customers throughout the design-in lifecycle, from early evaluation through production deployment
  • Build trusted relationships with customer engineering teams, serving as the go-to resource for product integration
  • Deliver technical presentations, training sessions, and design reviews to accelerate customer success
• Firmware Debug & Issue Resolution
  • Investigate and reproduce customer-reported issues involving firmware, silicon, hardware design, and system-level interactions
  • Drive root cause analysis and coordinate cross-functional teams to deliver timely resolutions
  • Develop firmware-based tools, scripts, and utilities to streamline debug and validation workflows
• Technical Collateral & Knowledge Sharing
  • Create high-quality application notes, integration guides, and technical documentation for internal and external audiences
  • Provide actionable feedback to product, firmware, and silicon teams to continuously improve products and customer experience
  • Contribute to the development of reference designs and best practices for product deployment
• Lab Validation & Bring-Up
  • Execute hands-on silicon and system bring-up activities, including firmware validation and performance characterization
  • Utilize lab equipment such as protocol analyzers, high-speed oscilloscopes, and traffic generators to diagnose complex issues
  • Support interoperability testing across diverse customer platforms and configurations

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in product applications, field applications, or systems engineering roles supporting complex semiconductor products
• Strong firmware development and debugging skills, including proficiency in embedded C and Python
• Experience with high-speed interfaces such as PCIe Gen5/6/7 or Ethernet
• Demonstrated ability to triage and resolve multi-layer issues spanning silicon, firmware, and system environments
• Excellent written and verbal communication skills with a track record of producing clear technical documentation

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related field
• Experience with Ethernet products, retimers, or PCIe connectivity solutions
• Hands-on experience with protocol analyzers, high-speed oscilloscopes, and BERTs
• Background working directly with cloud service providers, server OEMs, or networking equipment manufacturers
• Understanding of data center architectures including servers, AI platforms, JBOGs/JBODs, and network switches
• Familiarity with physical layer concepts and signal integrity fundamentals

The base salary range for this role is CAD 180,000 – CAD 205,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for a performance bonus, equity, and benefits.

Astera Labs is seeking a strategic and knowledgeable Benefits Manager to join our Human Resources team in San Jose, California. As we continue our hyper-growth trajectory as a leader in AI infrastructure connectivity, this role will be instrumental in designing, managing, and optimizing our global benefits programs that attract and retain world-class talent. 

This is a high-impact position that goes beyond day-to-day benefits administration. You'll serve as a strategic partner to HR leadership, analyzing market trends, ensuring compliance across multiple geographies, and driving initiatives that enhance the employee experience. The ideal candidate brings a global mindset, thrives in a fast-paced environment, and is passionate about building benefits programs that support our rapidly scaling workforce across the US, Canada, Asia, and EMEA. 

Key Responsibilities

Benefits Strategy & Program Management

• Develop and execute a comprehensive global benefits strategy aligned with Astera Labs' growth objectives and talent acquisition goals
• Evaluate and benchmark benefits offerings against industry standards and competitors to ensure market competitiveness
• Lead annual benefits renewal processes, including vendor negotiations and plan design recommendations
• Drive innovation in benefits offerings to support employee wellbeing and position Astera Labs as an employer of choice

Global Benefits Coordination

• Oversee end-to-end coordination of benefits programs across all operating regions, including the Canada, Asia, and EMEA, ensuring consistency, equity, and local compliance
• Serve as the primary point of contact for international benefits brokers, third-party administrators, and in-country HR partners
• Harmonize benefit plan designs across geographies while accommodating regional statutory requirements and cultural expectations
• Maintain a centralized benefits governance framework to ensure transparency, auditability, and scalability across all regions

Retirement Plans (401k) Administration

• Manage the full lifecycle of the company's 401(k) plan, including plan design, vendor management, compliance testing, and annual reporting (Form 5500)
• Partner with the 401(k) plan administrator and investment advisors to ensure the plan remains competitive, compliant, and aligned with employee financial wellness goals
• Oversee employer match programs, vesting schedules, and plan amendments in coordination with Finance and Legal
• Ensure compliance with ERISA, IRS regulations, and Department of Labor requirements; manage plan audits and non-discrimination testing
• Develop and deliver financial literacy and retirement readiness education to help employees maximize their retirement benefits
• Evaluate and expand retirement offerings for international employees, including country-specific pension and provident fund programs

Paid Time Off (PTO) Program Management

• Design, administer, and continuously improve the company's PTO programs, including vacation, sick leave, holidays, parental leave, and other leave of absence policies
• Ensure PTO policies comply with federal, state, and local regulations across all jurisdictions where Astera Labs operates (including California-specific requirements)
• Partner with Payroll and HRIS teams to ensure accurate PTO accrual, tracking, and reporting
• Benchmark PTO offerings against industry peers to maintain competitiveness and support talent attraction and retention
• Develop clear, accessible PTO communications and manager guides to promote consistent policy application across the organization
• Monitor PTO utilization trends and provide data-driven recommendations to HR leadership to support employee wellbeing and workforce planning

Global Benefits Administration & Compliance

• Manage day-to-day administration of health, welfare, retirement, and wellness programs across multiple countries
• Ensure compliance with federal, state, and international regulations (ERISA, ACA, COBRA, HIPAA, and country-specific requirements)
• Partner with external brokers, vendors, and legal counsel to navigate complex regulatory landscapes
• Develop and maintain benefits policies and procedures to support global scalability

Analytics & Communication

• Analyze benefits utilization data, cost trends, and employee feedback to inform strategic decisions and optimize program ROI
• Develop and deliver clear, engaging benefits communications and educational resources for employees
• Lead open enrollment planning and execution, ensuring a seamless employee experience
• Present benefits insights and recommendations to senior leadership

Cross-Functional Partnership

• Collaborate with Finance, Legal, and Payroll teams to ensure accurate benefits accounting and reporting
• Partner with Talent Acquisition to position benefits as a competitive advantage in recruiting top talent
• Support M&A activities and international expansion by assessing and integrating benefits programs

Basic Qualifications

• Bachelor's degree in Human Resources, Business Administration, or related field
• 10+ years of progressive experience in benefits administration and strategy
• Strong knowledge of US benefits regulations and compliance requirements (ERISA, ACA, COBRA, HIPAA)
• Demonstrated experience managing 401(k) plans, including compliance testing, vendor oversight, and employee education
• Hands-on experience administering PTO programs across multiple states, with working knowledge of California leave laws
• Experience managing relationships with benefits brokers, carriers, and vendors
• Proficiency with HRIS and benefits administration platforms
• Excellent analytical skills with the ability to translate data into actionable insights

Preferred Qualifications

• Experience coordinating global benefits across multiple countries, including international retirement and leave programs
• Experience in high-growth technology or semiconductor companies
• Strong project management skills with ability to manage multiple priorities simultaneously
• Exceptional communication and presentation skills with ability to influence stakeholders at all levels

Compensation

Salary range is $140,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

Job Title: Director of Design Verification

Overview

We are seeking a seasoned Director of Design Verification with 15+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domains.

Key Responsibilities

• Own and drive the end-to-end verification methodology for a specific product line.
• Lead, mentor, and grow a team of engineers, fostering technical excellence and innovation.
• Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.
• Champion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficiency.
• Collaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.
• Represent verification in executive reviews, customer engagements, and industry forums.
• Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
• 15+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
• Deep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification IPs.
• Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
• Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.

Required Experience

• Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).
• Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
• Strong background in writing assertions, cover properties, and analyzing coverage data.
• Experience in developing VIP abstraction layers to simplify and scale verification deployments.

Preferred Experience

• Expertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC.
• Experience with buffering, queuing, and QoS in complex NoC-based SoCs.
• System-level performance analysis on switching fabrics.
• Familiarity with AI-driven verification methodologies and workforce transformation strategies.

Director, Firmware Engineering (PCIe)

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

The mission of this role is to lead and scale the firmware engineering organization responsible for architecting and delivering firmware and microcontroller subsystems for Astera Labs’ SoC and systems products.

As a Director of Firmware Engineering, you will own the technical vision, execution strategy, and organizational development of the firmware team. You will be responsible for delivering highly differentiated firmware capabilities that are foundational to Astera Labs’ products across networking and compute infrastructure platforms.

This is a hands-on leadership role requiring both deep technical expertise and strong people leadership. Firmware is considered equally important to hardware at Astera Labs, and this role will have significant customer visibility and cross-functional influence across silicon, systems, networking, and compute architecture teams.

Key Responsibilities

• Lead, mentor, and scale a high-performing firmware engineering team, including hiring and organizational development
• Define and drive the firmware architecture and roadmap aligned with product and company strategy across networking and compute platforms
• Partner with hardware, ASIC, and system architecture teams (including network and compute architects) to define and deliver robust HW-SW interfaces
• Oversee execution of firmware development across multiple programs, ensuring quality, scalability, and on-time delivery
• Drive customer engagement, including supporting bring-up, debugging, and feature enablement in networking and compute deployments
• Establish best practices for firmware development, validation, release processes, and CI/CD infrastructure
• Influence product direction through deep technical insight into PCIe, system architecture, and network/compute workloads
• Foster a culture of ownership, innovation, and execution excellence

Basic Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Science, or related field; Master’s preferred
• 12+ years of experience in firmware/software development for complex SoC/silicon products in networking and/or compute systems (server, storage, hyperscale infrastructure)
• 5+ years of experience leading and managing high-performing engineering teams
• Proven track record of delivering complex firmware systems from architecture through production
• Strong understanding of modern data center architectures spanning networking and compute domains
• Strong ability to operate at both strategic and execution levels in a fast-paced environment
• Excellent communication skills and ability to engage effectively with customers and cross-functional teams

Required Experience

• Deep expertise in PCIe (Gen5 and beyond), including debugging with analyzers and exercisers
• Strong proficiency in C/C++ and experience building firmware SDKs
• Experience with Python for automation, validation, and firmware quality
• Experience working closely with ASIC/SoC teams to define and validate HW-SW interfaces
• Familiarity with firmware development environments (gcc/Make, GitHub, CI/CD pipelines, documentation tools)
• Experience with system-level interfaces including PCIe controllers, DDR, NVMe, and AMBA/AHB
• Hands-on experience with networking and/or compute system platforms, including server or hyperscale deployments

Preferred Experience

• Experience with PAM4 SerDes and understanding of link-level behaviors (equalization, CDR, link budgets)
• Hands-on experience with PCIe-based systems in server, storage, networking, and compute environments
• Experience with AIC firmware (NICs, switches) or PCIe/Ethernet switching stacks
• Experience working with data center networking stacks or compute acceleration platforms (e.g., GPU/AI systems)
• Background in embedded firmware for high-performance connectivity products

Role Overview 

Astera Labs is seeking a dynamic HR Director to lead our EMEA human resources team, overseeing operations across our Israel Design Centers in Haifa and Tel Aviv, as well as our R&D center in Aachen, Germany. This is a critical leadership role that will shape the people strategy for our rapidly expanding EMEA presence as we continue to scale our world-class engineering teams building the connectivity solutions powering the AI revolution. 

As HR Director, you will operate as a true business leader who happens to specialize in people strategy—not a support function, but a driver of business outcomes. You will partner with EMEA site leadership to accelerate product development timelines, improve engineering productivity, and build the organizational capabilities required to win in the AI infrastructure market. Equally critical, you will serve as the connective tissue between EMEA and our global corporate teams, ensuring seamless alignment on programs, policies, and priorities while representing EMEA needs in global discussions. This role demands a commercially-minded leader who connects every HR initiative to measurable business impact, whether that's reducing time-to-hire for critical roles, improving retention of top performers, or building leadership bench strength to support our expansion. You will build and scale a high-performing HR team while partnering closely with our global HR function to deliver results. 

Key Responsibilities 

Business Partnership & Strategic Impact 

• Drive EMEA people strategy that directly accelerates business outcomes including product delivery, engineering velocity, and market expansion 

• Operate as a member of the EMEA leadership team, contributing to business decisions beyond traditional HR scope 

• Translate business challenges into people solutions—identify where talent, organizational design, or capability gaps are limiting growth and take action 

• Establish and track HR metrics tied to business performance, holding the function accountable for measurable results 

Global Alignment & Collaboration 

• Partner closely with global corporate teams including HR, Finance, Legal, and IT to ensure EMEA alignment on company-wide initiatives and programs 

• Serve as the primary HR liaison between EMEA sites and headquarters, advocating for regional needs while maintaining global consistency 

• Collaborate on the design and rollout of global HR programs, adapting implementation for local markets while preserving intent 

• Build strong cross-functional relationships across geographies to enable effective decision-making and execution 

Talent Strategy & Competitive Advantage 

• Build a world-class semiconductor talent pipeline that gives Astera Labs a competitive edge in EMEA markets 

• Partner with engineering leadership to forecast talent needs and proactively address skill gaps before they impact delivery 

• Design compensation and retention strategies that protect critical talent and reduce regrettable attrition 

• Drive workforce planning that aligns headcount investments with product roadmap priorities 

Team Building & Scaling 

• Build, develop, and lead a high-performing HR team across Israel and Germany oriented around delivering business results 

• Effectively manage and develop remote teams across international borders, fostering collaboration and accountability across multiple sites 

• Drive scalable HR processes and infrastructure to support rapid growth without sacrificing speed or quality 

• Create clear accountability and performance expectations within the HR function 

HR Operations & Compliance 

• Ensure execution excellence in HR operations including employee relations, compensation, benefits, and performance management across EMEA 

• Maintain compliance with local labor laws and regulations in Israel and Germany 

• Continuously improve operational efficiency to free up capacity for strategic priorities 

Culture & Performance 

• Champion a high-performance culture that attracts ambitious talent and drives accountability 

• Implement initiatives that improve employee engagement and productivity, not engagement for its own sake 

• Foster an environment where top performers thrive and underperformance is addressed swiftly 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, or related field 

• 10+ years of progressive HR experience with significant time in HR leadership roles 

• 3+ years of experience managing and developing HR teams 

• Demonstrated ability to manage remote teams across international borders and multiple time zones 

• Experience in the semiconductor or high-tech hardware industry 

• Strong knowledge of Israel labor law and HR practices; familiarity with German employment regulations 

• Proven track record of scaling HR functions in high-growth environments 

• Demonstrated business acumen with a history of tying HR initiatives to measurable business outcomes 

Preferred Qualifications 

• Master's degree in Human Resources, MBA, or related advanced degree 

• Experience supporting engineering-heavy organizations in fast-paced, product-driven companies 

• Multi-country HR management experience across EMEA 

• Experience partnering with US-headquartered companies and navigating global/regional dynamics 

• Hebrew language fluency; German language skills a plus 

• Experience with M&A integration or establishing new site operations 

• HR certification (SHRM-SCP, CIPD, or equivalent) 

About the Role

We are seeking a highly operational and systems-savvy Director of Accounting Operations to lead and scale our global accounting processes in a fast-growing semiconductor technology company. This leader will own the record-to-report (R2R) function (excluding technical accounting and SEC reporting), along with accounts payable, revenue accounting, and other related accounting operations responsibilities.

This role is ideal for a hands-on, process-driven accounting leader with deep experience in developing teams in large global enterprise environments, process scaling, Oracle ERP, and centers of excellence models. The successful candidate will play a critical role in building a scalable, efficient, and well-controlled accounting organization capable of supporting a dynamic, global business.

Key Responsibilities

• Lead the accounting operations organization, including General Ledger, Intercompany & Consolidation, Accounts Payable, Revenue Accounting, International coordination, and other related areas.
• Develop subject matter expertise and global process ownership disciplines
• Oversee the overall global consolidation process, and ensure preparation of consolidated financial statements are timely, accurate, and in accordance with US GAAP.
• Build and scale the global accounting organization through strategic initiatives aligned with the objectives of the Company and leveraging technology partnering closely with the Finance Transformation and Business Systems teams.
• Partner with external auditors to ensure successful completion of quarter reviews and annual audits.
• Establish and maintain strong internal controls over financial reporting, governance practices, and continuous refinement of policies and procedures.
• Drive a disciplined, predictable, and timely monthly, quarterly, and annual close process.
• Own the design, structure, scalability, and ongoing governance of the chart of accounts (COA).
• Maintain consistency, data integrity, and reporting alignment across legal entities and geographies.
• Drive automation, standardization, and process redesign initiatives across the organization.
• Collaborate with cross-functional business partners to optimize processes and anticipate accounting outcomes and resources to accommodate.
• Build scalable processes that support rapid growth, acquisitions, and evolving business needs.

Leadership & Communication

• Demonstrated leadership capabilities with experience managing direct reports and influencing cross-functional teams.  
• Excellent communication and stakeholder management skills, capable of engaging across all organizational levels.  
• Strong program management skills, including in-depth involvement with stakeholders to execute effectively and produce thoughtful and comprehensive plans
• Highly operational and detail-oriented with a passion for process excellence.
• A systems-forward leader who leverages technology and thinks “automation first”.
• Comfortable working in a fast-paced, evolving environment.
• A strong cross-functional collaborator and business partner.
• A leader capable of balancing control rigor with business agility.

Team Development

• Build, mentor, and develop high-performing accounting teams.
• Foster a culture of operational excellence, accountability, and continuous improvement.

Cross-Functional Collaboration & Stakeholder Management

• Serve as a trusted partner to senior finance and business leaders, communicating progress, risks, and decisions effectively; deliver proactive operational solutions aligned with business objectives.

Qualifications

• 10+ years of progressive accounting experience, including leadership roles in large enterprise or multinational corporations.
• Strong background in accounting operations and controllership functions.
• Deep expertise in Oracle ERP (GL, AP, AR/Revenue, Fixed Assets, etc.).
• Proven track record in system implementations, finance transformations, or ERP optimization initiatives.
• Experience managing global accounting teams and international operations.
• Demonstrated success establishing or managing offshore shared services (outsourced or captive models).
• Strong operational mindset with the ability to drive process discipline and scalability.

Astera Labs is seeking an exceptional Director of System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments. 

Job Description 

• Seeking a strong technical leader who has delivered multiple SoC products. 
• Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs. 
• Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications. 
• Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification. 
• Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence. 
• Ensure timely bringup of new silicon and platforms, driving rootcause analysis and crossfunctional debug of hardware, firmware, and system issues. 
• Deliver high confidence validation results that support product qualification, customer sampling, and mass production readiness. 
• Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions. 
• The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fastmoving, highperformance computing environments. 
• Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies. 
• Drive a culture of technical excellence, accountability, and continuous improvement. 
• Manage resource planning, and vendor/partner relationships. 

Basic Qualifications 

• Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred. 
• ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and highperformance hardware companies. 
• ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems. 
• ≥2 years building high performance Engineering teams and validation methodologies. 
• Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions. 
• Expertise in validation methodologies: presilicon simulation/emulation, postsilicon bringup, system validation, stress testing, and performance characterization. 
• Strong background in debug methodologies, lab infrastructure, and automation frameworks. 
• Excellent communication skills and ability to influence executives and crossfunctional partners. 
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! 

Preferred Experience: 

• ≥5 years leading validation teams planning, execution and maintaining project visibility. 
• ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems. 
• Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet. 
• Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence. 

The base salary range is $200,000 CAD - $250,000 CAD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Astera Labs’ firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems.

Job Description

• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance.
• Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic Qualifications 

• Strong academic and technical background in electrical or computer engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Required Experience 

• ≥3 Years experience leading a team in a “lead by example” manner—planning sprints, assigning tasks based on individuals’ strengths and career aspirations, providing constructive/encouraging feedback, maintaining a “dashboard” view of project status, chipping into shore up gaps in execution as needed.
• ≥5 Years hands-on experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Good understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred Experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Familiarity with PCIe compliance standards and the ability to follow and be involved in compliance and standard consortiums.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, clock recovery and SerDes link budgets.
• Experience with PAM4 SerDes is a huge bonus!

Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle. 

As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers. 

Location - San Jose, CA OR Israel 

Key Responsibilities 

• Product Technical Ownership 

• Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement 

• Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met 

• Lead development of large-scale chips (300-400mm²) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures 

• Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths 

• Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality.  

• Cross-Functional Technical Leadership 

• Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest 

• Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria 

• Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies 

• Work closely with physical design teams on timing closure, power optimization, and backend execution 

• Process Excellence & Organizational Development 

• Establish and reinforce scalable processes, documentation, and handoffs that support company growth 

• Provide structured, data-driven decision-making and maintain a crisp operational cadence across the product line 

• Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration 

• Model steady, calm leadership, particularly in high-stakes or ambiguous situations 

• Shape engineering culture and talent strategy to support Astera's rapid growth trajectory 

Basic Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 

• 15+ years of experience across architecture, silicon design, validation, systems, or related domains 

• Proven track record of developing large-scale chips (300mm²+) through successful tapeout 

• Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures 

• Strong understanding of RTL design, design verification, DFT, and physical design flows 

• Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures 

• Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership 

• Strong communication and executive presence with the ability to influence at all levels of the organization 

Preferred Qualifications 

• Master's degree in Electrical Engineering or Computer Engineering 

• Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures 

• Experience with advanced process nodes (7nm, 5nm, or below) 

• Background in power management, clocking architectures, or high-speed analog integration 

• Experience operating in fast-growing startups or hyper-scale environments 

Key Leadership Competencies 

• Systems Thinking: See the big picture while managing details 

• Emotional Intelligence: Calm under pressure, empathetic, and influential 

• Adaptability: Thrive in ambiguity and fast-changing environments 

• Execution Discipline: Deliver predictable results without sacrificing innovation 

Role Overview

Astera Labs is seeking a Director, HR Operations to lead and scale our HR infrastructure during a pivotal period of hypergrowth. This role sits at the intersection of HR strategy, technology, and operational excellence—directing the teams and programs that manage our systems, data, employee services, and immigration functions. You'll lead a high-performing team while setting the vision for a best-in-class HR Operations function that delivers seamless employee experiences and drives efficiency through smart automation and AI-enabled solutions.

As a key leader on the HR team, you will oversee HRIS architecture and system implementations, people analytics, employee services, compliance, and global immigration programs. You'll serve as the Center of Excellence for global HR operations, establishing standards, best practices, and scalable processes across all regions. You'll partner cross-functionally with IT, Finance, Legal, and business leaders to ensure our HR infrastructure scales with the pace of our growth. This is an opportunity to shape how a high-growth semiconductor company operates—bringing strategic leadership, operational rigor, and innovation to the employee lifecycle.

Key Responsibilities

• Leadership & Team Development

  • Lead and develop a high-performing HR Operations team across systems, analytics, employee services, and immigration
  • Set strategic direction and priorities for the function, ensuring alignment with company growth objectives
  • Foster a culture of continuous improvement, accountability, and employee-centric service delivery
  • Partner with HR leadership and executives to shape HR strategy and operational roadmaps

• Center of Excellence for Global HR Operations

  • Serve as the Center of Excellence for HR operations, establishing global standards, policies, and best practices
  • Drive consistency and efficiency across all global locations while accommodating regional requirements
  • Provide guidance and support to regional HR teams on operational matters
  • Lead change management efforts to implement standardized processes and systems globally

• HR Systems & Technology

  • Direct the strategy, implementation, and optimization of HRIS platforms and the broader HR technology stack
  • Oversee system integrations across HR, Finance, and IT to create seamless data flows and reporting capabilities
  • Champion the evaluation and deployment of AI-powered tools to automate workflows, enhance self-service, and improve decision-making
  • Ensure maintenance and integrity of HR records and HRIS data

• HR Analytics, Dashboarding & Insights

  • Oversee the HR analytics function, ensuring leadership receives actionable insights on workforce trends, retention, and organizational health
  • Direct the development and maintenance of executive dashboards that provide real-time visibility into key HR metrics
  • Maintain data governance standards and ensure integrity across all HR systems
  • Guide the development of reporting frameworks that enable data-driven HR and business decisions

• Employee Services & Experience

  • Oversee end-to-end employee services including onboarding, offboarding, and HR support
  • Ensure efficient handling of routine employee queries about HR policies and programs
  • Drive the design and continuous improvement of employee-facing processes to deliver a frictionless, consumer-grade experience
  • Lead initiatives to scale operations globally while maintaining compliance and consistency

• Compliance & Employee Data Management

  • Ensure compliance with all applicable labor laws, regulations, and company policies across all locations
  • Oversee employee data management practices, ensuring accuracy, security, and privacy standards are maintained
  • Direct audits and compliance reviews to mitigate risk and maintain regulatory adherence
  • Partner with Legal to stay current on evolving employment law and implement necessary policy updates

• Immigration & Global Mobility

  • Direct the company's immigration program, ensuring timely and compliant visa processing, transfers, and renewals
  • Manage relationships with external immigration counsel and vendors
  • Optimize policies and processes that support the company's ability to attract and retain global talent

Basic Qualifications

• Bachelor's degree in Human Resources, Business Administration, Information Systems, or related field
• 10+ years of experience in HR Operations or HRIS roles
• 5+ years in a leadership capacity, managing and developing teams
• Proven track record leading end-to-end HRIS implementations (Workday, SAP SuccessFactors, or similar platforms)
• Experience overseeing HR analytics, reporting, dashboarding, and data management functions
• Deep understanding of HR compliance, labor laws, and employee data management best practices
• Experience scaling HR operations teams in high-growth or startup environments
• Familiarity with U.S. employment-based immigration programs (H-1B, PERM, green card processes)

Preferred Qualifications

• Experience in the semiconductor or technology hardware industry
• Hands-on experience deploying AI or automation tools within HR processes
• Background in employee services transformation and shared services models
• Strong program management skills with experience directing complex, cross-functional initiatives
• Experience supporting global workforce operations across multiple regions and establishing Centers of Excellence
• Excellent executive presence with ability to influence and advise senior leadership

Salary range is $170,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Overview

As a Firmware Engineering Director/ Manager, you will lead and scale firmware development efforts for Astera Labs’ SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development.

Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs.

This role supports two leadership levels:

• Firmware Engineering Manager
• Firmware Engineering Director

Key Responsibilities

• Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps.
• Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers.
• Provide technical oversight and architectural guidance without being the primary implementer.
• Partner closely with hardware architecture, RTL design, validation, and systems teams to define HW/SW interfaces, development milestones, and integration plans.
• Drive SoC bring-up readiness, firmware validation strategy, and risk mitigation across pre-silicon and post-silicon phases.
• Establish development processes, coding standards, and quality metrics to ensure predictable and scalable execution.
• Support customer engagements as needed, including escalation handling, technical reviews, and roadmap alignment.
• Communicate status, risks, and tradeoffs clearly to executive leadership and cross-functional stakeholders.
•  Director scope: own multi-team delivery, long-term roadmap planning, hiring strategy, and cross-org alignment across multiple product lines.

Firmware Domains Under Management

Teams under this role may span one or more of the following areas:

• PCIe Firmware: PCIe switch and controller firmware (Gen3+), including link training, enumeration, error handling, and performance optimization.
• Ethernet Firmware: Embedded firmware for high-speed Ethernet systems (100G–400G+), including PHY/MAC interaction and link bring-up.
• UCIe / Chiplet Firmware: Firmware for chiplet-based SoC architectures, including die-to-die interconnect initialization and advanced packaging enablement.

Required Experience

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of experience developing or supporting firmware for SoC, silicon, or systems products in compute, networking, or storage domains.
• 5+ years of experience in a people-management role, leading firmware or low-level software teams.
• Strong understanding of bare-metal firmware, RTOS environments, and firmware development lifecycles.
• Experience managing teams working on complex SoCs and high-speed interfaces such as PCIe, Ethernet, DDR, NVMe, or similar.
• Proven ability to lead execution across ambiguous, fast-moving environments with multiple stakeholders.
• Strong communication skills, executive presence, and customer-facing professionalism.
• Authorization to work in the U.S.

Preferred Experience

• Prior experience managing firmware teams delivering PCIe or Ethernet switch products.
• Experience with UCIe, chiplet architectures, or advanced packaging ecosystems.
• Track record of scaling teams through hiring, onboarding, and mentorship.
• Experience working with or supporting customers during bring-up, deployment, or escalations.
• Participation in industry ecosystems such as OCP or OpenBMC.
• Director level: experience owning multi-program delivery, long-term technical roadmaps, and cross-functional organizational planning.

Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.

Job Description

• Seeking a strong technical leader who has delivered multiple SoC products.
• Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs.
• Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications.
• Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.
• Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.
• Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.
• Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness.
• Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions.
• The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.
• Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.
• Drive a culture of technical excellence, accountability, and continuous improvement.
• Manage resource planning, and vendor/partner relationships.

Basic Qualifications

• Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred.
• ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.
• ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• ≥5 years building high performance Engineering teams and validation methodologies.
• Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.
• Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.
• Strong background in debug methodologies, lab infrastructure, and automation frameworks.
• Excellent communication skills and ability to influence executives and cross‑functional partners.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Preferred Experience

• ≥8 years leading validation teams planning, execution and maintaining project visibility.
• ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.
• Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.

The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

Role Overview 

Astera Labs is seeking a Director, Global Talent Acquisition to lead and scale our worldwide recruiting function during a pivotal period of hypergrowth. This is a high-impact leadership role responsible for building and executing the talent acquisition strategy that will fuel our expansion across North America, APAC, EMEA, and India. 

As a key member of the People team, you will own the end-to-end recruiting lifecycle, from executing on the workforce plan and employer branding to team development and operational excellence. You'll partner closely with executive leadership to ensure we attract and hire the world-class engineering and business talent needed to maintain our position as the leader in AI infrastructure connectivity. This role requires a hands-on leader who thrives in fast-paced environments, has deep semiconductor industry expertise, and has a proven track record of building high-performing global recruiting teams from the ground up. 

Key Responsibilities 

Global Talent Acquisition Strategy & Execution 

• Develop and execute a comprehensive global talent acquisition strategy aligned with Astera Labs' aggressive growth objectives and workforce plans 
• Partner with executive leadership and hiring managers to forecast hiring needs, prioritize roles, and deliver against ambitious recruiting targets 
• Build scalable recruiting processes, systems, and metrics to support a rapidly growing organization 

Team Leadership & Development 

• Lead, mentor, and scale a global team of recruiters and recruiting coordinators across North America, APAC, EMEA, and India 
• Establish clear performance expectations, provide ongoing coaching, and foster a culture of excellence, accountability, and continuous improvement 
• Identify and develop future recruiting leaders within the organization 

Semiconductor & Technical Recruiting Excellence 

• Leverage deep semiconductor industry knowledge and networks to source and attract top-tier engineering talent in a highly competitive market 
• Drive innovative sourcing strategies to build robust pipelines for critical technical roles across hardware, firmware, and software disciplines 
• Serve as a trusted advisor to hiring managers on market trends, compensation benchmarking, and competitive intelligence 

Operational Excellence & Employer Branding 

• Implement and optimize recruiting tools, processes, and analytics to drive efficiency and improve candidate experience 
• Partner with Marketing and People teams to strengthen Astera Labs' employer brand and position the company as a destination for top talent 
• Ensure compliance with global hiring regulations and maintain consistency in recruiting practices across all regions 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, or related field 
• 10+ years of progressive talent acquisition experience, including 5+ years in a leadership role managing global recruiting teams 
• Proven experience in the semiconductor or adjacent hardware technology industry 
• Demonstrated success scaling recruiting functions and building teams from scratch in high-growth environments 
• Experience leading distributed teams across multiple geographies (North America, APAC, EMEA, India) 
• Strong understanding of technical roles and the ability to effectively partner with engineering leaders 

Preferred Qualifications 

• Experience at a pre-IPO or recently public technology company during periods of rapid scale 
• Track record of recruiting for highly specialized semiconductor roles (analog/mixed-signal, ASIC, firmware, etc.) 
• Experience implementing or optimizing applicant tracking systems and recruiting analytics platforms 
• Strong executive presence with the ability to influence and build relationships at all levels of the organization 
• Data-driven mindset with experience using metrics to drive recruiting performance and strategic decisions 

Salary range is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

Overview

As a FP&A Business Unit Controller you will be primarily responsible for managing the business partnering relationships for the R&D business units including their annual budgets and quarterly forecast updates and actual performance. The ideal candidate has a strong understanding of financial processes and complex transaction flows with a desire to grow and contribute in a high-growth, fast-paced environment. This role must communicate and organize tasks well to be effective.

Primary Responsibilities

• Establish strong partnership with leadership to help business owners manage their business effectively
• Lead all forecasting and analysis activities for the business owners including: annual plan, quarterly forecast updates and strategic planning
• Develop, analyze, and interpret financial data to evaluate operating results against budget and profitability metrics
• Provide analytical insights, assess risks, and guide senior leadership in strategic decision-making
• Collaborate with Corporate Finance on various projects as needed
• Provide business analysis and support where needed

Qualifications

• 8+ years experience in FP&A and business partnering, preferably in semiconductor or other manufacturing
• Excellent financial modeling and business partnering skills
• Strong analytical and problem solving skills
• Great organization and communication skills, able to work effectively with the business to meet deadlines
• Familiarity with basic GAAP concepts (revenue recognition, accruals, capitalization vs expense)
• Advanced Excel skills
• Familiar with Oracle planning tools
• Strong understanding of financial transaction flows and financial reporting
• Strong feeling of ownership over business processes and desire to improve and make them more efficient
• Bachelor’s degree in Finance or related field

Salary range is $150,000 to $200,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.

Principal Quality Engineer 

Role Summary 

As Principal Quality Engineer based in Aachen, you are the technical authority for quality across our optical product line and regional quality lead for European operations. You will bridge HQ (San Jose) and the Aachen manufacturing site, drive quality integration for in-house optical manufacturing, lead supplier quality for regional semiconductor and optical vendors, and support Asia-based RMA activities for in-region products. 

Key Responsibilities 

Quality‑System Integration: Lead ISO 9001 alignment between San Jose HQ, Aachen, and other regional locations to harmonize procedures, audit schedules, and corrective action processes across both semiconductor and optical product lines. 

Process Development & Implementation: Design, document, and roll out new quality processes, procedures, and work instructions needed to support emerging photonics products and manufacturing capabilities. 

In‑Process Inspection & Controls: Oversee in‑process inspection activities for the in‑house manufacturing operation, establishing SPC, go/no‑go checkpoints, and real‑time defect‑tracking dashboards. 

Supplier Quality (Optics): Provide technical support and quality assurance for optical‑component and optical‑coating suppliers; conduct supplier audits, and drive corrective‑preventive actions (CAPA). 

Supplier Quality (Semiconductor): Serve as the regional point of contact for semiconductor suppliers, monitoring supplier performance, assisting with supplier audits, and leading issue resolution. 

Product Quality: Core Semiconductor Business – Lead technical investigation of field returns, warranty claims, and reliability failures for semiconductor and optical products; coordinate 8D root-cause analysis and interface with Field Application Engineers (FAEs).  

Cross‑Site Liaison: Act as the primary conduit between the Aachen site, other European/EMEA sites, and the San Jose HQ for quality information exchange, escalation handling, and best‑practice sharing. 

Metrics & Reporting:  Define, track, and report key quality KPIs (PPM, DPMO, warranty cost, MTBF, supplier defect rate, etc.) to senior leadership across the BU and corporate HQ. 

Quality Improvement: Lead and demonstrate the application of advanced quality improvement techniques including Lean, Six‑Sigma, and other methods to reduce waste, improve yield, and enhance overall product reliability. 

Education & Experience 

Technical Skills 

Core Competencies 

 Compensation

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and benefits. Astera Labs is committed to fair and equitable pay practices.

Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Overview
This role will be reported to the Sr. Cost Accounting and Inventory Manager and will be primarily responsible for overseeing and managing Astera Labs’ cost accounting processes, ensuring accurate financial reporting and providing insights to support business decision-making. The ideal candidate has semiconductor experience and a strong understanding of GAAP and internal controls structures.

Responsibilities
• Develop, implement, and maintain product cost accounting frameworks, cost accounting systems, processes, and internal controls to support a growing and evolving product portfolio. 
• Own the month-end close process for cost accounting, including preparation of journal entries and reconciliations related to cost of sales, inventory, manufacturing variances, overhead absorption, accruals, reserves, and cost allocations. 
• Lead detailed analysis of product costs, including material costs, subcontractor manufacturing costs, and other direct and indirect manufacturing costs. 
• Analyze and monitor manufacturing and inventory variances, and partner with Business Operations to identify cost drivers, trends, and opportunities for improvement. 
• Manage and enhance the standard cost process, including cost roll-ups, BOM/routing validation, cost component review, and quarterly standard cost updates; ensure standard costs accurately reflect current product structures and manufacturing assumptions. 
• Partner cross-functionally with Operations, Supply Chain, Engineering, and FP&A to evaluate the cost impact of new products, manufacturing process changes, supplier changes, and manufacturing transitions.
• Support new product introduction (NPI) and lifecycle cost management by reviewing initial product cost assumptions, validating costed BOMs, and ensuring timely setup of standard costs in the ERP system. 
• Support gross margin analysis by providing product cost insights, variance explanations, and bridge analyses for forecast, close, and management reporting. 
• Drive cost improvement initiatives by partnering with cross-functional teams to identify and evaluate opportunities for cost reduction and optimization, efficiency improvements, yield enhancement, and supply chain savings.

Qualifications
• 7+ years of experience in Finance or Accounting, including 5+ years of direct experience in product costing, standard cost accounting, and inventory control, preferably in the semiconductor industry. 
• Strong expertise in standard costing, cost roll-ups, BOM/routing structures, inventory valuation, cost of sales, and manufacturing variance analysis. 
• Solid understanding of semiconductor supply chain and manufacturing flows, including subcontract manufacturing, wafer/test/assembly processes, and related cost structures strongly preferred. 
• Thorough knowledge of US GAAP and related inventory and cost accounting principles, including reserves, capitalization, and cost recognition. 
• Excellent organizational, communication, and cross-functional collaboration skills.

Base salary range is $150,000 to $180,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Role Overview

Are you passionate about driving strategic growth through impactful corporate development initiatives in the AI and cloud infrastructure space? Astera Labs is seeking a Manager of Corporate Development to lead and support strategic transactions including acquisitions, investments, and strategic partnerships that will shape the future of AI connectivity.

In this high-visibility role, you will report to the Head of Corporate Development and work closely with cross-functional teams including engineering, product management, and executive leadership to identify and evaluate opportunities that align with Astera Labs' long-term growth strategy. You will be at the forefront of emerging AI infrastructure technologies, developing new business models and driving transactions that accelerate our position as the leader in purpose-built connectivity solutions.

This is a unique opportunity to join a hyper-growth company at the intersection of semiconductors and AI infrastructure, where your work will directly influence strategic decisions and contribute to building the connectivity backbone powering the next generation of data centers.

Key Responsibilities

• Strategic Transaction Leadership

  • Lead and support corporate development transactions through all phases of the transaction lifecycle, from target identification through close
  • Partner with executive and engineering leaders to evaluate opportunities that address strategic gaps and conduct build/buy/partner analysis
  • Lead deal-oriented project management throughout the entire deal lifecycle, ensuring timely execution and stakeholder alignment

• Financial & Strategic Analysis

  • Conduct detailed financial analyses including valuation, pro forma modeling, and investment assessments to evaluate deal alignment
  • Develop executive presentation materials to provide recommendations to the leadership team and board
  • Research adjacent and new market opportunities, including opportunity sizing, target landscaping, and competitive analysis

• Cross-Functional Collaboration & Integration

  • Collaborate with cross-functional teams to drive diligence and validate key assumptions and value drivers
  • Oversee post-merger integration to ensure deals deliver long-term success and structural enhancement for the company
  • Define and continually enhance the company's strategy to acquire new business opportunities and partnerships

• Market Intelligence

  • Develop deep expertise in emerging AI infrastructure technologies, companies, and business models
  • Monitor industry trends and competitive dynamics to inform corporate development strategy

Basic Qualifications

• Bachelor's degree in Business Administration, Electrical Engineering, Computer Science, or related field
• 5+ years of experience in corporate development, investment banking, private equity, venture capital, or related roles
• Experience in the semiconductor, high-tech, or AI infrastructure industry
• Demonstrated experience leading strategic transactions and working with executive leadership
• Strong analytical skills with expertise in valuation, financial modeling, and strategic analysis
• Excellent communication and presentation skills with the ability to convey complex concepts clearly to diverse audiences

Preferred Qualifications

• MBA or advanced degree
• Direct experience with M&A transactions in the semiconductor or data center infrastructure space
• Knowledge of AI/ML infrastructure, PCIe, CXL, or Ethernet technologies
• Proven ability to collaborate effectively across engineering and business functions
• Experience with post-merger integration planning and execution
• Willingness to travel as needed for deals, company training, industry events, and conferences

Salary range is $140,400 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description: 

As an Astera Labs Early Career Product Application Engineer, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products. 

Basic Qualifications 

• Strong academic and technical background in electrical engineering.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!  

Required Experience  

• Technical ownership of issue resolution
• Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.  
• Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences. 

Preferred experience 

• Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment. 
• Development/support for PCIe or Ethernet Switch or Retimer products. 
• PCIe compliance testing methodology and troubleshooting. 
• Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages. 
• Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc. 

The base salary range is $104k USD - $150k USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job Description:

As an Astera Labs Principal AEC / AOC Program Manager you will play a crucial role in overseeing the planning, coordination, and execution of manufacturing projects featuring Astera Labs' AEC / AOC portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. You will ensure that production processes run smoothly, meet quality standards, and are completed on time and within budget and responsible for manufacturing from NPI to mass production phases. To accomplish that, you will be working closely with designers, the manufacturing team, suppliers, and contract manufacturers. This role is expected to travel up to 30% of the year and will require business English skills.

Job Responsibilities

• Project Planning and Execution
• Develop Project Plans: Create detailed project plans, including schedules, budgets, resource allocation, and timelines.
• Coordinate Production Activities: Oversee all aspects of the manufacturing process, ensuring alignment with project goals.
• Monitor Progress: Track project milestones, deliverables, and deadlines to ensure timely completion.
• Problem Solving: Address and resolve issues that arise during the manufacturing process to avoid delays.
• Change Management
• ECO: Drive Engineering Change Order and Deviation processes in product design, manufacturing, and disposition
• PLM: Use Product Lifecycle Management systems such as Agile, Arena
• Ability to evaluate change including trade-offs
• Cross-Functional Team Leadership
• Lead Cross-Functional Teams: Manage and lead cross-functional teams, including engineering, production, quality, supply chain, and logistics.
• Facilitate Communication: Ensure effective communication between different departments and stakeholders involved in the manufacturing process.
• Assign Tasks: Delegate tasks and responsibilities to team members and monitor their performance.
• Budget and Cost Management
• Manage Budgets: Develop and manage project budgets, ensuring costs are controlled and within budget.
• Cost Analysis: Conduct cost-benefit analyses and identify opportunities for cost savings and efficiency improvements.
• Financial Reporting: Provide regular financial updates to senior management, highlighting any variances from the budget.
• Quality Assurance
• Ensure Quality Standards: Ensure that manufacturing processes meet the required quality standards and regulatory requirements.
• Implement Quality Controls: Develop and implement quality control procedures and processes to minimize defects and rework.
• Continuous Improvement: Identify areas for improvement and implement lean manufacturing practices to enhance efficiency and quality.
• Supply Chain Management
• Work closely with Business Operations / Supply Chain team to ensure timely delivery of materials and components.
• Risk Management
• Identify Risks: Identify potential risks in the manufacturing process, including supply chain disruptions, equipment failures, or quality issues.
• Develop Mitigation Plans: Create and implement risk mitigation plans to minimize the impact of identified risks.
• Monitor and Report: Continuously monitor risks and provide regular updates to stakeholders.
• Stakeholder Management
• Engage Stakeholders: Maintain strong relationships with key stakeholders, including customers, suppliers, and internal teams.
• Stakeholder Reporting: Prepare and present reports on project progress, challenges, and successes to senior management and other stakeholders.
• Regulatory Compliance
• Ensure Compliance: Ensure that all manufacturing processes comply with relevant industry regulations, safety standards, and environmental laws.
• Documentation: Maintain accurate documentation of manufacturing processes, quality controls, and compliance activities.
• Technology and Innovation
• Adopt New Technologies: Identify and implement new technologies and processes that can improve manufacturing efficiency, quality, and cost-effectiveness.
• Process Optimization: Continuously seek ways to optimize manufacturing processes through automation, innovation, and best practices.
• Reporting and Documentation
• Project Reports: Prepare detailed project reports, including progress updates, financial status, and quality metrics.
• Documentation: Ensure all project documentation is accurate, up-to-date, and easily accessible for future reference.

Qualifications

• Educational Background
• Bachelor’s Degree (Required): A bachelor’s degree in electrical engineering, manufacturing, industrial engineering, mechanical engineering, or a related field.
• Advanced Degree (Preferred): A Master’s degree in business administration (MBA), engineering management, or a related field can be an advantage, especially for leadership roles.
• Professional Experience
• Relevant Experience: A minimum of 8 years of experience in manufacturing, engineering, or production environments, with several years in a project management or program management role.
• Leadership Experience: Proven experience leading cross-functional teams and managing complex projects from concept through production.
• Industry-Specific Experience: Experience in electronics industry. Experience with high speed / high complexity projects preferred.
• Technical Skills
• Manufacturing Processes: In-depth knowledge of manufacturing processes, production techniques, and industry best practices.
• Project Management: Strong project management skills, including planning, scheduling, budgeting, and resource management.
• Lean Manufacturing: Familiarity with lean manufacturing principles, Six Sigma, and other process improvement methodologies.
• Quality Assurance: Knowledge of quality management systems (e.g., ISO standards) and quality control processes.
• Supply Chain Management: Understanding of supply chain management, procurement, and logistics in a manufacturing environment.

Job Description:

As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.
• 8+ years of experience supporting or developing complex analog IC designs.

Required Experience:

• Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
• Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
• Solid track-record for implementation of analog circuits high-speed data transmission.
• Design and tape out experience in advanced CMOS nodes (ex. 7nm, 5nm 3nmFinFET) is a must.
• Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
• Knowledge of TIA design and drivers for optical applications is highly desirable
• Experience in RFIC design for wireless or wireline communication systems is highly desirable.
• Strong technical independent contributor with a proven ability to drive results.
• Excellent teamwork, presentation, and documentation skills.
• Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
• Strong experience in lab chip bring-up and debugging efforts.

Preferred Experience:

• Relevant research publications and/or patents in analog or RF IC design.
• Familiarity in programming/scripting languages such as Python, Matlab, or C.
• Experience with PCB design.
• Familiarity with Verilog RTL or DSP design concepts.
• Knowledge of optical transceivers.
• Expertise in ESD protection techniques and IC packaging methodologies.

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Are you passionate about driving business growth for the next generation of data infrastructure with hyperscale and AI platform providers – through customer intimacy, deal negotiation and commercial strategies?

We are seeking a highly proficient and experienced business manager to join our team at Astera Labs. As a key member of our business management team, you will work closely with customers, sales, product marketing, operations and other internal cross-functional teams to accelerate revenue and execute on our deal pipeline for critical opportunities. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of commercial expertise and customer insight across our product portfolio. 

Based in San Jose, CA, this position requires an in-person presence with travel to customers. 

Key Responsibilities 

• Lead customer deal pipeline: Work closely with sales and lighthouse customers secure strategic design-wins and progress pipeline towards design-in and conversion to contracts and purchase orders. 
• Own commercial frameworks: Set, align and approve pricing and commercial terms for key deals and establish consistent pricing strategies and methodologies across products in partnership with product marketing teams.
• Facilitate customer and segment playbooks: Leverage commercial, market and product expertise to support strategy definition and partner with sales to develop playbooks for key customers, segments and regions – covering key elements such as customer insights, relationship mapping, competitive analysis, win/loss analysis solution positioning and negotiation plans. 
• Support business process innovation: Work closely with business functions to enable the next phase of scale through identifying, prioritizing and executing key operational improvements such as new operating procedures, tools or organizational clarity. 

Qualifications 

• Bachelor’s degree in engineering, computer science or business/marketing
• 10+ years of experience in, product marketing, sourcing, supply chain, operations, sales or other customer-facing product roles within the semiconductor industry
• Strong strategic thinking and analytical skills, with the ability to translate customer pain points into innovative solutions (deals, partnerships, or product adoption)
• Proven track record of negotiating and influencing customers, leading to key agreements, contracts or purchase orders
• Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner 
• Broad understanding of high-speed protocols (PCIe is required; Ethernet, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure 
• Results-oriented mindset with a focus on driving measurable impact and achieving business objectives 
• Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment 
• Willingness to travel as needed for customer meetings, industry events, and trade shows 

Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.

Key Responsibilities

• Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
• Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
• Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
• Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
• Work with RTL designers to troubleshoot and resolve design issues.
• Drive verification strategy and methodology for SoCs in server and networking applications.

Required Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred).
• 8+ years of experience in SoC verification, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
• Familiarity with verification of switching architectures, including packet processing and forwarding engines.
• Excellent communication skills and ability to work independently with minimal supervision.

Preferred Qualifications

• Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
• Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
• Knowledge of Ethernet/PCIe switching and central buffer architectures.
• Experience with emulation platforms and hardware-software co-verification

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.

Key Responsibilities

• Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
• Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
• Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
• Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• SystemVerilog/Verilog familiarity.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Principal Power and Board Design Engineer 

Overview:
We are seeking a highly skilled and experienced Power and Board Design Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.

Key Responsibilities:

• Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.

• Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance mismatches.

• Develop and implement board-level designs, to meet electrical and mechanical requirements with a deep understanding of PCB layout rules and constraints.

• Implement thermal solutions to maintain optimal operating temperatures for components.

• Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also will be asked to do the same evaluation on overall system level design components.

• Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.

• Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.

• Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.

• Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.

Qualifications:

• Education: Bachelor’s or Master’s degree in electrical engineering or a related field.

• Experience: 8-10 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.

• Technical Skills:

  • Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.

  • Strong understanding of power integrity principles and techniques.

  • Experience with power component selection and vendor collaboration.

  • Hands-on experience with debugging power-related issues using lab equipment.

• Soft Skills:

  • Excellent problem-solving and analytical skills.

  • Strong communication and teamwork abilities.

  • Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Experience with high-speed interfaces such as PCIe, DDR, and USB.

• Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.

• Familiarity with Design for Manufacturability (DFM) considerations.

• Experience in thermal management and reliability analysis.

Why Join Us:

• Work on cutting-edge ASIC designs in a collaborative and innovative environment.

• Opportunity to influence power design strategies and contribute to product success.

• Access to state-of-the-art tools and resources to enhance your skills and career growth.

If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.

Base pay range for this role is $209,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role Overview

Astera Labs is seeking a Principal Product Applications Engineer to join our Aries PCIe Retimer team and serve as a critical technical bridge between our customers and engineering organization. As AI infrastructure demands explode, our Aries Smart Retimers are enabling the high-speed, low-latency PCIe connectivity that powers the world's most advanced data centers—and you'll be at the center of that growth.

In this high-impact role, you'll work directly with hyperscalers, OEMs, and system builders to drive successful adoption of our Aries PCIe products. You'll combine deep technical expertise with customer-facing skills to solve complex system-level challenges, create compelling technical documentation, and influence product direction based on real-world customer needs. This is an opportunity to shape how next-generation AI and cloud infrastructure connects and scales.

You'll collaborate cross-functionally with design engineering, validation, sales, and marketing teams while building strong relationships with customers who are defining the future of computing. If you thrive at the intersection of cutting-edge silicon and customer success, this role offers exceptional visibility and impact.

Key Responsibilities

Customer Technical Engagement

• Serve as the primary technical resource for customers during pre-sales evaluation and post-sales deployment of Aries PCIe retimers
• Deliver technical presentations, product training, and demonstrations to customer engineering teams
• Build trusted advisor relationships with key accounts and drive product adoption

System-Level Debug & Validation Support

• Lead root cause analysis and debugging of complex PCIe signal integrity and protocol issues in customer systems
• Support customer lab bring-up, characterization, and validation activities
• Develop and execute test plans to reproduce and resolve customer-reported issues

Technical Documentation & Enablement

• Create application notes, reference designs, and best practices guides for PCIe system implementation
• Develop collateral that accelerates customer time-to-deployment
• Contribute to product documentation including datasheets and user guides

Cross-Functional Collaboration

• Partner with product management and engineering to translate customer feedback into product requirements
• Support sales teams with technical expertise during customer engagements
• Represent the voice of the customer in internal roadmap and feature discussions

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in applications engineering, technical support, or system engineering roles
• Strong understanding of PCIe architecture, protocol, and electrical specifications (Gen4/Gen5/Gen6)
• Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BERT tools
• Experience debugging high-speed serial interfaces at both the physical and protocol layers
• Excellent written and verbal communication skills with ability to explain complex technical concepts
• Develop and modify firmware using C to implement features, optimize performance, and resolve technical issues
• Travel to customer sites worldwide to provide on-site technical support, conduct system integration, and drive issue resolution

Preferred Qualifications

• Experience with PCIe retimers, redrivers, or similar connectivity components
• Familiarity with server, storage, or GPU system architectures
• Background in signal integrity analysis and simulation tools
• Scripting proficiency (Python, TCL) for test automation and data analysis
• Prior experience working directly with hyperscale or enterprise data center customers
• Track record of creating high-quality technical documentation and application notes

Salary range is $158,400 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description: 

As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to ODMs to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. We need experience supporting the development and designing-in of semiconductor products for PCIe/CXL. There are opportunities to support key ODMs directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products. 

Basic Qualifications 

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred. 
• Minimum of 10 years’ experience designing in complex SoC/silicon products with a high speed (preferably PCIe) interface. 
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!  

Required Experience 

• Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 4.0 at a minimum, some experience with 5.0/CXL preferred. 
• Silicon/System bring-up and debug experience in customer systems.  
• Technical ownership of issue resolution: Driving and directing internal teams, and driving communication to customers through FAE and sales teams. 
• Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.  
• Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences. 
• Global customer engagement support, with travel as required for on-site activities, reviews, and system bring-up.

Preferred experience 

• Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment. 
• Development/support for PCIe or Ethernet Switch or Retimer products. 
• PCIe compliance testing methodology and troubleshooting. 
• Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages. 
• Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc. 

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader with products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Texas, Taiwan, China, Canada, and Israel. 

As an Astera Labs Product Applications Engineer, you will be part of a team that supports design-in of Astera Labs’ portfolio of connectivity products by the world’s leading cloud service providers and server and network OEMs. In this role, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. You will investigate and duplicate issues reported by customers, and drive critical issues to resolution. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.

Basic Qualifications

• Strong academic and technical background in electrical, electronics, or computer engineering or a closely related field. At a minimum, an engineering bachelor’s degree is required. A master’s degree is preferred.
• A minimum of 12 years’ experience working with cloud service providers or server or network OEM customers to design in complex SoC/silicon products for server, storage, and/or networking applications.
• Entrepreneurial spirit, open-minded approach, and can-do attitude. Think and act with the customer in mind!

Required Experience

• Silicon/system bring-up and debug experience in customer systems.
• Strong knowledge of embedded FW development and in-system debug
• Firmware development with C-language, scripting with Python or other equivalent programming languages.

• Strong knowledge of PCIe protocol, including LTSSM, EQ, DMA, etc.
• Strong knowledge of NRZ/PAM4 SerDes level debugging (TX/RX Equalization) in PCIe, Ethernet (25G and above), etc.
• Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes.

• Broad knowledge of NRZ/PAM4 SerDes-based protocols such as PCIe or Ethernet (25G and above).
• Understanding of Data Center systems such as servers, compute nodes, JBOGs/JBODs, and networking switches/routers/interconnects, etc.
• Technical writing skills and the ability to generate clear, precise documentation including datasheets, application notes, and similar guides for both internal audiences and customers.

Preferred Experience

• Broad knowledge of signal processing and ECC coding for communications
• Device driver development
• Development/support for PCIe or Ethernet switch products
• Working with silicon characterization/validation teams to ensure desired device performance is readily achievable in customer systems.
• Knowledge of simulation/modeling, schematic capture, and PCB layout tools from Cadence, Altium and others.
• Knowledge of simulation tools such as Keysight ADS, SiSoft QCD, and others, for IBIS-AMI analysis.
• A strong background in high-speed board design and techniques for preserving signal integrity.

Job Description: 

As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. Astera Labs is seeking a Principal Product Applications Engineer in Shanghai, China with experience supporting the development and designing-in of semiconductor products for PCIe/CXL. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.

Basic Qualifications

· Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred.

· Minimum of 10 years’ experience designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.

· Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Required Experience

· Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 5.0 at a minimum, some experience with 6.0/CXL preferred.

· Silicon/System bring-up and debug experience in customer systems.

· Technical ownership of issue resolution: Driving and directing internal teams toward issue resolution. Driving communication with customers, FAEs, and sales team members

· Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.

· Comfort working with software/firmware associated with semiconductor products, such as: Firmware development with C-language, scripting with Python or other equivalent programming languages.

Preferred experience

· Triaging complex customer reported issues which require taking into account multiple layers of conditions. For instance, silicon, firmware, hardware board design, and system environment.

· Experience with common data center BMC implementation, and BIOS configuration

· Development/support for PCIe or Ethernet Switch or Retimer products.

· PCIe compliance testing methodology and troubleshooting.

· Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc.

Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure?  

We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing, engineering and other internal cross-functional teams to define and deliver competitive silicon, hardware and software solutions.  

This is a unique opportunity to play a pivotal role in the success of our Taurus Ethernet Retimer portfolio. We are scaling our Taurus product management team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team.   

Based in San Jose, this position requires an in-person presence with travel to customers.  

Key Responsibilities  

• Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback. 
• Lead product planning: Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch. 
• Lead customer technical engagement: Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design wins throughout the product lifecycle. 
• Support go-to-market: Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning.  

Qualifications  

• Deep understanding of high-speed protocols (Ethernet is required; UAL, PCIe, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure 
• 10+ years of experience in product management, applications engineering or other technical product roles within the semiconductor industry
• Proven track record of defining and launching successful semiconductor products
• Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products 
• Excellent communication skills with the ability to articulate complex technical concepts in a clear and compelling manner 
• Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment 
• Experience working with customers and partners to understand their needs and drive product definition 
• Willingness to travel as needed for customer meetings, industry events, and trade shows  

Principal Product Manager – Smart Cable Modules 

Astera Labs is at the center of the AI infrastructure revolution, and our Smart Cable Modules are critical to enabling the high-bandwidth, low-latency connectivity that next-generation data centers demand. We're looking for a Principal Product Manager to own and drive this exciting product portfolio—working directly with hyperscalers and AI platform providers to define solutions that push the boundaries of what's possible. 

In this role, you'll be the connective tissue between our customers, engineering teams, and go-to-market functions. You'll translate complex customer requirements into differentiated products, guide development from concept through launch, and help secure design wins with the world's most demanding infrastructure builders. This is a high-visibility, high-impact opportunity to shape products that will power the future of AI and cloud computing. 

Based in San Jose, this position requires an in-person presence with regular travel to customers. 

Key Responsibilities 

• Product Definition & Strategy 
  • Define detailed product requirements for Smart Cable Modules, prioritizing features, enhancements, and bug fixes based on business goals and customer feedback 
  • Translate market trends and customer insights into a compelling product roadmap 
  • Drive competitive differentiation through deep understanding of PCIe, Ethernet, and system architectures 

• Customer Engagement & Design Wins 
  • Serve as the primary technical product interface with lighthouse customers, translating their needs into actionable product requirements 
  • Secure and support new design wins throughout the product lifecycle 
  • Build strong relationships with hyperscalers and AI platform providers to ensure Astera Labs remains their connectivity partner of choice 

• Cross-Functional Leadership 
  • Collaborate with engineering to drive products from ideation through launch, ensuring on-time delivery of competitive solutions 
  • Partner with product marketing on go-to-market planning, sales enablement, competitive analysis, and product positioning 
  • Work across Astera Labs functions to align priorities and drive consensus in a fast-paced environment 

Basic Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Science, or related technical field 
• 8+ years of experience in product management, applications engineering, or technical product roles within the semiconductor industry 
• Deep understanding of high-speed protocols (PCIe, Ethernet, CXL) and system architectures used in cloud and AI infrastructure 
• Proven track record of defining and launching successful semiconductor products 
• Strong communication skills with the ability to articulate complex technical concepts to both technical and business audiences 
• Willingness to travel for customer meetings, industry events, and trade shows 

Preferred Qualifications 

• Master's degree in Electrical Engineering, Computer Science, or related field 
• Experience working directly with hyperscalers or large cloud infrastructure providers 
• Background in cable modules, retimers, or high-speed connectivity products 
• Experience driving products through full lifecycle from concept to high-volume production 
• Strong strategic thinking and analytical skills with ability to translate customer pain points into competitive products 
• Experience speaking Mandarin

Salary range is $158,400 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite.

Basic Qualifications

• Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.
• 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
• Have a proven track record with defining hardware system constraints and high-speed technology roadmaps.
• Cross-functional design mentality with the electrical design community to develop systems.
• Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.
• Proven track record solving problems independently, preferably as a tech lead.
• Entrepreneurial, open-minded behavior, and can-do attitude.
• Authorized to work in the US and start immediately.

Required Experience

• Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects
• 2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets
• EM modeling of BGA and connector structures
• High-speed SERDES channel simulation, and equalization
• PI simulations with Ansys/Cadence toolsets
• Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
• Working knowledge of PCB fabrication limits and trade-offs
• Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections.
• Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome.

Overview: 

The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance.

Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs.

Basic Qualifications:

•  Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
•  ≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
•  Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead
• Required experience
• Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet
• Strong problem-solving skills, ability to solve problems independently
• Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

•  Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
•  Familiarity with PCIe or Ethernet especially Electrical Compliance sections
•  Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
•  Working knowledge of C or C++ for embedded FW
•  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
•  Working knowledge of common serial data specifications such as I2C, SPI, etc
•  Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
•  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is USD 203,00 - USD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Overview

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 10 + years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, executing validation plans for complex SoC designs. 

Required Experience:

• Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet.
• Familiarity with Electrical Compliance section of PCIe Base Spec and CEM Spec
• Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ, CDR, etc and concepts such as PAM4
• Experience in PRBS testing and optimization of high-speed PCIe data links over short, med, and long channels
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops
• Hands-on experience with signal integrity, especially as it relates to PCIe testing, Channel Loss budgeting, and de-embedding
• Working knowledge of C or C++ for embedded FW, experience using git-based version control such as github
• Familiarity with PCIe standards and both NRZ and PAM-4 signaling
• Working knowledge of common serial data specifications such as I2C, SPI, etc
• Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is $185,000 USD - $230,000 USD. Your base salary will be determined based on your experience and the pay of employees in similar positions. 

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description:

We are seeking an experienced leader to drive Supplier / Manufacturing Quality Engineering to anchor our global supplier quality efforts across both Astera Lab’s semiconductor and board-level products. In this role, candidates will drive leading supplier quality across key manufacturing partners including IC fabs, OSAT’s, and PCB/PCBA vendors. A strong foundation in supplier quality engineering, uniquely paired with experience in advanced data analytics (including AI and machine learning) for predictive quality, risk assessments, and product quality analytics will be highly valuable to this role.

Responsibilities:

Supplier Quality Management

· Nurture winning partnerships across all our strategic manufacturing suppliers: semiconductor wafer fabs, advanced packaging & test (OSAT), boards & assemblies (PCB / PCBA / SMT), substrates / interposers, probe cards, and passive components.

· Develop robust supplier selection and onboarding processes in collaboration with Design, Procurement, Business & Engineering Operations teams.

· Define, build, and manage the systems to collect the data (KPI’s) needed to track supplier performance and drive continuous improvement.

· Audit to assess the effectiveness of supplier process controls, manufacturing capabilities, and overall quality management system.

· Coach suppliers by sharing your deep manufacturing experience and knowledge.

· International travel as needed, potentially on short notice. There is no minimum amount but prepare to accommodate up to 20%.

Advanced Data Analytics & AI/ML

· Create data collection methods to enable product and supplier advanced data analytics needed for monolithic, chiplet, and board products. Data sources will include manufacturing inline controls, production test (including data collection from advanced embedded agents), and failure analysis activities.

· Leverage data into quality models & methods to predict product quality issues and supply chain risks.

· Integrate AI/ML tools into quality systems and dashboards (e.g., outlier screening, automated defect detection, trend analysis, real-time alerts).

· Experience with AI/ML tools is a plus but not required; ability to work with technical partners on model development is key.

Cross-functional Collaboration

· Interface with R&D, NPI, product engineering, ops and other engineering teams to provide supplier input into product design and DFX.

· Support early supplier involvement and ensure quality requirements needed for manufacturability & testability are achieved, and learnings are propagated appropriately to other products in production & development.

· Represent supplier quality as needed in line failure reviews, excursion management, material reviews (MRB), and CAPA processes.

· Partner with engineering and manufacturing teams to conduct quarterly engineering reviews, evaluate supplier changes (PCN), and assess supplier risks.

· With engineering engagement, lead quality audits, and corrective action activities using tools such as 8D, 5-why, and FMEA.

Education & Experience

· Bachelor’s or Master’s degree in Engineering or equivalent experience.

· 8+ years of career progression in supplier quality engineering in the semiconductor and/or board-level electronics industry.

· 3+ years direct experience working embedded within a high-volume advanced manufacturing operation in an engineering role.

· Experience with supplier development in Asia with global manufacturing supply chains.

· Six Sigma or ASQ certification a plus

Technical Skills

· Strong knowledge of IC fabrication, packaging (including chiplet), board assembly (SMT), and test processes.

· Familiarity with reliability qualification methodologies in the application of IPC, Telcordia, JEDEC requirements.

· Proficiency with quality engineering tools (FMEA, APQP, PPAP, SPC, OE, etc.).

· Experience using analytics tools (e.g., JMP, SQL, Excel) to support quality insights. Exposure to AI/ML frameworks is a plus, but not required.

· Fluent in English and Mandarin

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Education and Experience Requirements

• Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 8-12 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Desired Qualifications

• Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
• Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
• Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
• Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
• Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
• Experience with PAM4 SerDes validation (200G/100G/50G)
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
• Knowledge of Signal Integrity simulation tools
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Job Description

We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
• Familiar with high-speed load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with using Advantest 93k ATE platform.
• Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.
• Experience in running External loopback at wafer sort.
• Familiarity with modern databases

Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure?  

We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing, engineering and other internal cross-functional teams to define and deliver competitive silicon, hardware and software solutions.  

This is a unique opportunity to play a pivotal role in the success of our Aries PCIe Retimer portfolio. We are scaling our Aries product management team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team.   

Based in San Jose, this position requires an in-person presence with travel to customers.  

Key Responsibilities  

• Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback. 
• Lead product planning: Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch. 
• Lead customer technical engagement: Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design wins throughout the product lifecycle. 
• Support go-to-market: Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning.  

Qualifications  

• Deep understanding of high-speed protocols (PCIe is required; Ethernet, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure 
• 10+ years of experience in product management, applications engineering or other technical product roles within the semiconductor industry
• Proven track record of defining and launching successful semiconductor products
• Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products 
• Excellent communication skills with the ability to articulate complex technical concepts in a clear and compelling manner 
• Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment 
• Experience working with customers and partners to understand their needs and drive product definition Willingness to travel as needed for customer meetings, industry events, and trade shows  

If you are passionate about driving innovation and shaping the future of data center connectivity through world-class products, we encourage you to apply. Join Astera Labs in unleashing the potential of cloud and AI infrastructure!  

Job Description

We are seeking a detail-oriented Quality Systems Engineer / PLM Analyst to support the administration and continuous improvement of our Quality Management System (QMS) and Product Lifecycle Management (PLM) processes.

This role will support the management of product data, engineering change control, and document control within Arena PLM, while also contributing to key QMS activities such as CAPA management, internal audits, and controlled documentation. The position plays a critical role in ensuring accurate product lifecycle data, effective configuration management, and compliance with quality standards across semiconductor, hardware, and optical product lines.

The ideal candidate will work cross-functionally with engineering, manufacturing, quality, and operations teams to ensure efficient product development processes and strong quality system governance.

Key Responsibilities

PLM System & Product Data Management

• Support administration and daily operations of Arena PLM, including product records, document control, and engineering change processes.
• Create and maintain items, Bills of Materials (BOMs), and product structures for semiconductor, hardware, and optical products.
• Coordinate and manage Engineering Change Orders (ECOs) including creation, workflow routing, and release tracking.
• Maintain document revision control, lifecycle states, and product configuration data within the PLM system.
• Support New Product Introduction (NPI) processes including part setup, BOM releases, and product data readiness.
• Ensure accurate data synchronization between PLM and ERP systems (e.g., Oracle ERP) in collaboration with IT and operations teams.
• Assist with PLM data governance, cleanup, and process standardization initiatives.

Quality Management System (QMS) Support

• Support the administration and continuous improvement of the company’s Quality Management System (QMS).
• Maintain controlled documents, procedures, and records, ensuring proper revision control and accessibility.
• Assist with Corrective and Preventive Actions (CAPA) tracking and documentation.
• Participate in Material Review Board (MRB) processes and nonconformance documentation.
• Support internal and external audits, including documentation preparation and follow-up actions.
• Maintain quality records and metrics used in management reviews and compliance reporting.
• Ensure alignment between engineering changes in PLM and updates to quality system documentation.

Cross-Functional Collaboration

• Serve as a liaison between engineering, manufacturing, operations, and quality teams to support effective PLM and QMS processes.
• Provide training and guidance to users on PLM system usage and document control procedures.
• Support initiatives to improve product data management, engineering change processes, and quality system efficiency.
• Drive adoption and compliance with PLM and quality documentation processes across the organization.

Required Qualifications:

• Bachelor’s degree in Engineering, Science, Quality, or a related technical field.
• 3–5 years of experience supporting PLM systems and/or Quality Management Systems.
• Experience working with PLM platforms such as Arena PLM or similar product lifecycle management systems.
• Familiarity with engineering change management (ECO/ECN), BOM management, and document control processes.
• Experience supporting QMS processes such as CAPA, MRB, internal audits, and document control.
• Experience working with ERP systems such as Oracle ERP or similar platforms.
• Strong organizational and analytical skills with high attention to detail.
• Excellent communication and cross-functional collaboration skills.

Preferred Skills: 

• Experience supporting product development environments in semiconductor, electronics, or hardware manufacturing.
• Familiarity with quality standards such as ISO 9001.
• Experience supporting New Product Introduction (NPI) processes.
• Knowledge of configuration management and product data governance.
• Experience generating reports or analytics from PLM or ERP systems.

Department: Sales Operations /
Reports To: Sales Operations Director
Location: Taiwan

Employment Type: Full-Time

Position Overview:

We are seeking a highly organized and detail-oriented entry-level candidate to support our sales operations in a fast-paced, high-tech environment. This role is responsible for processing customer purchase orders for Astera Labs product portfolio—ensuring compliance with internal policies, licensing terms, and revenue recognition guidelines. You will collaborate closely with Sales, Legal, Finance, Quality, Supply Chain and Logistics teams to ensure orders are booked, billed, and delivered accurately and on time.

Key Responsibilities:

• Review and enter orders into the order management system (e.g., Oracle ERP) including customer purchase orders (POs), samples and RMAs
• Validate orders for accuracy, contract terms, licensing details, and revenue recognition compliance (SOX compliance and ISO)
• Coordinate with Sales, Legal, and Finance to resolve order discrepancies, billing issue, payment term/incoterm compliance or missing documentation
• Track order status, fulfillment timelines, and escalate delivery or provisioning issues when needed
• Generate order confirmations, invoices, and shipping documents where applicable
• Support month-end and quarter-end order processing deadlines in coordination with Finance
• Maintain accurate records of all orders including qty, customer communications, and contract terms in CRM/ERP systems
• Drive RMA approval process and manage RMA request from customer communication, system handling to fulfillment.
• Act as a liaison between Sales, Product Marketing, Supply Chain, and Customers to manage and support sample requests—particularly for NPI products and development boards.
• Ensure fast-turnaround on sample process and maintain accurate records of all sample-related activities in sample tracking system.
• Contribute to process improvements and automation initiatives to increase operational efficiency

Qualifications:

• Bachelor's degree in Business Administration, Finance, or related field (or equivalent experience)
• 2+ years of experience in order administration or sales operations, preferably in the high-tech industry
• Familiarity with CRM and ERP systems (Salesforce, Oracle, CPQ, SAP, or similar)
• Understanding of supply chain, forecasting, billing terms, incoterms and revenue recognition principles
• Strong analytical, organizational, and problem-solving skills
• High attention to detail and ability to work independently under tight deadlines
• Excellent written and verbal communication skills
• Strong Excel and data analysis skills; experience with PPT and BI tools (e.g., PowerBI) is a plus

Preferred Skills:

• Experience working with cross-functional teams in a global technology company
• Knowledge of semiconductor industry and experience in customer interfacing role.
• Understanding of SOX compliance and f audit requirements
• Prior experience with quote-to-cash workflows

Working Environment:

• On-site work environment
• Fast-paced, deadline-driven high-tech setting
• May require extended hours during fiscal close periods