Director, Firmware Engineering (PCIe)

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

The mission of this role is to lead and scale the firmware engineering organization responsible for architecting and delivering firmware and microcontroller subsystems for Astera Labs’ SoC and systems products.

As a Director of Firmware Engineering, you will own the technical vision, execution strategy, and organizational development of the firmware team. You will be responsible for delivering highly differentiated firmware capabilities that are foundational to Astera Labs’ products across networking and compute infrastructure platforms.

This is a hands-on leadership role requiring both deep technical expertise and strong people leadership. Firmware is considered equally important to hardware at Astera Labs, and this role will have significant customer visibility and cross-functional influence across silicon, systems, networking, and compute architecture teams.

Key Responsibilities

• Lead, mentor, and scale a high-performing firmware engineering team, including hiring and organizational development
• Define and drive the firmware architecture and roadmap aligned with product and company strategy across networking and compute platforms
• Partner with hardware, ASIC, and system architecture teams (including network and compute architects) to define and deliver robust HW-SW interfaces
• Oversee execution of firmware development across multiple programs, ensuring quality, scalability, and on-time delivery
• Drive customer engagement, including supporting bring-up, debugging, and feature enablement in networking and compute deployments
• Establish best practices for firmware development, validation, release processes, and CI/CD infrastructure
• Influence product direction through deep technical insight into PCIe, system architecture, and network/compute workloads
• Foster a culture of ownership, innovation, and execution excellence

Basic Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Science, or related field; Master’s preferred
• 12+ years of experience in firmware/software development for complex SoC/silicon products in networking and/or compute systems (server, storage, hyperscale infrastructure)
• 5+ years of experience leading and managing high-performing engineering teams
• Proven track record of delivering complex firmware systems from architecture through production
• Strong understanding of modern data center architectures spanning networking and compute domains
• Strong ability to operate at both strategic and execution levels in a fast-paced environment
• Excellent communication skills and ability to engage effectively with customers and cross-functional teams

Required Experience

• Deep expertise in PCIe (Gen5 and beyond), including debugging with analyzers and exercisers
• Strong proficiency in C/C++ and experience building firmware SDKs
• Experience with Python for automation, validation, and firmware quality
• Experience working closely with ASIC/SoC teams to define and validate HW-SW interfaces
• Familiarity with firmware development environments (gcc/Make, GitHub, CI/CD pipelines, documentation tools)
• Experience with system-level interfaces including PCIe controllers, DDR, NVMe, and AMBA/AHB
• Hands-on experience with networking and/or compute system platforms, including server or hyperscale deployments

Preferred Experience

• Experience with PAM4 SerDes and understanding of link-level behaviors (equalization, CDR, link budgets)
• Hands-on experience with PCIe-based systems in server, storage, networking, and compute environments
• Experience with AIC firmware (NICs, switches) or PCIe/Ethernet switching stacks
• Experience working with data center networking stacks or compute acceleration platforms (e.g., GPU/AI systems)
• Background in embedded firmware for high-performance connectivity products

Job Overview

As a Firmware Engineering Director/ Manager, you will lead and scale firmware development efforts for Astera Labs’ SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development.

Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs.

This role supports two leadership levels:

• Firmware Engineering Manager
• Firmware Engineering Director

Key Responsibilities

• Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps.
• Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers.
• Provide technical oversight and architectural guidance without being the primary implementer.
• Partner closely with hardware architecture, RTL design, validation, and systems teams to define HW/SW interfaces, development milestones, and integration plans.
• Drive SoC bring-up readiness, firmware validation strategy, and risk mitigation across pre-silicon and post-silicon phases.
• Establish development processes, coding standards, and quality metrics to ensure predictable and scalable execution.
• Support customer engagements as needed, including escalation handling, technical reviews, and roadmap alignment.
• Communicate status, risks, and tradeoffs clearly to executive leadership and cross-functional stakeholders.
•  Director scope: own multi-team delivery, long-term roadmap planning, hiring strategy, and cross-org alignment across multiple product lines.

Firmware Domains Under Management

Teams under this role may span one or more of the following areas:

• PCIe Firmware: PCIe switch and controller firmware (Gen3+), including link training, enumeration, error handling, and performance optimization.
• Ethernet Firmware: Embedded firmware for high-speed Ethernet systems (100G–400G+), including PHY/MAC interaction and link bring-up.
• UCIe / Chiplet Firmware: Firmware for chiplet-based SoC architectures, including die-to-die interconnect initialization and advanced packaging enablement.

Required Experience

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of experience developing or supporting firmware for SoC, silicon, or systems products in compute, networking, or storage domains.
• 5+ years of experience in a people-management role, leading firmware or low-level software teams.
• Strong understanding of bare-metal firmware, RTOS environments, and firmware development lifecycles.
• Experience managing teams working on complex SoCs and high-speed interfaces such as PCIe, Ethernet, DDR, NVMe, or similar.
• Proven ability to lead execution across ambiguous, fast-moving environments with multiple stakeholders.
• Strong communication skills, executive presence, and customer-facing professionalism.
• Authorization to work in the U.S.

Preferred Experience

• Prior experience managing firmware teams delivering PCIe or Ethernet switch products.
• Experience with UCIe, chiplet architectures, or advanced packaging ecosystems.
• Track record of scaling teams through hiring, onboarding, and mentorship.
• Experience working with or supporting customers during bring-up, deployment, or escalations.
• Participation in industry ecosystems such as OCP or OpenBMC.
• Director level: experience owning multi-program delivery, long-term technical roadmaps, and cross-functional organizational planning.

Astera Labs’ firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems.

Job Description

• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance.
• Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic Qualifications 

• Strong academic and technical background in electrical or computer engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Required Experience 

• ≥3 Years experience leading a team in a “lead by example” manner—planning sprints, assigning tasks based on individuals’ strengths and career aspirations, providing constructive/encouraging feedback, maintaining a “dashboard” view of project status, chipping into shore up gaps in execution as needed.
• ≥5 Years hands-on experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Good understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred Experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Familiarity with PCIe compliance standards and the ability to follow and be involved in compliance and standard consortiums.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, clock recovery and SerDes link budgets.
• Experience with PAM4 SerDes is a huge bonus!

Astera Labs is seeking an exceptional Director of System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments. 

Job Description 

• Seeking a strong technical leader who has delivered multiple SoC products. 
• Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs. 
• Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications. 
• Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification. 
• Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence. 
• Ensure timely bringup of new silicon and platforms, driving rootcause analysis and crossfunctional debug of hardware, firmware, and system issues. 
• Deliver high confidence validation results that support product qualification, customer sampling, and mass production readiness. 
• Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions. 
• The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fastmoving, highperformance computing environments. 
• Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies. 
• Drive a culture of technical excellence, accountability, and continuous improvement. 
• Manage resource planning, and vendor/partner relationships. 

Basic Qualifications 

• Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred. 
• ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and highperformance hardware companies. 
• ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems. 
• ≥2 years building high performance Engineering teams and validation methodologies. 
• Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions. 
• Expertise in validation methodologies: presilicon simulation/emulation, postsilicon bringup, system validation, stress testing, and performance characterization. 
• Strong background in debug methodologies, lab infrastructure, and automation frameworks. 
• Excellent communication skills and ability to influence executives and crossfunctional partners. 
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! 

Preferred Experience: 

• ≥5 years leading validation teams planning, execution and maintaining project visibility. 
• ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems. 
• Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet. 
• Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence. 

The base salary range is $200,000 CAD - $250,000 CAD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.

Job Description

• Seeking a strong technical leader who has delivered multiple SoC products.
• Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs.
• Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications.
• Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.
• Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.
• Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.
• Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness.
• Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions.
• The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.
• Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.
• Drive a culture of technical excellence, accountability, and continuous improvement.
• Manage resource planning, and vendor/partner relationships.

Basic Qualifications

• Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred.
• ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.
• ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• ≥5 years building high performance Engineering teams and validation methodologies.
• Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.
• Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.
• Strong background in debug methodologies, lab infrastructure, and automation frameworks.
• Excellent communication skills and ability to influence executives and cross‑functional partners.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Preferred Experience

• ≥8 years leading validation teams planning, execution and maintaining project visibility.
• ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.
• Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.

The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

Role Overview 

Astera Labs is seeking System Validation Engineers across multiple levels to lead post‑silicon bring‑up and system validation for high‑performance PCIe and CXL memory expansion products used in AI and cloud data centers. You will design and execute validation plans, automate data‑centric test flows, drive root‑cause investigations across silicon, firmware, hardware, and systems, and work directly with customers to validate real world performance and interoperability. 

This role is based in our Vancouver office, which is a strategic growth hub for Astera Labs' validation team. You'll have the opportunity to be a foundational member of this expanding site while collaborating closely with our core team in San Jose. This is a unique chance to help shape the team's culture, processes, and technical direction as we scale our validation capabilities to meet surging demand for AI infrastructure connectivity. 

What Success Looks Like: 

• New silicon and platforms brought up on schedule with reproducible validation results 
• Automated test suites that reduce manual effort and provide clear pass/fail and performance metrics 
• Rapid, data-backed root-cause resolution of system issues and strong customer satisfaction during integration 

Key Responsibilities 

• Validation Planning & Strategy 
• Create comprehensive validation plans for AI fabric switch products covering functionality, performance, reliability, and interoperability 
• Contribute to compliance testing strategies and adapt consortium test cases for execution from x86 and ARM platforms 
• Produce clear, data-driven validation reports and status updates for internal stakeholders and customers 
• Silicon & System Bring-Up 
• Lead silicon and platform bring-up activities, verify boot and runtime behavior on x86 and ARM systems 
• Ensure timely readiness for customer engagements and product launches 
• Debug complex issues across PCIe, CXL, NVMe, Ethernet, firmware, and hardware layers using protocol analyzers, logic analyzers, and CPU-based tool suites 
• Test Automation & Infrastructure 
• Develop robust, repeatable automation for IC and board testing with emphasis on execution efficiency, data collection, analysis, and automated reporting 
• Design experiments to root-cause unexpected behavior and report results and specification compliance in an automated fashion 
• Customer & Cross-Functional Collaboration 
• Collaborate directly with customers to capture system requirements, reproduce customer scenarios, and demonstrate product capabilities 
• Drive cross-functional root-cause analysis with silicon, firmware, hardware, and system teams and document findings and corrective actions 

Basic Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 
• 2-12+ years of experience supporting or developing complex SoC or silicon products for server, storage, or networking domains (level dependent) 
• Working understanding of x86 and ARM architectures and UEFI/Linux boot sequences 
• Solid grasp of high-speed signaling principles 
• Hands-on experience with high-speed protocols such as PCIe, CXL, NVMe, or Ethernet 
• Proven experience in silicon and system bring-up, validation, and debug in lab and customer environments 
• Strong Python automation skills for bench control, test orchestration, data analysis, and reporting 
• Experience with lab equipment including protocol analyzers, logic analyzers, in-circuit debuggers, and CPU-based tool suites 
• Strong prioritization, planning, and independent execution skills with a customer-focused mindset 

Preferred Qualifications 

• Master's degree in Electrical Engineering, Computer Engineering, or related field 
• Working knowledge of C or C++ for embedded firmware and device drivers 
• Familiarity with PCIe compliance standards and experience adapting consortium tests for platform execution 
• Advanced understanding of memory architectures, high-speed signaling, and system boot flows 
• Track record of influencing cross-functional teams and navigating complex matrixed organizations 
• Entrepreneurial, can-do attitude with ability to think and act with the customer in mind 

The base salary range for this role is $125,000 - $290,000 CAD depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

The Role and Its Impact 

Our analog connectivity product portfolio includes sophisticated mixed-signal components that form the critical signal conditioning path in both optical modules and copper interconnects: transimpedance amplifiers, transmit drivers, continuous-time linear equalizers, and integrated analog subsystems. The firmware you develop will directly control the adaptive behavior, calibration sequences, and real-time performance optimization of these analog circuits deployed in data centers worldwide.  

As a Principal Engineer in our Signal Connectivity Engineering group, you'll shape firmware architectures that directly impact the performance and reliability of connectivity solutions powering AI infrastructure globally. You'll take end-to-end ownership of the software lifecycle, from pre-silicon planning through production deployment and field support. You will bridge the gap between sophisticated analog circuit design and the software intelligence required to make these circuits adaptive and robust. Working at the intersection of embedded systems and analog control, you'll collaborate closely with mixed-signal designers, systems architects, silicon validation engineers, and customer teams while building and leading a technical team in a high-growth company. 

We're a startup, and this role reflects that reality. You'll have responsibilities spanning firmware architecture, team building, CI/CD infrastructure, customer engagement, and lab automation. We're looking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. 

This position offers an opportunity to build and lead a team from the ground up. You'll help hire two engineers and will play an active role in recruiting as the team grows. Depending on your preferences, you can either manage these engineers directly from day one, or mentor them while remaining in a technical lead capacity, either path is fully supported. 

Level is negotiable based on experience and qualifications. 

Location & Travel 

This is a remote position, but candidates must be located and authorized to work in the Ottawa area. Occasional travel to our San Jose headquarters will be required, approximately twice per year for chip bring-ups and project coordination. 

Core Responsibilities 

Software Ownership & Architecture 

• Own the complete firmware stack for analog connectivity products, from low-level hardware abstraction through customer-facing APIs 
• Design and implement embedded firmware that controls complex analog subsystems including adaptive equalization, gain control, PLL/CDR feedback loops, and thermal management 
• Architect calibration algorithms, state machines, and control flow for managing analog tuning parameters across process, voltage, and temperature variation 
• Establish software quality gates and validation criteria at each development phase 

Technical Leadership & Team Building 

• Help recruit and hire two engineers to join your team, with ongoing involvement in recruiting as the team expands 
• Lead your team, whether through direct management or technical mentorship, through design, implementation, code review, and debugging activities 
• Lead architecture discussions and technical tradeoff decisions; balance performance, code size, maintainability, and time-to-market 
• Serve as the go-to technical expert for mixed-signal firmware and analog control loop behavior 
• Drive difficult debug sessions in the lab and through remote customer support, coordinating across silicon design, systems, and applications teams 

Cross-Functional Collaboration 

• Partner with analog circuit designers to understand hardware behavior, tuning requirements, and failure modes 
• Collaborate with product applications to translate customer requirements into firmware features and APIs 
• Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases 
• Coordinate with field applications engineers to support customer integration and resolve deployment issues 
• Provide regular project updates on progress, risks, dependencies, and technical challenges 

What You Bring 

Required Qualifications: 

• BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field 
• 10+ years of embedded C/C++ firmware development in resource-constrained environments 
• Proven track record as a Technical Lead or Team Lead on embedded projects from architecture through production 
• Deep understanding of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware design 
• Solid experience with analog control loops: PID controllers, feedback systems, adaptive algorithms, and tuning methodologies 
• Strong proficiency with Linux development tools: gcc/clang, make, bash scripting, gdb, and git 
• Excellent verbal and written communication skills; ability to explain complex technical concepts clearly 
• Demonstrated problem-solving ability and systematic debugging approach on real hardware 
• Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment 

Highly Valued Skills: 

• Experience with Python for test automation, data analysis, or general scripting 
• Hands-on experience building and maintaining Jenkins CI/CD pipelines and automated test infrastructure 
• Familiarity with mixed-signal systems: ADC/DAC interfaces, sensor readout, analog signal conditioning, calibration techniques 
• Knowledge of transimpedance amplifiers, transmit drivers, equalizers (CTLE/DFE), CDR/PLL circuits, or related analog signal path components 
• Background in optical module firmware, pluggable optics/AEC standards (MSA/CMIS), retimer or gearbox firmware/API, or high-speed copper connectivity 
• Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, Viavi/Lecroy/Exfo/Keysight/Tektronix/etc. 
• Exposure to SERDES, Ethernet PHYs, layer 1 devices, or PCIe physical layer implementations 
• Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin 
• Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments 
• Experience with RTOS, device drivers, coroutines 
• Prior people management, mentorship, or recruiting experience 

Compensation 

Salary range is CAD $184,500 to $205,000 depending on experience, level, and business need. This role will include a discretionary bonus, extremely competitive equity package, comprehensive health/dental/vision coverage, professional development opportunities, and a culture that values technical excellence, collaboration, and innovation. 

Job Description

The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• Minimum 8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).
• Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience developing embedded firmware for PCIe products.
• MQX RTOS or ThreadX Development or enablement.
• High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
• High level of proficiency in Python for automating pre-processors/post-processors and FW QC.
• Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.
• Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).
• Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces
• Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc

Preferred Experience

• Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC)
• Experience with industry forums and collaboration workgroups such as OCP and OpenBMC

The base salary range is $203,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Title: Lead Firmware QA Engineer, Astera Labs, Bengaluru, India. 
 
Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning.

Basic Qualifications:

• Bachelor’s degree in electrical engineering (EE) or Computer Science is required; a master’s or PhD in EE is preferred with minimum 4 years of experience.

Required Experience:

• Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol.
• Estimate work, identify dependencies and develop schedules.
• Responsible for designing and executing functional, performance, interoperability and stress tests.
• Work closely with  Silicon team, architecture team, FW development team to understand the design and develop test strategies.
• Responsible for manual and automation testing.
• Strong knowledge of scripting ( Python ) is must.
• Responsible for automation development and manual testing.
• Perform Signal integrity and protocol level validation.
• Closely work with development teams to triage and debug issues.
• Knowledge of collecting PCIe trace using PCIe analyzer and analyzing the trace to triage issues.
• Experience in PRBS testing, loopback and margining tests.
• Good understanding of OOB testing and Protocols like MCTP, I2C, SPDM etc.
• Experience is PCIe compliance testing is a plus.
• Regularly working with Hyperscale's and Tier 1 OEMs to communicate plans and status, address escalations, deliver on SLAs.
• Knowledge in validation of NIC controllers and storage controllers is preferred.
• Requirements management and traceability through software development phases.
• Mentoring and coaching team members to help them excel in their jobs.
• Power user of Git, Jira and Confluence.

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion.
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic qualifications 

• Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Required experience 

• Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget. Experience with PAM4 SerDes is a huge bonus!
• Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
• Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.

The base salary range is $205,000.00 USD – $255,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

The Role and Its Impact 

Our Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications, providing critical signal conditioning for high-speed connectivity in AI infrastructure. The firmware you develop will manage complex system and IP integration, SERDES configuration, link training sequences, and diagnostic capabilities for these devices deployed in data centers worldwide. 

As a Principal Engineer in our Signal Connectivity Engineering group, you'll contribute to firmware that directly impacts the performance and reliability of Ethernet connectivity solutions powering AI infrastructure globally. Working closely with the SoC software, transceiver module software, and system validation teams, you'll take ownership of feature development and rollout, software integration testing, and customer debug activities. Working at the intersection of embedded systems and high-speed Ethernet connectivity, you'll collaborate closely to bring these systems to production. 

We're a startup, and this role reflects that reality. You'll have responsibilities spanning firmware development, customer engagement, debug and validation support, and cross-functional coordination. We're looking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. 

This position offers strong mentorship opportunities as you work alongside experienced engineers and help bring products from development through customer deployment. 

Level is negotiable based on experience and qualifications. 

Location 

This is an on-site position based in our San Jose, CA office. 

Core Responsibilities 

Firmware Development & Debug 

• Develop and maintain embedded firmware for Ethernet retimers and gearboxes, from low-level hardware abstraction through customer-facing APIs 
• Drive Layer 1 PHY and SERDES debug activities, including link bring-up issues, signal integrity problems, and interoperability failures 
• Support complex IP integration efforts across multiple subsystems within the SoC 
• Implement and optimize link training sequences, equalization tuning, and diagnostic features 
• Assist with software quality gates and validation criteria at each development phase 

Product Rollout & Customer Integration 

• Partner with the software lead to drive product rollout activities from development through production deployment 
• Support customer integration efforts through firmware customization, debug assistance, and technical guidance 
• Investigate field-reported issues and coordinate resolution with internal teams 
• Develop and maintain SDK/API interfaces that enable customer platform integration 

Cross-Functional Collaboration 

• Work extensively with digital SoC teams to understand hardware behavior, register interfaces, and IP integration requirements 
• Collaborate with field applications engineers to support customer bring-up and resolve deployment issues 
• Partner with platform applications teams to ensure firmware meets system-level requirements 
• Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases 
• Provide regular project updates on progress, risks, dependencies, and technical challenges 

What You Bring 

Required Qualifications: 

• BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field 
• 10+ years of embedded C/C++ firmware development in resource-constrained environments 
• Deep understanding of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware design 
• Experience with Layer 1 PHY firmware, SERDES bring-up, or SDK/API development for networking devices 
• Strong proficiency with Linux development tools: gcc/clang, make, bash scripting, gdb, and git 
• Excellent verbal and written communication skills; ability to explain complex technical concepts clearly 
• Demonstrated problem-solving ability and systematic debugging approach on real hardware 
• Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment 

Highly Valued Skills: 

• Experience with PMA, FEC, or related PHY-layer subsystems beyond the PMD/SERDES 
• Familiarity with NIC or switch management software, for system test purposes 
• Exposure to SAI (Switch Abstraction Interface) or OpenBMC 
• Experience with Python for test automation, data analysis, or general scripting 
• Hands-on experience building and maintaining Jenkins CI/CD pipelines and automated test infrastructure 
• Background in retimer or gearbox firmware/API, active electrical cables, or high-speed Ethernet connectivity 
• Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, BERT, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar 
• Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin 
• Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments 
• Experience with RTOS, device drivers, or coroutines 
• Prior technical lead, mentorship, or team lead experience 

Compensation 

Salary range is $185,000 USD - $203,000 USD depending on experience, level, and business need. This role will include a discretionary bonus, competitive equity package, comprehensive health/dental/vision coverage, professional development opportunities, and a culture that values technical excellence, collaboration, and innovation.

Job Description

Astera labs is seeking a skilled and motivated Data Scientist. This individual will play a pivotal role in identifying key data points for collection, developing strategies to accumulate data and deriving actionable insights an anomaly based on a solid foundation of relevant know-how. Also, will also be responsible for creating, testing, and deploying scripts and methods for data collection and analysis to support decision-making. The Engineer will collaborate with cross-functional teams to identify critical data sources to determine the most effective data collection strategies, will develop automated and scalable data collection pipelines, will ensure data quality, integrity, and consistency across all sources and may use AI techniques to refine the results toward failures predictions.

Basic Qualifications

• Bachelor’s degree in computer science, Data Science, Engineering, Mathematics, or a related field.
• Advanced degrees in data science or Machine learning / AI - Advance.
• Proficiency in programming languages such as Python, R, or MATLAB.
• Strong understanding of data manipulation and analysis tools (e.g., Pandas, NumPy, SQL).
• Understanding of high speed interfaces such as Ethernet, PCI-E , WiFi.
• Experience with data visualization tools such as Tableau, Matplotlib, Graphana.
• Strong analytical and critical-thinking skills to identify patterns and outliers.
• Customer-obsession, Think and act with the customer in mind!
• Goal-driven, Self-motivated, be able to work independently and with teams with people around the globe.
• Entrepreneurial, open-minded behavior and can-do attitude.

Required Experience

• Experience with data manipulation and analysis tools (e.g., Pandas, NumPy, SQL).
• Machine learning and AI techniques and frameworks (e.g., TensorFlow, Scikit-learn).
• Proven ability to manage multiple tasks and meet deadlines.

Preferred Experience

• Embedded Firmware development with C-language, scripting with Python or other equivalent programming languages.
• Master’s degree in a relevant field.
• Experience with cloud platforms (e.g., AWS, Azure, GCP) for data storage and processing.
• Familiarity with big data technologies (e.g., Hadoop, Spark).
• Knowledge of engineering design tools and processes.

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Education and Experience Requirements

• Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 8-12 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Desired Qualifications

• Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
• Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
• Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
• Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
• Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
• Experience with PAM4 SerDes validation (200G/100G/50G)
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
• Knowledge of Signal Integrity simulation tools
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!