As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

Job Title: Director of Design Verification

Overview

We are seeking a seasoned Director of Design Verification with 15+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domains.

Key Responsibilities

• Own and drive the end-to-end verification methodology for a specific product line.
• Lead, mentor, and grow a team of engineers, fostering technical excellence and innovation.
• Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.
• Champion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficiency.
• Collaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.
• Represent verification in executive reviews, customer engagements, and industry forums.
• Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
• 15+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
• Deep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification IPs.
• Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
• Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.

Required Experience

• Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).
• Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
• Strong background in writing assertions, cover properties, and analyzing coverage data.
• Experience in developing VIP abstraction layers to simplify and scale verification deployments.

Preferred Experience

• Expertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC.
• Experience with buffering, queuing, and QoS in complex NoC-based SoCs.
• System-level performance analysis on switching fabrics.
• Familiarity with AI-driven verification methodologies and workforce transformation strategies.

Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle. 

As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers. 

Location - San Jose, CA OR Israel 

Key Responsibilities 

• Product Technical Ownership 

• Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement 

• Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met 

• Lead development of large-scale chips (300-400mm²) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures 

• Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths 

• Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality.  

• Cross-Functional Technical Leadership 

• Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest 

• Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria 

• Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies 

• Work closely with physical design teams on timing closure, power optimization, and backend execution 

• Process Excellence & Organizational Development 

• Establish and reinforce scalable processes, documentation, and handoffs that support company growth 

• Provide structured, data-driven decision-making and maintain a crisp operational cadence across the product line 

• Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration 

• Model steady, calm leadership, particularly in high-stakes or ambiguous situations 

• Shape engineering culture and talent strategy to support Astera's rapid growth trajectory 

Basic Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 

• 15+ years of experience across architecture, silicon design, validation, systems, or related domains 

• Proven track record of developing large-scale chips (300mm²+) through successful tapeout 

• Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures 

• Strong understanding of RTL design, design verification, DFT, and physical design flows 

• Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures 

• Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership 

• Strong communication and executive presence with the ability to influence at all levels of the organization 

Preferred Qualifications 

• Master's degree in Electrical Engineering or Computer Engineering 

• Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures 

• Experience with advanced process nodes (7nm, 5nm, or below) 

• Background in power management, clocking architectures, or high-speed analog integration 

• Experience operating in fast-growing startups or hyper-scale environments 

Key Leadership Competencies 

• Systems Thinking: See the big picture while managing details 

• Emotional Intelligence: Calm under pressure, empathetic, and influential 

• Adaptability: Thrive in ambiguity and fast-changing environments 

• Execution Discipline: Deliver predictable results without sacrificing innovation 

Overview

Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
• Work closely with post-silicon teams to facilitate silicon bring-up and debug.
• Mentor junior engineers to develop their technical skills and expertise.
• Actively contribute to the development and improvement of silicon development processes.
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success.

Required Qualifications:

Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Architecture definition and micro-architecture development
• RTL coding, functional simulation, and synthesis
• Timing closure and gate-level simulation (GLS)
• Design for test (DFT) implementation
• Production experience with advanced CMOS nodes (≤7nm)

Protocols & Integration:

• Deep expertise in at least one high-speed protocol—PCIe , Ethernet, Infiniband, DDR, or similar
• Third-party IP integration and verification.
• Block-level design ownership from architecture through GDS

Tools & Methodologies:

• Proficiency with Cadence and/or Synopsys digital design flows
• Familiarity with UVM-based verification methodologies.
• Silicon bring-up, debug, and failure analysis expertise

Professional Attributes:

• Strong work ethic with the ability to balance multiple priorities in a dynamic environment
• Excellent communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements
• Customer-focused mindset with ability to translate business needs into technical excellence

Preferred Qualifications

• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality

Role Summary
We are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose.

Responsibilities — What You Will Own

1) Chief of Staff to Head of Engineering

•    Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs. 
•    Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate. 
•    Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes.
•    Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions.
•    Support org design, headcount planning, and hiring prioritization for engineering teams.
•    Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes
•    Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety.
•    Support the head of engineering with administrative and org related activities

2) Lead ASIC Tape out Management  (Silicon Programs)

•    Status management — collect and track status across functions contributing to ASIC tapeouts.
•    Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence.
•    IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops.
•    Quality & documentation — monitor quality KPIs, ensure engineering documentation completeness.
•    Requirements tracking — ensure PRDs/features are captured, tracked, baselined.
•    Resource monitoring — track compute, hardware, storage consumption and thresholds.
•    Internal reporting — generate status reporting for Silicon Engineering leadership.

3) Influence Without Authority

•    Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy.
•    Create order in ambiguous spaces; shape scope where it is undefined.

Qualifications

•    10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).
•    Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role.  
•    Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.
•    Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).
•    Proven ability to organize complex workflows and drive consistent follow-through.
•    High EQ and organizational awareness; can navigate tension and align diverse viewpoints. 
•    Exceptional written/verbal communication, structured thinking, and execution discipline.
•    Prior experience in leading RTL2GDSII chip design is a huge plus.

What Success Looks Like

•    Engineering leadership spends more time on strategic and technical decisions, less on coordination.
•    Milestones hit with fewer escalations and clearer accountability.
•    Status, risks, and decisions are crisp — never ad hoc or late.
•    Teams feel supported, not policed — trust increases, friction decreases without compromising on accountability  .
•    Ambiguity decreases over time as clarity and execution rhythm scale with the org.

Salary range is $216,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

• Emulation Flow Execution & Implementation

  • Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
  • Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
  • Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market

• System-Level Debug & Validation

  • Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
  • Ensure rapid cycles from RTL to functional stability through systematic debug approaches
  • Own technical blocks and drive them to completion independently

• Cross-Functional Collaboration

  • Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
  • Ensure seamless hardware-software integration for AI infrastructure connectivity
  • Collaborate with Design and Verification teams to optimize emulation strategies

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• 3+ years of hands-on experience in Emulation at semiconductor companies
• Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce)
• Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs
• Experience developing and maintaining execution flows for building, running, and debugging emulation models
• "Can-do" approach with ability to own technical blocks and drive them to completion independently

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related field
• Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis
• Proficiency in scripting languages such as Python or TCL for automation and flow enhancement
• Experience with standard debug environments (e.g., Verdi)
• Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink)
• Background in hardware-software co-verification methodologies

Job Description:

We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic Qualifications:

• Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)
• Experience in working with PCIe Gen3 and above
• Have gone through at least one cycle of full product development life cycle
• Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred
• Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
• Digital and analog circuit level understanding for DUT.
• Excellent team player with great communication skills
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required Experience:

• Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions
• Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.
• Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs
• Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions
• Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred Experience:

• Working with silicon validation teams to ensure device performance meets production requirements.
• Firmware development in C/C++, scripting in Python, or other equivalent programming experience.
• Hands on experience in product/package qualification

Role Overview

Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions—from early architecture definition through production ramp—enabling the next generation of AI infrastructure and connectivity products.

As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers.

This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.

Key Responsibilities

• Team Leadership & Execution
  • Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows
  • Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs
  • Lead design reviews, audits, and issue resolution through bring-up and production ramp

• Package Design Delivery
  • Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production
  • Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements
  • Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery

• Cross-Functional Collaboration
  • Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges
  • Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps
  • Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms

• Methodology & Automation
  • Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Materials Science, or related field
• 10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP
• 5+ years of leadership experience managing teams or technical organizations in IC packaging environments
• Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool
• Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)
• Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals
• Proven experience working with OSATs and substrate vendors through development and production ramp
• Experience working with OSATs and substrate vendors through development and production ramp
• Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration
• Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization
• Background in early package feasibility, platform evaluation, and technology roadmap development
• Familiarity with chip floor planning, architecture, and system-level tradeoffs
• Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations

The base salary range is $230,000 USD – $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees' pay in similar positions.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Subsystem (Multiple IP’s/Partitions) Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. 

As the Physical Design Subsystem (Multiple IP’s/Partitions) Lead you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SubSystem with your team for chips that drive the world’s largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. 

Key Responsibilities

• Build and mentor a high-performing Partitions team , owning the end-to-end execution from Synthesis to Signoff 
• Take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff 
• Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) 
• Lead and guide external contractors and global partners to ensure seamless execution and delivery 
• Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon 

Basic Qualifications

• B.Sc. or M.Sc. in Electrical Engineering 
• 15+ years of hands-on experience in Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) 
• Proven experience in leading teams or projects with a "can-do" approach and excellent communication skills 
• Deep expertise in RTL2GDS flows, including P&R, STA, Physical verification (DRC/LVS), Formal verification, low-power implementation (UPF/CPF), EMIR and evaluating foundry process nodes and third-party IPs 
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) 
• Experience managing both complex Macro-level designs subsystem level and Full-Chip integration 
   

Preferred Experience

• Deep understanding of Power & Noise analysis (EM/IR) 
• Experience with DFT (Design for Test) integration 
• Background in high-speed interfaces or data center protocols 

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won’t just execute tasks; you will define the Formal verification strategy for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities

• Own and develop formal verification environments from scratch through to sign-off
• Apply formal verification methodologies and strategies to prove the correctness of intricate designs
• Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
• Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
• Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
• Architect and develop generic, common formal functions and properties to be reused across multiple projects

Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in Formal Verification within semiconductor companies
• Deep expertise in formal verification methodologies, tools, and flows
• Strong understanding of RTL design and verification principles
• Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)
• Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving

Preferred Qualifications

• Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle
• Experience with SystemVerilog UVM-based design verification
• Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe)
• Background in high-speed serial interface verification

Overview: 

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Description:

We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic Qualifications:

• Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)
• Experience in working with RF testing and characterization
• Knowledge of spectrum analyzers, vector network analyzers (VNA), and other RF test equipment
• Have gone through at least one cycle of full product development life cycle
• Strong academic/technical background in electrical or computer engineering; bachelor’s is required; MS preferred
• Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
• Digital and analog circuit level understanding for DUT.
• Excellent team player with great communication skills
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required Experience:

• Detail-oriented monitoring of device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs
• Experience with RF calibration techniques and de-embedding methodologies
• Experience with RF parameter measurements including S-parameters, insertion loss, return loss, and signal integrity analysis
• Hands-on work with Advantest 93k ATE platform (SmartScale/ExaScale) including test program updates for wafer sort and final test solutions
• Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions
• Energetic work mindset to meet the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred Experience:

• Hands-on product/package qualification
• Partnering with Fabs on process development and yield improvement initiatives
• Collaboration with silicon validation teams to ensure device performance meets production requirements
• Firmware development in C/C++, scripting in Python, or other equivalent programming languages

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description

We are looking for Senior SoC Verification/Validation Engineer who are passionate about bringing next-generation SoCs to life on industry-leading emulation platforms. You will play a critical role in validating complex SoCs for AI connectivity and cloud infrastructure, ensuring functionality and performance well before silicon tape-out.

Basic Responsibilities

• Play a key role in developing complex SOCs for AI connectivity and cloud infrastructures 
• Bring up and validate high-speed serial interfaces such as PCIe, Ethernet and UALink, and overall SoC functionality 
• Collaborate closely with Architecture, Design, Verification, and SW/FW teams to define and execute functional/performance validation plans
• Develop C/C++ FW and tests to validate and execute all test plan items 
• Build tools and methodologies to validate and debug all HW and SW/FW issues on the emulation platform

Required Qualification

• BS/MS in Electrical Engineering, Computer Engineering or related field.
• 5+ years of hands-on experience in pre-silicon verification/validation.
• Strong hands-on experience in running and debugging SOC simulation.
• Protocol knowledge in high-speed protocols such as PCIe, UALink and/or Ethernet is essential
• Proficiency in programming and scripting languages (System Verilog, C/C++, Python) 
• Strong debugging and analytical skills
• Excellent communication skills and ability to work independently with minimal supervision.
• Currently based locally or open to relocation.

Preferred Experience: 

• Bring up and validation experience using the industry standard emulation platforms (Palladium or Zebu) 
• Hands-on experience in running and debugging SOC simulation and emulation platforms.

The base salary range is $165,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

Job Description:

As an Astera Labs HVM Product and Test Engineering, you will support existing products already in HVM (high volume manufacturing) at our Asia OSAT partners. Maintaining smooth manufacturing to ensure on-time customer shipments is one key objective. In this role, you will complement the New Product Introduction Product Engineers as products are released into production and own the engineering manufacturing during mass production. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic qualifications:

· Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)

· Experience in working with PCIe Gen3 and above

· Have gone through at least one cycle of full product development life cycle

· Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred

· Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.

· Digital and analog circuit level understanding for DUT.

· Excellent team player with great communication skills

· Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required experience:

· Proven track record continuing seamless production of semiconductor products partnering with OSATs supporting high volume manufacturing through the complete product lifecycle

· Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions

· Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.

· Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs

· Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions

· Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred experience:

· Working with silicon validation teams to ensure device performance meets production requirements.

· Firmware development in C/C++, scripting in Python, or other equivalent programming experience.

· Hands on experience in product/package qualification

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

• Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs
• Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners
• Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy
• Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids
• Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs
• Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA
• Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)

Basic Qualifications

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in Physical Design CAD or Physical Verification with a heavy focus on parasitic extraction
• Expert proficiency with industry-standard extraction tools such as Synopsys StarRC, Cadence Quantus (QRC), or Siemens Calibre xACT
• Strong scripting skills in Tcl and Python for flow automation and database manipulation
• Deep understanding of semiconductor physics, interconnect modeling, and the impact of parasitics on timing, EM (Electromigration), and IR drop
• Proven experience in validating tech files and running extraction for complex, multi-million gate designs

Preferred Experience

• Hands-on experience with 5nm, 3nm, or more advanced process nodes, including FinFET-specific extraction challenges
• Familiarity with 3D field solvers and their use in benchmarking standard extraction engines
• Knowledge of Netlist formats (SPEF, DSPF) and their integration into STA and Spice simulation flows
• Experience with compute farm management (LSF/Slurm) and version control (Git)

Role Overview

Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

Job Description

We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
• Familiar with high-speed load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with using Advantest 93k ATE platform.
• Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.
• Experience in running External loopback at wafer sort.
• Familiarity with modern databases

Job Description:

As a Manager of Package Signal & Power Integrity (SIPI) at Astera Labs, you will lead and scale the SIPI engineering function responsible for developing high-performance IC packaging solutions that enable next-generation connectivity products. You will define technical strategy, build and mentor a high-performing team, and drive cross-functional execution from early definition through production. You will partner closely with silicon architecture, package design, PCB board team, hardware validation, manufacturing, and external suppliers (substrate vendors and OSATs) to ensure first-pass success while meeting electrical, cost, schedule, and production goals. You will also drive SIPI methodology evolution, modeling standards, and co-design frameworks across the chip–package–board ecosystem to enable scalable execution across multiple product lines.

Key Responsibilities

• Define and drive the company’s package SIPI strategy across multiple product generations. Ensure robust electrical performance for high-speed interfaces such as PCIe, CXL, Ethernet, and other SerDes protocols (200G/400G+).
• Lead packaging decisions impacting signal integrity, power delivery network (PDN) performance, and substrate design, including selecting packaging platforms, defining substrate stack-up, bump planning, and package architecture to meet high-speed and power integrity requirements.
• Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule.
• Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria.
• Build, mentor, and scale a high-performing SIPI engineering organization, establishing clear priorities, accountability, and technical excellence across concurrent programs while driving talent development and resource planning.
• Represent SIPI leadership in executive reviews and major program milestones, clearly communicating technical strategy, risks, tradeoffs, and execution status to senior leadership and cross-functional stakeholders.

Required qualifications:

• 10+ years of progressive experience in Signal and Power Integrity (SIPI) modeling, analysis, and optimization across the chip–package–board system.
• Demonstrated experience leading teams or technical organizations in IC packaging environments.
• Strong ability to translate business objectives into technical roadmaps and execution plans.
• Deep expertise in EM extraction and modeling tools (e.g., ANSYS HFSS, SIwave, 3DLayout, Keysight ADS, etc.).
• Proven track record delivering high-performance packages such as FCBGA, FCCSP, coreless substrate, chiplet-based, and 2.5D architectures.
• Experience supporting high-speed connectivity products (PCIe, Ethernet, or equivalent SerDes technologies).
• Extensive experience in high-speed S-parameter extraction and system-level SI/PI modeling.
• Expert-level knowledge of PDN design including DC IR drop, loop inductance, target impedance, AC transient behavior, and chip-package-model (CPM).
• Experience driving chip–package–board co-design and system-level validation (eye diagram, ERL, transient response, power-aware SI).
• Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope).
• Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability.
• Experience leading vendor engagements and managing technical execution through production ramp.

Preferred Qualifications:

• Exposure to system-level performance considerations such as skew optimization, channel budget allocation strategy, or power delivery tradeoffs at the package level.
• Background in early package platform evaluation, technology benchmarking, and roadmap trade studies for next-generation connectivity or AI infrastructure products.
• Experience implementing modeling automation, workflow optimization, or data-driven design review processes to improve team scalability and execution efficiency.
• Experience with advanced packaging architectures including chiplet-based designs, 2.5D/3D integration, silicon interposer, bridge-based interconnect (e.g., EMIB-style), and heterogeneous integration platforms.
• Familiarity with UCIe-based die-to-die interconnect integration and associated SI/PI challenges at the package and substrate level.

This position can be hired as a Manager Level or Director Level. The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Design Ownership & Implementation

  • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
  • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
  • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

• Quality Assurance & Design Optimization

  • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
  • Apply design techniques to meet PPA (Power, Performance, Area) targets
  • Contribute to design quality through verification and validation activities

• Methodology Innovation & Collaboration

  • Participate in design methodology improvements and tool automation initiatives
  • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
  • Collaborate effectively across teams to ensure seamless integration

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of experience in logic design at semiconductor companies
• Knowledge and experience in Verilog and/or SystemVerilog
• Excellent communication skills with ability to work effectively across teams
• Understanding of digital design principles and RTL coding best practices

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Knowledge of DDR and PCIe protocols and implementation
• Understanding of power management techniques for low-power design
• Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis
• Proficiency in scripting languages such as Python or Perl
• Experience with high-speed serial interface designs or connectivity protocols

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. 
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments. 

Key Responsibilities

• Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing 
• Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration) 
• Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices 
• Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints 
• Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance 
• Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets 
• Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp 
• Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews 

Basic Qualifications

• 10+ years of hands-on IC BIG package design experience for high-performance semiconductor products, with full ownership from concept through tape-out 
• Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and experience designing complex packages (BGA, FCBGA, FCCSP) 
• Strong package architecture & integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership 
• Deep understanding of signal, power, and thermal integrity at the package level, with ability to drive design tradeoffs based on analysis 
• Proven manufacturing and release experience, including DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs 

Preferred Qualifications

• Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces 
• Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.) 
• Experience supporting chiplet-based architectures and heterogeneous integration 
• Prior technical leadership or package ownership on high-volume products 

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Design Verification Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - it’s an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.

Key Responsibilities

• Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
• Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
• Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
• Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
• Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent

Basic Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Ability to work at least 2 days a week at our Haifa/Tel Aviv center
• Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)
• Basic familiarity with Verilog or SystemVerilog from academic projects or lab work
• A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail
• Fluent in Hebrew and English with the ability to work effectively in a team environment

Preferred Qualifications

• Completed courses in VLSI, Digital Systems, or Computer Architecture
• Proficiency in Python, Perl, or Tcl
• Any prior exposure to UVM/OVM or constrained-random verification is a major plus
• Basic understanding of protocols like PCIe, Ethernet, or DDR

About Astera Labs

Astera Labs is a rapidly growing semiconductor company redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions—built on PCIe®, CXL™, Ethernet, and custom fabrics—enable seamless data movement across compute, memory, and storage. As part of our team, you'll help validate the silicon that powers the world's most advanced AI platforms.

Role Overview

As an Entry-Level System Validation Engineer on the Taurus team, you will validate Astera Labs' Taurus Ethernet Smart Cable Modules and Taurus ASICs. You'll work on chip bring-up, system-level debug, and interoperability testing across real-world AI server and networking platforms, collaborating closely with electrical validation, firmware, and product applications teams.

Key Responsibilities

• Execute system validation test plans for Taurus Ethernet Smart Cable Modules.
• Perform chip bring-up and debug for Taurus ASICs in lab environments using oscilloscopes, protocol analyzers, BERTs, and network switches
• Validate high-speed interconnects and AI fabrics in custom silicon, including signal integrity, link training, FEC stats, and protocol compliance
• Collaborate with electrical validation, firmware, and product applications teams to root-cause issues and drive resolution
• Document validation results, debug findings, and contribute to bring-up notes and test reports

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• Strong academic foundation in circuit analysis, signals and systems, electromagnetics, or high‑speed digital design through coursework and labs
• Familiarity with PCIe®, CXL™, or Ethernet standards
• Familiarity with fundamental signal‑integrity concepts such as eye diagrams, jitter, noise, impedance, and transmission lines
• Exposure to electrical lab equipment (e.g., oscilloscopes, logic analyzers, network analyzers)
• Experience using scripting or programming languages such as Python, MATLAB, TCL, or C/C++
• Comfortable working with lab tools and debugging hardware
• Strong analytical and communication skills

Preferred Skills

• Exposure to post-silicon validation or bring-up of connectivity IP blocks
• Knowledge of signal integrity analysis and eye diagram interpretation
• Familiarity with Linux systems, shell scripting, and version control (Git)
• Understanding of AI workloads and how interconnect bandwidth impacts performance

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won’t just be using tools; you’ll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.

Key Responsibilities

• Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
• Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
• Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
• Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows

Basic Qualifications

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on professional experience in relevant industries 
• Proven experience in Python and Tcl within a Linux/Unix environment
• Knowledge and experience in Verilog and/or System Verilog
• Very good communication skills

Preferred Experience

• Strong understanding of the VLSI design cycle, familiarity with clock domain crossing, simulation, debugging, synthesis and timing analysis
• Hands-on experience with industry-standard tools for lint, synthesis, simulation
• Experience with version control systems (Git) and compute cluster management (LSF/SGE)

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. 

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

• Execute SoC Top-level physical design and actively drive full-chip convergence
• Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
• Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
• Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
• Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

Basic Qualifications

• B.Sc. or M.Sc. in Electrical Engineering
• 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
• Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills
• Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
• Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration

Preferred Qualifications

• Deep understanding of Power & Noise analysis (EM/IR)
• Experience with DFT (Design for Test) integration into the physical design flow
• Background in high-speed interfaces or data center protocols

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.

Key Responsibilities

• Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
• Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
• Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
• Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• SystemVerilog/Verilog familiarity.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff Physical STA Expert to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the sign-off methodology for chips that power the world's most advanced AI clusters.

As a Staff Physical STA Expert , you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the world’s most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. 

Key Responsibilities

• Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments 
• Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence 
• Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments 
• Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners 
• Have a passion for better workflows? You’ll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarter 

Basic Qualifications

• B.Sc. in Electrical Engineering or Computer Engineering 
• 8+ years of deep, hands-on experience in Static Timing Analysis (STA) at leading semiconductor companies, specifically working on advanced process technologies 
• Deep expertise in multi-scenario STA, timing/SDC constraint development and verification. You have a "full-chip" perspective, managing both complex macro-level designs and top-level integration 
• Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off 
• Solid knowledge of physical design flows (P&R, Physical Verification) and how they intersect with timing closure 

Preferred Experience

• Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) 
• Proven track record of managing both complex Macro-level designs and Full-Chip timing integration 
• Strong background in scripting and automation to enhance timing closure efficiency 

We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation.  The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues.  The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.

Basic qualifications:

• Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.
• Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required experience:

• Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols.
• High level of proficiency in System Verilog and verification environments.
• Experience understanding software and hardware co-simulation limitations and debug methods.
• Experience in programming and scripting languages (like perl/python/C).
• Currently based locally or open to relocation.

Preferred experience:

• Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.
• Experience in modeling for emulation and prototyping, and/or non-UVM environments

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

• Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
• Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
• Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
• Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
• Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

Basic Qualifications

• B.Sc. in Electrical Engineering or Computer Engineering
• 5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting)
• Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels
• Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off
• Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure

Preferred Experience

• Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia)
• Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration
• Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency

As an Astera Labs’ Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs’ connectivity products that support the world’s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams.

Basic qualifications:

• Minimum of bachelor’s degree in computer engineering/ electrical engineering, Masters preferred.
• Minimum 10+ years of experience in a semiconductor company as a DFT engineer
• Must be local or willing to relocate

Required experience:

• Chip design, Verilog and System Verilog
• Verification, UVM methodology
• ATPG tools
• Scan insertion tools
• Gate-level simulations
• Static timing analysis
• Scripting (Perl/Tcl)
• Familiarity with ATE
• Hands-on expertise with commercial test generation tools for large complex designs
• Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression
• Experience running test compression software
• Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools

Preferred experience:

• Experience with defining and implementing SOC level verification on large designs.
• Working with 93k Tester

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Physical Implementation & Execution

  • Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
  • Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
  • Own macro-level implementation with deep hands-on experience in floorplanning and complex routing

• Signoff & Design Integrity

  • Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
  • Ensure first-pass silicon success through rigorous signoff flows and analysis
  • Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness

• Methodology Development & Cross-Functional Collaboration

  • Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
  • Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
  • Leverage scripting and automation to make engineering environment faster and more robust

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of hands-on experience in Physical Design at semiconductor companies
• Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing
• Experience working with advanced process technologies (7nm and below)
• Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis
• Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks

Preferred Qualifications

• Experience with full-chip level implementation and integration
• Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon
• Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout
• Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
• Background in high-speed interface designs or connectivity protocols

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Senior DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Senior DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

• DFT Architecture & Strategy

  • Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
  • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
  • Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies

• Test Pattern Development & Optimization

  • Generate and optimize high-quality test and debug patterns for production
  • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
  • Drive test coverage and quality metrics to meet stringent manufacturing requirements

• Cross-Functional Collaboration & Methodology Innovation

  • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
  • Participate in developing and maintaining cutting-edge DFT implementation flows
  • Automate and improve methodologies using advanced scripting and tools

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of hands-on experience in DFT roles at semiconductor companies
• Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG
• Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent)
• Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA)
• Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements
• Experience in chip bring-up and mass production activities
• Background in advanced process technologies (7nm and below)
• Excellent communication skills with ability to work effectively in global team environments

Overview
Join our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
• Scripting and automation for ASIC methodology improvement.
• Accountable for quality and overall design success with the support of senior engineers.

Required Qualifications
Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent
• 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
• Track record of delivering high quality digital designs from definition to production.
• Experience with functional and formal verification at block and chip level. 
• Understanding of clocking, CDC and RDC
• Experience with CMOS nodes (≤7nm)

Protocols & Integration:

• Familiarity with high-speed protocols—PCIe, Ethernet, DDR, or similar
• Experience with IP development and integration

Tools & Methodologies:

• Proven SystemVerilog and Python expertise in a production environment
• Familiarity with Synopsys and/or Cadence digital design flows
• Basic understanding of UVM-based verification methodologies

Professional Attributes:

• Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment
• Good communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who adapts quickly to changing requirements
• Customer-focused mindset with the ability to prioritize and work independently to deliver high quality designs.

Preferred Qualifications

• Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus
• Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary ASIC Design Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As an ASIC Design Student, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks
• Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient
• Work closely with the verification team to run simulations, analyze results, and ensure design quality
• Interact with Architecture and Backend teams to understand the full chip development lifecycle
• Help leverage AI-based automation tools to optimize engineering workflows

Basic Qualifications

• Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Strong academic record with a focus on Digital Logic Design and VLSI
• Ability to work at least 2 days per week at our Haifa/Tel Aviv center
• Solid understanding of logic design principles and hardware description languages (Verilog or SystemVerilog)
• A "can-do" attitude with a passion for solving complex technical challenges
• Fluent in Hebrew and English with the ability to work effectively in a team environment

Preferred Qualifications

• Hands-on experience with FPGA projects or university-level tape-out projects
• Proficiency in Python, Perl, or Bash for automation
• Completed courses in Computer Architecture, Synthesis, or Static Timing Analysis (STA)
• Basic familiarity with high-speed protocols like PCIe or DDR

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.

Key Responsibilities

• Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
• Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
• Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
• Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
• Own the design database structure and version control to ensure team alignment and data integrity
• Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
• Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

Basic Qualifications

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on professional experience with back-end industrial tool suites (e.g., Synopsys Fusion Compiler or Cadence Genus/Innovus)
• Expert-level proficiency in Tcl and Python for high-level flow automation, data parsing, and tool customization
• Deep technical understanding of Physical Design concepts, including clock tree synthesis (CTS), routing congestion, timing closure, and signal integrity
• Proven experience executing sign-off flows for complex, high-performance designs
• Strong communication skills and a collaborative approach to solving complex engineering bottlenecks

Preferred Experience

• Hands-on experience with 5nm, 3nm, or more advanced process nodes
• Practical knowledge of compute farm management (LSF/Slurm) and revision control (Git) for managing massive design databases
• Experience in developing proprietary automation wrappers for industry-standard EDA tools

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters.

As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments.

Key Responsibilities

• Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
• Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
• Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
• Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
• Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
• Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
• Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
• Support NPI, qualification, and product sustainment activities, including vendor technical reviews

Basic Qualifications

• 5+ years of hands-on IC package design experience for high-performance semiconductor products, with full technical ownership from concept through tape-out
• Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and hands-on experience designing complex packages (BGA, FCBGA, FCCSP)
• Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership
• Deep understanding of signal, power, and thermal integrity at the package level, with the ability to execute design tradeoffs based on analysis
• Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs

Preferred Qualifications

• Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces
• Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)
• Experience supporting chiplet-based architectures and heterogeneous integration
• Demonstrated track record of complete technical package ownership on high-volume products

Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.

Key Responsibilities

• Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
• Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
• Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
• Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
• Work with RTL designers to troubleshoot and resolve design issues.
• Drive verification strategy and methodology for SoCs in server and networking applications.

Required Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred).
• 8+ years of experience in SoC verification, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
• Familiarity with verification of switching architectures, including packet processing and forwarding engines.
• Excellent communication skills and ability to work independently with minimal supervision.

Preferred Qualifications

• Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
• Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
• Knowledge of Ethernet/PCIe switching and central buffer architectures.
• Experience with emulation platforms and hardware-software co-verification

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Role Overview

Join Astera Labs as a Technical Lead Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 5+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $160,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

Role Overview

As a Principal Package Thermal & Mechanical Engineer at Astera Labs, you will serve as a technical leader driving the development and modeling of advanced IC packaging solutions that enable next-generation AI and high-performance connectivity systems.

In this highly visible role, you will define and execute thermal and mechanical modeling strategies across the chip–package–board system, influencing package architecture, material selection, and reliability design. You will partner closely with package design, SIPI, silicon, system, and manufacturing teams to ensure robust thermal/mechanical performance and first-pass success.

You will also drive modeling methodologies, correlation strategies, and best-known methods (BKMs), while engaging directly with customers to translate complex simulation insights into actionable system-level solutions.

Key Responsibilities

• Thermal & Mechanical Modeling Leadership
• Define and drive thermal and mechanical modeling strategies for advanced packages (FCBGA, FCCSP, multi-die, and chiplet-based architectures)
• Perform detailed thermal simulations including steady-state and transient heat transfer (conduction, convection, and interface resistances such as TIM1/TIM2)
• Develop and deploy compact thermal models (CTM), reduced-order models (ROM), and DELPHI-based models for system-level integration
• Analyze power density, hotspot behavior, and package-to-system thermal interactions across air and liquid cooling environments
• Perform thermo-mechanical stress/strain analysis including CTE mismatch, viscoelastic material behavior, and deformation
• Predict package warpage across process and use conditions (reflow, underfill cure, board attach, field operation)
• Model solder joint reliability and fatigue using industry standard models
• Package Architecture & Thermal Design Strategy
• Drive package design decisions including material selection (EMC, substrate, TIM, lid/heat spreader), thermal path optimization, and early-stage architecture definition across air and liquid cooling solutions (air, cold plate, CPO/CPC)
• Conduct DOE, sensitivity studies, and worst-case analysis to guide tradeoffs across performance, cost, reliability, and manufacturability
• System Co-Design & Automation
• Partner cross-functionally to drive chip–package–board co-design and resolve system-level thermal/mechanical challenges, including system integration constraints
• Serve as a technical interface for customers and internal teams, translating modeling results into actionable insights and leading design reviews and issue resolution
• Develop and scale modeling methodologies, workflows, and BKMs; mentor engineers and improve efficiency through automation and scripting (Python, MATLAB)

Basic Qualifications

• M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field
• 8+ years of experience in semiconductor packaging with strong focus on thermal and mechanical modeling
• Deep expertise in thermal modeling and simulation, including steady-state and transient analysis, compact thermal modeling (CTM), DELPHI methodology, and system-level thermal integration using tools such as ANSYS Icepak, Flotherm, or equivalent
• Deep expertise in thermo-mechanical modeling and FEA simulation, including stress/strain analysis, warpage prediction, and reliability modeling (BLR/CLR), using tools such as ANSYS Mechanical, or equivalent
• Proven ability to correlate simulation results with lab measurements
• Experience influencing package design and delivering solutions to production
• Strong cross-functional collaboration across package design, SIPI, system, and manufacturing teams

Preferred Qualifications

• Experience with high-power AI / HPC packages and large FCBGA (>50mm)
• Familiarity with advanced packaging technologies:2.5D / 3D integration, Chiplet, CPO/CPC
• Experience with system-level cooling solutions: Liquid cooling, cold plates, immersion cooling
• Knowledge of JEDEC standards and reliability qualification methodologies
• Experience working with OSATs and substrate vendors on thermal/mechanical design optimization
• Proficiency in scripting (Python, MATLAB) for modeling automation
• Exposure to multi-physics coupling (electrical–thermal–mechanical interactions)

 The base salary range is $185,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.

Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we're revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution.

In this highly strategic role, you'll serve as Astera Labs' technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You'll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers exceptional scope for impact—your work will directly enable the rack-scale AI infrastructure that's transforming cloud computing and enterprise data centers worldwide.

Key Responsibilities

• Strategic Leadership & Methodology Development
• Define and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols
• Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality
• Represent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verification
• Drive cross-functional collaboration to influence technical direction across the organization
• Technical Execution & Innovation
• Develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications
• Identify key logic components and critical micro-architectural properties essential for ensuring design correctness
• Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs
• Apply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth
• Develop and maintain scripts to enhance FV productivity and streamline verification processes
• Team Development & Cross-Functional Partnership
• Mentor Principal and Lead Engineers across global sites in advanced formal verification techniques
• Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels
• Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback
• Prepare and deliver customer meetings and executive presentations with minimal supervision

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
• 15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization
• Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification
• Advanced scripting abilities with Python or Perl for automation and productivity enhancement
• Proven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision
• Strong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus
• Entrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards

Preferred Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification
• Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold
• Experience with both bug hunting and static proof verification techniques
• Familiarity with automating formal verification workflows within a CI/CD environment
• Deep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink
• Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)
• Patents or publications in formal verification or hardware verification methodologies
• Track record of recruiting, mentoring, and developing formal verification talent across distributed teams

Salary range is $230,000 to $285,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.

Key Responsibilities

• As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
• Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
• Architect and recommend flow improvements and enhance existing methodology for high performance design.
• Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
• Work with cross function teams to define requirements and specifications to achieve best PPA
• Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity
• Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• 2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Knowledge of agentic AI solutions is a plus.
• Experience working with EDA/IP vendors for both RTL and hard-macro integration.
• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.

As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
• ≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. 
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in tcl, python or Perl.

Preferred Experience:

• Knowledge of design for test (DFT)
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.

Role Overview
Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.

Key Responsibilities

• Architecture & Technical Leadership
• Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines
• Establish architectural standards and best practices that scale across the design organization
• Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area
• Design Execution & Ownership
• Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up
• Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies
• Own accountability for design quality, schedule, and successful production delivery
• Cross-Functional Collaboration
• Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues
• Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up
• Work with firmware and software teams to optimize hardware-software interfaces
• Mentorship & Process Excellence
• Mentor and develop junior and senior engineers, elevating team technical capabilities
• Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure
• Contribute to organizational knowledge sharing and technical reviews

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure
• Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows
• Track record of delivering multiple high-performance designs to production

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)
• Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems
• Proven contributions to design methodology, CAD automation, or infrastructure improvements
• Experience leading technical teams or driving cross-functional initiatives in data center environments

Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description

We are looking for Lead ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, DDR, NVMe, USB, etc.

Basic Qualifications

· Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.

· ≥5-year experience releasing complex SoC/silicon products to high volume manufacturing.

· Working knowledge of high-speed protocols like PCIe, Ethernet, DDR, NVMe, USB, etc.

· Professional attitude with ability to execute on multiple tasks with minimal supervision.

· Strong team player with good communication skills to work alongside a team of high caliber engineers and different OSAT’s.

Required Experience

· Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.

· Collaboration with design team to define test strategy, create and own test plan.

· Familiar with high-speed load board design techniques.

· Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.

· Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.

· Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.

· Expertise in production test of high speed SerDes operating at 16Gbps and higher.

· Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.

· Experience in bringing up test programs at OSATs.

· Experience with using Advantest 93k ATE platform.

· Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

· Fluent in data processing using high level programming languages.

· Familiarity with modern databases

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR & Power Integrity to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will execute the Electro-Migration and IR Drop (EMIR) analysis and sign-off from block level to full-chip, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. You will be responsible for validating power grid architectures to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments.

Key Responsibilities

• Execute static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from the block level through to full-chip sign-off
• Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
• Work with Physical Design teams to implement optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
• Collaborate closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
• Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
• Perform root-cause analysis for voltage drop violations and EM risks, proposing and implementing layout fixes alongside the PD team
• Verify current density rules for ESD protection networks and ensure compliance with strict foundry reliability constraints
• Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

Basic Qualifications

• Bachelor's or Master's degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
• Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, Totem, or Cadence Voltus)
• Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm), including fin-heating, thermal coupling, and layout-dependent effects
• Solid understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
• Proven ability to debug complex voltage drop issues, identify "weak spots" in the grid, and drive convergence on large, complex designs
• Proficiency in Python, Tcl, or Perl for flow automation and data parsing

Preferred Experience

• Experience with AI, networking, PCIe, CXL, or large-scale SerDes integration
• Background in Analog/Mixed-Signal EMIR analysis (using Totem or specialized analog flows)
• Experience performing Chip-Package-System (CPS) thermal and power co-simulation
• Familiarity with thermal analysis tools and their interaction with electrical performance
• Experience working with sign-off criteria and margins for high-volume production chips

Job Description

We are seeking a Technical Lead Digital Design Engineer with deep expertise in high-performance PCIE controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for Serdes and Controller IPS, processor and peripherals
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensure timing closure, assess verification completeness, CDC, lint etc.
• Utilize tools from Synopsys/Cadence for design and emulation.

Basic Qualifications:

• Bachelor’s in Electronics/Electrical engineering (Master's preferred).
• 5+ years of digital design experience, with 4+ years focused on PCIE controller, PCS or PHY implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise:

• Hands-on experience with PCIE Controller or Serdes/PHY IP.
• Hands-on pre-silicon and post-silicon design implementation.
• Hands-on experience  FW interaction and embedded design.
• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
• Top level integration and DFT knowledge.

Preferred Experience:

• PCIE SerDes controller or IP level experience.
• Understanding of PAD design, DFT, and floor planning.
• Experience with NIC, switch, or storage product development including embedded FW.
• Familiarity with working in design and verification workflows in a CI/CD environment.