Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle. 

As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers. 

Location - San Jose, CA OR Israel 

Key Responsibilities 

• Product Technical Ownership 

• Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement 

• Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met 

• Lead development of large-scale chips (300-400mm²) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures 

• Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths 

• Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality.  

• Cross-Functional Technical Leadership 

• Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest 

• Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria 

• Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies 

• Work closely with physical design teams on timing closure, power optimization, and backend execution 

• Process Excellence & Organizational Development 

• Establish and reinforce scalable processes, documentation, and handoffs that support company growth 

• Provide structured, data-driven decision-making and maintain a crisp operational cadence across the product line 

• Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration 

• Model steady, calm leadership, particularly in high-stakes or ambiguous situations 

• Shape engineering culture and talent strategy to support Astera's rapid growth trajectory 

Basic Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 

• 15+ years of experience across architecture, silicon design, validation, systems, or related domains 

• Proven track record of developing large-scale chips (300mm²+) through successful tapeout 

• Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures 

• Strong understanding of RTL design, design verification, DFT, and physical design flows 

• Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures 

• Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership 

• Strong communication and executive presence with the ability to influence at all levels of the organization 

Preferred Qualifications 

• Master's degree in Electrical Engineering or Computer Engineering 

• Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures 

• Experience with advanced process nodes (7nm, 5nm, or below) 

• Background in power management, clocking architectures, or high-speed analog integration 

• Experience operating in fast-growing startups or hyper-scale environments 

Key Leadership Competencies 

• Systems Thinking: See the big picture while managing details 

• Emotional Intelligence: Calm under pressure, empathetic, and influential 

• Adaptability: Thrive in ambiguity and fast-changing environments 

• Execution Discipline: Deliver predictable results without sacrificing innovation 

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

• Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
• Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
• Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
• Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
• Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

Basic Qualifications

• B.Sc. in Electrical Engineering or Computer Engineering
• 5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting)
• Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels
• Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off
• Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure

Preferred Experience

• Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia)
• Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration
• Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Senior DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Senior DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

• DFT Architecture & Strategy

  • Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
  • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
  • Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies

• Test Pattern Development & Optimization

  • Generate and optimize high-quality test and debug patterns for production
  • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
  • Drive test coverage and quality metrics to meet stringent manufacturing requirements

• Cross-Functional Collaboration & Methodology Innovation

  • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
  • Participate in developing and maintaining cutting-edge DFT implementation flows
  • Automate and improve methodologies using advanced scripting and tools

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of hands-on experience in DFT roles at semiconductor companies
• Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG
• Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent)
• Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA)
• Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements
• Experience in chip bring-up and mass production activities
• Background in advanced process technologies (7nm and below)
• Excellent communication skills with ability to work effectively in global team environments

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.

Key Responsibilities

• Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
• Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
• Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
• Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
• Own the design database structure and version control to ensure team alignment and data integrity
• Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
• Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

Basic Qualifications

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on professional experience with back-end industrial tool suites (e.g., Synopsys Fusion Compiler or Cadence Genus/Innovus)
• Expert-level proficiency in Tcl and Python for high-level flow automation, data parsing, and tool customization
• Deep technical understanding of Physical Design concepts, including clock tree synthesis (CTS), routing congestion, timing closure, and signal integrity
• Proven experience executing sign-off flows for complex, high-performance designs
• Strong communication skills and a collaborative approach to solving complex engineering bottlenecks

Preferred Experience

• Hands-on experience with 5nm, 3nm, or more advanced process nodes
• Practical knowledge of compute farm management (LSF/Slurm) and revision control (Git) for managing massive design databases
• Experience in developing proprietary automation wrappers for industry-standard EDA tools

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

• Emulation Flow Execution & Implementation

  • Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
  • Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
  • Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market

• System-Level Debug & Validation

  • Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
  • Ensure rapid cycles from RTL to functional stability through systematic debug approaches
  • Own technical blocks and drive them to completion independently

• Cross-Functional Collaboration

  • Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
  • Ensure seamless hardware-software integration for AI infrastructure connectivity
  • Collaborate with Design and Verification teams to optimize emulation strategies

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• 3+ years of hands-on experience in Emulation at semiconductor companies
• Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce)
• Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs
• Experience developing and maintaining execution flows for building, running, and debugging emulation models
• "Can-do" approach with ability to own technical blocks and drive them to completion independently

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related field
• Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis
• Proficiency in scripting languages such as Python or TCL for automation and flow enhancement
• Experience with standard debug environments (e.g., Verdi)
• Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink)
• Background in hardware-software co-verification methodologies

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. 
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments. 

Key Responsibilities

• Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing 
• Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration) 
• Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices 
• Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints 
• Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance 
• Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets 
• Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp 
• Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews 

Basic Qualifications

• 10+ years of hands-on IC BIG package design experience for high-performance semiconductor products, with full ownership from concept through tape-out 
• Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and experience designing complex packages (BGA, FCBGA, FCCSP) 
• Strong package architecture & integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership 
• Deep understanding of signal, power, and thermal integrity at the package level, with ability to drive design tradeoffs based on analysis 
• Proven manufacturing and release experience, including DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs 

Preferred Qualifications

• Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces 
• Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.) 
• Experience supporting chiplet-based architectures and heterogeneous integration 
• Prior technical leadership or package ownership on high-volume products 

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won’t just be using tools; you’ll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.

Key Responsibilities

• Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
• Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
• Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
• Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows

Basic Qualifications

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on professional experience in relevant industries 
• Proven experience in Python and Tcl within a Linux/Unix environment
• Knowledge and experience in Verilog and/or System Verilog
• Very good communication skills

Preferred Experience

• Strong understanding of the VLSI design cycle, familiarity with clock domain crossing, simulation, debugging, synthesis and timing analysis
• Hands-on experience with industry-standard tools for lint, synthesis, simulation
• Experience with version control systems (Git) and compute cluster management (LSF/SGE)

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. 

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

• Execute SoC Top-level physical design and actively drive full-chip convergence
• Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
• Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
• Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
• Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

Basic Qualifications

• B.Sc. or M.Sc. in Electrical Engineering
• 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
• Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills
• Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
• Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration

Preferred Qualifications

• Deep understanding of Power & Noise analysis (EM/IR)
• Experience with DFT (Design for Test) integration into the physical design flow
• Background in high-speed interfaces or data center protocols

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters.

As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments.

Key Responsibilities

• Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
• Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
• Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
• Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
• Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
• Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
• Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
• Support NPI, qualification, and product sustainment activities, including vendor technical reviews

Basic Qualifications

• 5+ years of hands-on IC package design experience for high-performance semiconductor products, with full technical ownership from concept through tape-out
• Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and hands-on experience designing complex packages (BGA, FCBGA, FCCSP)
• Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership
• Deep understanding of signal, power, and thermal integrity at the package level, with the ability to execute design tradeoffs based on analysis
• Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs

Preferred Qualifications

• Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces
• Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)
• Experience supporting chiplet-based architectures and heterogeneous integration
• Demonstrated track record of complete technical package ownership on high-volume products

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Subsystem (Multiple IP’s/Partitions) Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. 

As the Physical Design Subsystem (Multiple IP’s/Partitions) Lead you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SubSystem with your team for chips that drive the world’s largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. 

Key Responsibilities

• Build and mentor a high-performing Partitions team , owning the end-to-end execution from Synthesis to Signoff 
• Take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff 
• Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) 
• Lead and guide external contractors and global partners to ensure seamless execution and delivery 
• Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon 

Basic Qualifications

• B.Sc. or M.Sc. in Electrical Engineering 
• 15+ years of hands-on experience in Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) 
• Proven experience in leading teams or projects with a "can-do" approach and excellent communication skills 
• Deep expertise in RTL2GDS flows, including P&R, STA, Physical verification (DRC/LVS), Formal verification, low-power implementation (UPF/CPF), EMIR and evaluating foundry process nodes and third-party IPs 
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) 
• Experience managing both complex Macro-level designs subsystem level and Full-Chip integration 
   

Preferred Experience

• Deep understanding of Power & Noise analysis (EM/IR) 
• Experience with DFT (Design for Test) integration 
• Background in high-speed interfaces or data center protocols 

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won’t just execute tasks; you will define the Formal verification strategy for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities

• Own and develop formal verification environments from scratch through to sign-off
• Apply formal verification methodologies and strategies to prove the correctness of intricate designs
• Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
• Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
• Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
• Architect and develop generic, common formal functions and properties to be reused across multiple projects

Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in Formal Verification within semiconductor companies
• Deep expertise in formal verification methodologies, tools, and flows
• Strong understanding of RTL design and verification principles
• Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)
• Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving

Preferred Qualifications

• Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle
• Experience with SystemVerilog UVM-based design verification
• Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe)
• Background in high-speed serial interface verification

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

• Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs
• Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners
• Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy
• Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids
• Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs
• Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA
• Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)

Basic Qualifications

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in Physical Design CAD or Physical Verification with a heavy focus on parasitic extraction
• Expert proficiency with industry-standard extraction tools such as Synopsys StarRC, Cadence Quantus (QRC), or Siemens Calibre xACT
• Strong scripting skills in Tcl and Python for flow automation and database manipulation
• Deep understanding of semiconductor physics, interconnect modeling, and the impact of parasitics on timing, EM (Electromigration), and IR drop
• Proven experience in validating tech files and running extraction for complex, multi-million gate designs

Preferred Experience

• Hands-on experience with 5nm, 3nm, or more advanced process nodes, including FinFET-specific extraction challenges
• Familiarity with 3D field solvers and their use in benchmarking standard extraction engines
• Knowledge of Netlist formats (SPEF, DSPF) and their integration into STA and Spice simulation flows
• Experience with compute farm management (LSF/Slurm) and version control (Git)

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Design Ownership & Implementation

  • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
  • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
  • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

• Quality Assurance & Design Optimization

  • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
  • Apply design techniques to meet PPA (Power, Performance, Area) targets
  • Contribute to design quality through verification and validation activities

• Methodology Innovation & Collaboration

  • Participate in design methodology improvements and tool automation initiatives
  • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
  • Collaborate effectively across teams to ensure seamless integration

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of experience in logic design at semiconductor companies
• Knowledge and experience in Verilog and/or SystemVerilog
• Excellent communication skills with ability to work effectively across teams
• Understanding of digital design principles and RTL coding best practices

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Knowledge of DDR and PCIe protocols and implementation
• Understanding of power management techniques for low-power design
• Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis
• Proficiency in scripting languages such as Python or Perl
• Experience with high-speed serial interface designs or connectivity protocols

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR & Power Integrity to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will execute the Electro-Migration and IR Drop (EMIR) analysis and sign-off from block level to full-chip, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. You will be responsible for validating power grid architectures to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments.

Key Responsibilities

• Execute static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from the block level through to full-chip sign-off
• Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
• Work with Physical Design teams to implement optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
• Collaborate closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
• Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
• Perform root-cause analysis for voltage drop violations and EM risks, proposing and implementing layout fixes alongside the PD team
• Verify current density rules for ESD protection networks and ensure compliance with strict foundry reliability constraints
• Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

Basic Qualifications

• Bachelor's or Master's degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
• Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, Totem, or Cadence Voltus)
• Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm), including fin-heating, thermal coupling, and layout-dependent effects
• Solid understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
• Proven ability to debug complex voltage drop issues, identify "weak spots" in the grid, and drive convergence on large, complex designs
• Proficiency in Python, Tcl, or Perl for flow automation and data parsing

Preferred Experience

• Experience with AI, networking, PCIe, CXL, or large-scale SerDes integration
• Background in Analog/Mixed-Signal EMIR analysis (using Totem or specialized analog flows)
• Experience performing Chip-Package-System (CPS) thermal and power co-simulation
• Familiarity with thermal analysis tools and their interaction with electrical performance
• Experience working with sign-off criteria and margins for high-volume production chips

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff Physical STA Expert to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the sign-off methodology for chips that power the world's most advanced AI clusters.

As a Staff Physical STA Expert , you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the world’s most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. 

Key Responsibilities

• Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments 
• Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence 
• Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments 
• Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners 
• Have a passion for better workflows? You’ll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarter 

Basic Qualifications

• B.Sc. in Electrical Engineering or Computer Engineering 
• 8+ years of deep, hands-on experience in Static Timing Analysis (STA) at leading semiconductor companies, specifically working on advanced process technologies 
• Deep expertise in multi-scenario STA, timing/SDC constraint development and verification. You have a "full-chip" perspective, managing both complex macro-level designs and top-level integration 
• Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off 
• Solid knowledge of physical design flows (P&R, Physical Verification) and how they intersect with timing closure 

Preferred Experience

• Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) 
• Proven track record of managing both complex Macro-level designs and Full-Chip timing integration 
• Strong background in scripting and automation to enhance timing closure efficiency