Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Summary

We are seeking a student intern to drive product quality improvements across both Astera Lab’s semiconductor and board-level products. In this role, the candidate will perform failure analysis for customer returns. The candidate will also compile 8D reports to communicate the analysis findings to the customers.

Key Responsibilities

· Perform system-level test for the customer returns on a bench in the lab.

· Review ATE test log files.

· Work with third-party labs to perform electrical FA (EFA) for more in-depth analysis.

· Log analysis results to the portal system daily.

· Work with internal teams and suppliers to drive product quality improvements.

· Write up analysis reports to provide updates to the customers. Participate in the meetings with customers to present the technical findings.

· Bring up and validate new test equipment in the lab. Update the lab inventory list.

· Perform additional tasks assigned by the Director of Field Quality Engineering.

Education & Experience

· Final year students from Bachelor’s degree are welcome to apply.

· Students from Master’s degree are preferred.

Technical Skills

· Good knowledge of IC fabrication, packaging, board assembly (SMT), and test processes

· Strong communication skills in English and Mandarin.

Working Conditions:

· May require occasional travel to customer sites within Taiwan.

· Must be flexible to work on-site and available during business hours for at least 3 days per week.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Principal Quality Engineer 

Role Summary 

As Principal Quality Engineer based in Aachen, you are the technical authority for quality across our optical product line and regional quality lead for European operations. You will bridge HQ (San Jose) and the Aachen manufacturing site, drive quality integration for in-house optical manufacturing, lead supplier quality for regional semiconductor and optical vendors, and support Asia-based RMA activities for in-region products. 

Key Responsibilities 

Quality‑System Integration: Lead ISO 9001 alignment between San Jose HQ, Aachen, and other regional locations to harmonize procedures, audit schedules, and corrective action processes across both semiconductor and optical product lines. 

Process Development & Implementation: Design, document, and roll out new quality processes, procedures, and work instructions needed to support emerging photonics products and manufacturing capabilities. 

In‑Process Inspection & Controls: Oversee in‑process inspection activities for the in‑house manufacturing operation, establishing SPC, go/no‑go checkpoints, and real‑time defect‑tracking dashboards. 

Supplier Quality (Optics): Provide technical support and quality assurance for optical‑component and optical‑coating suppliers; conduct supplier audits, and drive corrective‑preventive actions (CAPA). 

Supplier Quality (Semiconductor): Serve as the regional point of contact for semiconductor suppliers, monitoring supplier performance, assisting with supplier audits, and leading issue resolution. 

Product Quality: Core Semiconductor Business – Lead technical investigation of field returns, warranty claims, and reliability failures for semiconductor and optical products; coordinate 8D root-cause analysis and interface with Field Application Engineers (FAEs).  

Cross‑Site Liaison: Act as the primary conduit between the Aachen site, other European/EMEA sites, and the San Jose HQ for quality information exchange, escalation handling, and best‑practice sharing. 

Metrics & Reporting:  Define, track, and report key quality KPIs (PPM, DPMO, warranty cost, MTBF, supplier defect rate, etc.) to senior leadership across the BU and corporate HQ. 

Quality Improvement: Lead and demonstrate the application of advanced quality improvement techniques including Lean, Six‑Sigma, and other methods to reduce waste, improve yield, and enhance overall product reliability. 

Education & Experience 

Technical Skills 

Core Competencies 

 Compensation

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and benefits. Astera Labs is committed to fair and equitable pay practices.

Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Role Overview 

Astera Labs is seeking an experienced and hands-on Principal Optical Reliability Engineer to drive reliability strategy across our cutting-edge portfolio of connectivity products, with a focus on silicon photonics and optical components. As AI infrastructure demands unprecedented bandwidth and performance, this role is critical to ensuring our products deliver exceptional reliability through end-of-life. 

You will lead reliability initiatives and serve as an internal consultant, defining and implementing methodologies across component, chiplet, photonic, and board-level products. This is a high-impact position where you'll partner closely with design, product/test engineering, quality, and manufacturing teams to embed reliability-aware principles. 

Key Responsibilities 

• Reliability Strategy & Methodology 
  • Develop and implement comprehensive design reliability methodologies for semiconductor circuits and optical systems, including pre-qualification, production release, ongoing reliability monitoring (ORM), and soft error evaluation 
  • Lead the application of advanced reliability modeling techniques to analyze trade-offs between performance and long-term product reliability 
  • Establish and refine usage models to guide design-phase reliability assessments and integrate learning from manufacturing and field return data in post-silicon validation 
• Failure Analysis & Root Cause 
  • Apply expert knowledge of semiconductor and optical reliability failure mechanisms, including Electrostatic Discharge (ESD), Latch-Up (LU), Soft Errors, Gate Oxide Time-Dependent Dielectric Breakdown (GOX TDDB), Electromigration, Device Aging, laser degradation, and photodetector wear-out 
  • Utilize a hands-on approach to comprehend silicon, photonic, and package-level failure mechanisms, collaborating seamlessly with internal and external teams to drive root cause analysis and resolution 
  • Evaluate qualification results for new product introductions and drive continuous improvement in design-for-reliability tools, processes, and organizational knowledge 
• Cross-Functional Collaboration & Vendor Management 
  • Collaborate across design, product engineering, manufacturing, and reliability teams to capture and institutionalize best practices that improve product robustness and reduce DPPM 
  • Serve as a subject matter expert helping design engineers incorporate reliability-aware design principles early in development 
  • Work closely with vendors to review and interpret component specifications, reliability data, and qualification reports, including Mean Time Between Failures (MTBF), failure-rate predictions, derating analysis, and stress test results 

Basic Qualifications 

• Master's degree in Electrical Engineering, Applied Physics, Photonics, or a related field 
• 8+ years of experience in semiconductor reliability, with direct experience in silicon photonics, optical components, or optoelectronic device reliability 
• Strong background in semiconductor physics, device modeling, and reliability verification techniques including statistical and probability techniques 
• Deep knowledge of advanced packaging technologies, including 2.5D, 3D, and chiplet architectures, as well as module and system board reliability 
• Working knowledge of electronic components/devices and their failure modes and mechanisms 
• Proven leadership in driving complex technical issues to closure across global, cross-functional teams 

Preferred Qualifications 

• PhD in Electrical Engineering, Applied Physics, or Photonics 
• Experience with silicon photonics reliability, including laser aging, photodetector degradation, and fiber coupling reliability 
• Knowledge of high-performance compute and AI cloud infrastructure, as well as switch/network interfaces 
• Experience with PCBA (printed circuit board assembly) design, fabrication, and validation testing 
• Strong experience in product reliability in the context of mechanical, thermal, and electrical stresses for modules and board assemblies 
• Excellent communication skills with the ability to articulate technical concepts clearly across all levels of the organization 
• Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

 Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description:

We are seeking an experienced leader to drive Supplier / Manufacturing Quality Engineering to anchor our global supplier quality efforts across both Astera Lab’s semiconductor and board-level products. In this role, candidates will drive leading supplier quality across key manufacturing partners including IC fabs, OSAT’s, and PCB/PCBA vendors. A strong foundation in supplier quality engineering, uniquely paired with experience in advanced data analytics (including AI and machine learning) for predictive quality, risk assessments, and product quality analytics will be highly valuable to this role.

Responsibilities:

Supplier Quality Management

· Nurture winning partnerships across all our strategic manufacturing suppliers: semiconductor wafer fabs, advanced packaging & test (OSAT), boards & assemblies (PCB / PCBA / SMT), substrates / interposers, probe cards, and passive components.

· Develop robust supplier selection and onboarding processes in collaboration with Design, Procurement, Business & Engineering Operations teams.

· Define, build, and manage the systems to collect the data (KPI’s) needed to track supplier performance and drive continuous improvement.

· Audit to assess the effectiveness of supplier process controls, manufacturing capabilities, and overall quality management system.

· Coach suppliers by sharing your deep manufacturing experience and knowledge.

· International travel as needed, potentially on short notice. There is no minimum amount but prepare to accommodate up to 20%.

Advanced Data Analytics & AI/ML

· Create data collection methods to enable product and supplier advanced data analytics needed for monolithic, chiplet, and board products. Data sources will include manufacturing inline controls, production test (including data collection from advanced embedded agents), and failure analysis activities.

· Leverage data into quality models & methods to predict product quality issues and supply chain risks.

· Integrate AI/ML tools into quality systems and dashboards (e.g., outlier screening, automated defect detection, trend analysis, real-time alerts).

· Experience with AI/ML tools is a plus but not required; ability to work with technical partners on model development is key.

Cross-functional Collaboration

· Interface with R&D, NPI, product engineering, ops and other engineering teams to provide supplier input into product design and DFX.

· Support early supplier involvement and ensure quality requirements needed for manufacturability & testability are achieved, and learnings are propagated appropriately to other products in production & development.

· Represent supplier quality as needed in line failure reviews, excursion management, material reviews (MRB), and CAPA processes.

· Partner with engineering and manufacturing teams to conduct quarterly engineering reviews, evaluate supplier changes (PCN), and assess supplier risks.

· With engineering engagement, lead quality audits, and corrective action activities using tools such as 8D, 5-why, and FMEA.

Education & Experience

· Bachelor’s or Master’s degree in Engineering or equivalent experience.

· 8+ years of career progression in supplier quality engineering in the semiconductor and/or board-level electronics industry.

· 3+ years direct experience working embedded within a high-volume advanced manufacturing operation in an engineering role.

· Experience with supplier development in Asia with global manufacturing supply chains.

· Six Sigma or ASQ certification a plus

Technical Skills

· Strong knowledge of IC fabrication, packaging (including chiplet), board assembly (SMT), and test processes.

· Familiarity with reliability qualification methodologies in the application of IPC, Telcordia, JEDEC requirements.

· Proficiency with quality engineering tools (FMEA, APQP, PPAP, SPC, OE, etc.).

· Experience using analytics tools (e.g., JMP, SQL, Excel) to support quality insights. Exposure to AI/ML frameworks is a plus, but not required.

· Fluent in English and Mandarin

As an Astera Labs Technical Lead Lab Validation Engineer, you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions.  You will:

• Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions.  Collaborate with design, validation, and system engineering teams as needed.
• Modify device firmware to test out engineering theories leading to potential fixes or production screens.
• Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems.
• Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability.
• Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports.
• Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures.
• Develop and run stress tests and margining experiments to identify weak design or process corners.
• Provide feedback on system-level integration challenges for retimers and PCIe switches (e.g., board layout, equalization tuning, firmware interactions).
• Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing.
• Document debug findings, propose design/process/test improvements, and contribute to FA methodologies.
• Participate in new product development process to ensure readiness for customer returns before products are launched. Collaborating in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts.

Basic qualifications:

• Minimum of a Bachelor’s in Electrical Engineering while a Master’s degree is preferred. 
• Minimum of 10 years relevant experience of which 5 years’ is hands-on mixed high-speed lab experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA.
• Python programming.
• Deep understanding of PCIe protocol (up through Gen6), retimer architecture, and SerDes signal integrity.
• Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing).
• Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures).
• Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity.
• Experience in post-silicon validation and bring-up of high-speed PHYs or retimers.
• Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures.
• Strong written and verbal communication skills.

Preferred experience (ideal candidate has some of this, but OJT is also possible):

• C (not C++).
• Experience with optics.
• Experience with chip-level security and RAS features.
• ATE (Automated Test Equipment) Advantest V93K.
• Understanding of system-level architecture for servers, storage, and AI/ML platforms where PCIe retimers/switches are deployed.

Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.

The base salary range is $160,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job Description

We are seeking a detail-oriented Quality Systems Engineer / PLM Analyst to support the administration and continuous improvement of our Quality Management System (QMS) and Product Lifecycle Management (PLM) processes.

This role will support the management of product data, engineering change control, and document control within Arena PLM, while also contributing to key QMS activities such as CAPA management, internal audits, and controlled documentation. The position plays a critical role in ensuring accurate product lifecycle data, effective configuration management, and compliance with quality standards across semiconductor, hardware, and optical product lines.

The ideal candidate will work cross-functionally with engineering, manufacturing, quality, and operations teams to ensure efficient product development processes and strong quality system governance.

Key Responsibilities

PLM System & Product Data Management

• Support administration and daily operations of Arena PLM, including product records, document control, and engineering change processes.
• Create and maintain items, Bills of Materials (BOMs), and product structures for semiconductor, hardware, and optical products.
• Coordinate and manage Engineering Change Orders (ECOs) including creation, workflow routing, and release tracking.
• Maintain document revision control, lifecycle states, and product configuration data within the PLM system.
• Support New Product Introduction (NPI) processes including part setup, BOM releases, and product data readiness.
• Ensure accurate data synchronization between PLM and ERP systems (e.g., Oracle ERP) in collaboration with IT and operations teams.
• Assist with PLM data governance, cleanup, and process standardization initiatives.

Quality Management System (QMS) Support

• Support the administration and continuous improvement of the company’s Quality Management System (QMS).
• Maintain controlled documents, procedures, and records, ensuring proper revision control and accessibility.
• Assist with Corrective and Preventive Actions (CAPA) tracking and documentation.
• Participate in Material Review Board (MRB) processes and nonconformance documentation.
• Support internal and external audits, including documentation preparation and follow-up actions.
• Maintain quality records and metrics used in management reviews and compliance reporting.
• Ensure alignment between engineering changes in PLM and updates to quality system documentation.

Cross-Functional Collaboration

• Serve as a liaison between engineering, manufacturing, operations, and quality teams to support effective PLM and QMS processes.
• Provide training and guidance to users on PLM system usage and document control procedures.
• Support initiatives to improve product data management, engineering change processes, and quality system efficiency.
• Drive adoption and compliance with PLM and quality documentation processes across the organization.

Required Qualifications:

• Bachelor’s degree in Engineering, Science, Quality, or a related technical field.
• 3–5 years of experience supporting PLM systems and/or Quality Management Systems.
• Experience working with PLM platforms such as Arena PLM or similar product lifecycle management systems.
• Familiarity with engineering change management (ECO/ECN), BOM management, and document control processes.
• Experience supporting QMS processes such as CAPA, MRB, internal audits, and document control.
• Experience working with ERP systems such as Oracle ERP or similar platforms.
• Strong organizational and analytical skills with high attention to detail.
• Excellent communication and cross-functional collaboration skills.

Preferred Skills: 

• Experience supporting product development environments in semiconductor, electronics, or hardware manufacturing.
• Familiarity with quality standards such as ISO 9001.
• Experience supporting New Product Introduction (NPI) processes.
• Knowledge of configuration management and product data governance.
• Experience generating reports or analytics from PLM or ERP systems.