The Role

We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

Responsibilities

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Serve as the primary technical interface to substrate vendors, assembly houses, and OSATs.
• Drive material selection, substrate technology choices, and assembly process optimization.

Qualifications 

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 10+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies.

Nice to Have

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
• Background in high-speed digital or mixed-signal SoCs.
• Familiarity with aerospace, space, or high-reliability electronics.
• Experience defining packaging strategy from early architecture through first silicon and volume ramp.
• Demonstrated history of building or scaling package design methodology within an organization.

Compensation and Benefits:

• Base salary range for this role is $200,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role

We are seeking a Senior Embedded Firmware Engineer to develop and enhance low‑level embedded firmware for high‑performance mixed‑signal and digital SoCs. In this role, you will contribute to the bring‑up, validation, and production readiness of custom silicon by working closely with digital ASIC, mixed‑signal, RF, verification, and system engineering teams. You will help implement core firmware components, validate hardware functionality, and ensure reliable, scalable firmware foundations for next‑generation products.

Responsibilities

• Contribute to the design and implementation of embedded firmware architecture, including boot flows, HAL components, drivers, and system services.
• Develop low‑level firmware in C/C++ (and assembly when required) for CPUs, DSPs, and microcontrollers within custom SoCs.
• Implement and maintain bootloaders, secure boot flows, and early hardware initialization sequences.
• Develop device drivers for on‑chip peripherals such as DMA engines, memory controllers, interconnects, SerDes, ADC/DAC interfaces, timers, and GPIO.
• Participate in pre‑silicon firmware development and validation activities.
• Support post‑silicon bring‑up, including power‑on sequencing, clock/reset initialization, memory bring‑up, and peripheral testing.
• Debug hardware/firmware interactions using JTAG, logic analyzers, oscilloscopes, trace tools, and custom debug instrumentation.
• Collaborate with SoC architects and designers to refine register maps, memory maps, interrupt structures, DMA flows, and debug infrastructure.
• Provide firmware input during design reviews and silicon development milestones.
• Bring up and integrate RTOS or bare‑metal environments.
• Support integration with higher‑level system software or application processors.
• Implement robust error handling, logging, and recovery mechanisms.
• Contribute to manufacturing test firmware, production firmware, and field diagnostics.
• Help ensure long‑term maintainability and scalability of firmware across multiple SoC generations.

Qualifications

• 5+ years of experience in embedded firmware development for SoCs or complex embedded systems.
• Strong proficiency in C/C++ for embedded systems and a solid understanding of low‑level hardware interactions.
• Hands‑on experience with SoC bring‑up or board‑level bring‑up.
• Strong understanding of CPU architectures (ARM, RISC‑V, or similar), memory systems (SRAM, DRAM, DDR, caches), interrupts, DMA, and low‑power states.
• Experience collaborating with ASIC/SoC design or hardware engineering teams.
• Demonstrated ability to debug complex hardware/firmware issues.

Nice to Have

• Experience with secure boot, hardware security modules, or cryptographic accelerators.
• Familiarity with pre‑silicon environments such as RTL simulation, emulation, or FPGA prototyping.
• Experience with high‑speed interfaces (PCIe, Ethernet, JESD, SerDes).
• Background in satellite communication, networking, compute, automotive, or other high‑reliability systems.
• Experience developing firmware for radiation‑tolerant or mission‑critical systems.

Compensation and Benefits:

• Base salary range for this role is $160,000 – $220,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role supports the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will collaborate with internal teams for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.  

Responsibilities 

• Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Establish package design standards, methodologies, and best practices.  
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces. 
• Support package-level SI/PI strategy, including high-speed digital interfaces, power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling. 
• Drive material selection, substrate technology choices, and assembly process optimization.  

Qualifications 

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 5+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies. 

Nice to Have

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates). 
• Background in high-speed digital or mixed-signal SoCs. 
• Familiarity with aerospace, space, or high-reliability electronics. 
  

Compensation and Benefits:

• Base salary range for this role is $180,000 – $260,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior Mixed-Signal Behavioral Modeling Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams.   

Responsibilities 

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.). 
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog. 
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog). 
• Integrate AMS models into digital verification environments (UVM-based). 
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification. 
• Support architectural exploration through early-phase modeling and system-level simulations.  
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions. 
• Work with digital and verification teams to ensure seamless integration of AMS models. 
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up. 
• Act as technical leader and subject-matter expert.  

Required Qualifications  

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field. 
• 5+ years of experience in analog/mixed-signal modeling and/or AMS verification. 
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages. 
• Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers). 
• Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar). 

Preferred Qualifications  

• Experience building AMS verification methodologies from scratch. 
• Familiarity with UVM-based verification and digital design flows. 
• Knowledge of signal processing theory, RF system modeling, or communication systems. 
• Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling. 
• Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

• Base salary range for this role is $160,000 – $230,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Drive advancement of DV methodologies and improvements.
• Manage external IP providers and verification partners when needed.
• Take lead on large and/or complex systems. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
• Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
• Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
• Experience with developing and integrating reference models.
• Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
• Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
• Involvement in post-silicon validation planning and execution. 

Nice to Have

• Experience with low power verification.
• Experience with analog behavioral models.
• Familiarity with physical design flows.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $190,000 – $285,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.  

Responsibilities 

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 
• Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 
• Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 
• Develop and maintain scripts and automation to improve flow efficiency and consistency. 
• Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 
• Assist in chip-level integration, ECOs, and tapeout preparation. 
• Contribute to methodology development, tool evaluation, and flow documentation. 
• Support your product through production and spaceflight.  

Required Qualifications  

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 
• 5–10 years of experience in ASIC physical design for complex SoCs. 
• Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 
• Strong understanding of timing analysis, power optimization, and physical verification flows. 
• Experience with hierarchical or flat SoC design methodologies. 
• Familiarity with FinFET technologies. 
• Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 
• Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications  

• Exposure to radiation-hardened or space-qualified ASICs. 
• Experience with chip-package co-design or advanced packaging (2.5D/3D). 
• Familiarity with physical design service vendor management or offshore collaboration. 
• Experience with sign-off through TSMC. 
• Experience with Gate-All-Around technologies.  
• Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
• Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.

Required Qualifications 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC physical design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
• Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
• Excellent communication, leadership, and cross-functional collaboration skills.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

• Base salary range for this role is $190,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.  

Responsibilities 

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. 
• Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. 
• Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.  
• Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. 
• Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). 
• Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. 
• Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. 
• Contribute to methodology development, automation, and flow improvements. 

Qualifications  

• B.S. or M.S. in Electrical Engineering or related field. 
• 7+ years of experience in DFT for complex SoCs. 
• Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows. 
• Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. 
• Experience with low-power DFT techniques. 
• Familiarity with mixed-signal integration challenges and test methodologies. 
• Strong debugging skills across RTL, gate-level, and silicon. 

Nice to Have 

• Experience with MBIST/LBIST implementation and memory repair flows. 
• Knowledge of IEEE 1149.x (JTAG/boundary scan) standards. 
• Experience with multi-voltage domain and power-aware DFT. 
• Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing). 
• Scripting experience for automation. 
• Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs. 
• Prior involvement in A0 silicon bring-up and yield ramp. 
• Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role

We are seeking a Senior RFIC Layout Designer to drive the physical implementation of advanced RF and mixed-signal integrated circuits for next-generation satellite communication systems. This is a senior individual contributor role focused on hands-on layout execution and top-level integration, working closely with cross-functional teams to deliver high-performance silicon.

Responsibilities

• Execute high-quality layout for RF, analog, and mixed-signal blocks in advanced FinFET nodes (e.g., LNA, RF amplifiers, mixers, PLL, LO generation, ADC/DAC, baseband filters, bandgap/bias/LDO)
• Contribute to top-level layout integration, including block placement, routing, power planning, and floorplanning.
• Contribute to layout strategies to meet performance, area, power, reliability, and manufacturability targets.
• Ensure robust implementation of matching and symmetry for sensitive RF/analog structures, and high-frequency routing and parasitic control.
• Ensure robust implementation of EM/IR, ESD, latch-up, and reliability considerations
• Collaborate closely with RF/analog designers, digital implementation teams, package/PCB engineers, and CAD to ensure seamless integration.
• Participate in establishing review processes (layout reviews, signoff checks, and quality metrics) to ensure first-pass silicon success.
• Drive full-chip physical signoff, including DRC/LVS/ERC closure, EM/IR and reliability verification.
• Own tapeout readiness and interface with foundry and EDA partners as needed.

Qualifications 

• 5+ years of RF/analog/mixed-signal layout experience.
• Extensive hands-on experience with advanced FinFET process technologies (≤16nm preferred).
• Proven track record of top-level SoC layout integration and successful silicon tapeouts.
• Experience collaborating with distributed teams, including collaborating with external layout vendors.
• Deep understanding of RF and analog layout techniques and device physics, including high-frequency effects, parasitics, and isolation strategies.
• Extensive hands-on experience with power planning and full-chip physical architecture.
• Strong proficiency with industry-standard tools.

Nice to Have

• Experience with high-frequency RF systems for wireless or satellite communications.
• Experience working on large mixed-signal SoCs with significant digital content.
• Exposure to reliability requirements for space or high-reliability applications.
• Experience developing methodologies in a high-growth environment.

Compensation and Benefits:

• Base salary range for this role is $120,000 – $180,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
• Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
• Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Nice to Have

• Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
• Familiarity with developing and integrating reference models.
• Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI).
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

• Base salary range for this role is $130,000 – $200,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are looking for a Principal ASIC Synthesis and Timing Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the constraints development and validation—from RTL handoff to synthesis —and collaborate closely with architecture, RTL design, DFT, and physical design team. This role also involves managing external physical design partners, driving convergence of schedule and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

• Own the complete RTL-to-Synthesis flow: Do synthesis at block and top level, Work with physical design team to integrate the floorplanning information for physical synthesis. 
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Own Lint, CDC and UPF checks and drive collaboration to close out issues. 
• Develop an end to end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the  post layout netlist.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.  

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with timing closure, IR drop analysis, low power implementation and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience in design convergence with offshore/outsourced PD teams or vendors.
• Able to resolve formal verification issues. 
• Able to analyze and fix VCLP issues regarding UPF.
• Experience with Logic equivalence check debug, Functional ECO development and implementation with minimal database disruption, Low power checker to validate UPF;
• Familiarity with DFT integration, STA sign-off with functional ECO implementation.
• Excellent communication, leadership, and cross-functional collaboration skills.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team. 

Nice to Have 

• Exposure to radiation-hardened or space-qualified ASICs.
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.  
• Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

• Base salary range for this role is $190,000 – $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
• Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
• Participate in ASIC team interviews.
• Contribute to advancement of DV methodologies and improvements.
• Engage external IP providers and verification partners when needed. 

Qualifications 

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
• Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
• Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
• Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). 

Nice to Have

• Experience with developing and integrating reference models.
• Understanding of low power verification.
• Familiarity with gate-level simulation and analog behavioral models.
• Involvement in post-silicon validation planning and execution.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus. 
  

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Mixed-Signal Behavioral Modeling Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams.  

Responsibilities 

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.). 
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog. 
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog). 
• Integrate AMS models into digital verification environments (UVM-based). 
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification. 
• Support architectural exploration through early-phase modeling and system-level simulations.  
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions. 
• Work with digital and verification teams to ensure seamless integration of AMS models. 
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up. 
• Act as technical leader and subject-matter expert.  

Required Qualifications  

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field. 
• 2+ years of experience in analog/mixed-signal modeling and/or AMS verification. 
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages. 
• Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers). 
• Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar). 

Preferred Qualifications  

• Experience building AMS verification methodologies from scratch. 
• Familiarity with UVM-based verification and digital design flows. 
• Knowledge of signal processing theory, RF system modeling, or communication systems. 
• Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling. 
• Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

• Base salary range for this role is $130,000 – $180,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks