We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance.

The ideal candidate has a strong background in DevOps, workload porting, or application enablement. While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale.

This role is remote, based in the United States or Australia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware.
• Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier.
• A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through strategic IT and DevOps enablement.
• Collaborative & Cross-Functional: You enjoy acting as the "technical glue" between IT, DevOps, and AI teams, coordinating complex efforts across boundaries to ensure seamless workload transitions.
• Architecture Agnostic: You are a systems thinker who understands how to bridge the gap between infrastructure and core silicon engineering.

What We Need

• Education: BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
• Workload Expertise: Extensive experience in workload porting, DevOps engineering, or application enablement.
• Systems Fluency: Strong familiarity with CPU architectures and systems design, with a proven track record of troubleshooting and optimizing performance across new architectures.
• Leadership Qualities: Ability to coordinate across multiple technical teams and the potential to mentor or grow a small engineering pod.
• Execution Focus: A mindset geared toward technical delivery and methodology development rather than broad community networking.

What You Will Learn

• Gain deep expertise in bleeding-edge RISC-V system software across server and AI-accelerated environments.
• Directly influence an upcoming project, a high-visibility initiative shaping the future of our internal compute infrastructure.
• Work at the intersection of AI/ML workloads and hardware/software co-design.
• Shape the technical roadmap for how the industry adopts RISC-V for high-performance compute.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is looking  for a STA methodology engineer who owns timing across advanced-node, high-performance, low-power designs, bringing deep expertise with PrimeTime, noise/crosstalk/OCV analysis, and strong scripting skills. They will lead the development and optimization of end-to-end STA methodologies and flows, drive data- and ML-assisted timing automation, and partner closely with logic, physical design, DFT, and EDA vendors to solve complex timing challenges across multiple IPs and products. 

This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Fort Collins, CO.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who you are

• An experienced Static Timing Analysis (STA) / timing methodology engineer with a BS/M in Electrical or Computer Engineering (or equivalent experience) 5+ years in industry, focused on high-performance and low-power designs at advanced technology nodes. As well as a deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• You are fluent with PrimeTime and related signoff tools (e.g., PT-SI, PTPX, PT-ECO) and have extensive hands-on experience driving signoff correlation, advanced static timing analysis, and signoff closure.
• You are strong at debugging timing constraints, resolving timing correlation issues, and developing effective timing closure strategies.
• You write robust, production-quality scripts in Tcl, Python, and/or Perl and are comfortable building and maintaining CAD utilities and flow components.

What we need

• A senior methodology owner to lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes. Experience developing and enhancing STA methodologies across the full RTL-to-GDS flow, including: Early timing estimation and timing feasibility checks. Timing optimization techniques in synthesis and place-and-route. Timing signoff methodologies and criteria. Post-route timing ECO strategies and execution.
• A technical leader to architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA (Power, Performance, Area) and runtime efficiency.
• A methodology engineer who can explore and deploy data-driven and ML-assisted techniques to: Improve STA automation. Predict and prioritize timing risk. Guide optimization strategies across blocks and full-chip. Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity.
• A methodology owner who continuously refines workflows and introduces new technologies to ensure robust, PPA-optimized timing solutions across all product lines.

What you will learn

• How to scale STA methodologies across a diverse portfolio of IP and SoC programs, balancing aggressive performance targets with strict power and area constraints.
• Best practices for integrating data-driven and ML-assisted approaches into timing flows to improve automation, predictability, and decision-making.
• How to influence tool roadmaps by partnering closely with leading EDA vendors on advanced-node timing, noise, and variability challenges.
• How to operate within and help shape a rapidly evolving startup design environment, including tradeoffs between quick solutions and long-term methodology investments.
• Deeper cross-functional insight into how logic design, physical design, and DFT interact with STA methodology, and how to build flows that serve all of these stakeholders effectively.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Implementation of DFT features into RTL using verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in finFET technologies.
• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

At Tenstorrent, we are building open, scalable compute for real AI workloads. As Director of Customer Engineering, you own the technical relationship with strategic customers and FAEs, turning their silicon needs into precise requirements for our hardware and software teams. You connect customer architectures to Tenstorrent platforms so their models run efficiently on our silicon.

This role is hybrid, based out of Toronto, Austin, TX or Belgrade, Serbia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced leader of customer-facing technical teams and Field Application Engineering organizations.
• Strong background across RTL, verification, and physical design for custom silicon programs.
• Systems thinker who understands how RTL choices affect software, performance, and customer solutions.
• Clear communicator who aligns customers, FAEs, and internal teams around shared technical goals.

What We Need

• Own technical customer relationships and convert high-level asks into concrete engineering specifications.
• Coordinate with hardware and software leads on customer-specific NEO silicon configurations.
• Oversee RTL changes and NEO customization required to meet each customer’s requirements.
• Drive tight collaboration between customer silicon teams and internal DV for reliable delivery.

What You Will learn

• How to scale technical customer success for custom AI silicon at state of art.
• End-to-end advanced chip design workflows for large customer programs.
• How open-source AI software stacks integrate with Tenstorrent hardware in production settings.
• Ways to influence product roadmaps directly from real customer workloads and feedback.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we build open, state of art compute for AI and RISC‑V. You will create and own our quality organization across hardware systems and custom silicon, setting the standards that let us scale fast without sacrificing reliability. This role requires regular domestic and international travel to suppliers, contract manufacturers, and Tenstorrent sites.

This role is hybrid, based out of Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• 12+ years driving hardware or semiconductor quality across design, process, incoming, supplier, and systems.
• Experienced with servers, PCs, and/or PCIe cards, plus ASIC or custom silicon quality.
• Comfortable leading global CM and supplier audits and traveling frequently worldwide.
• You have experience working in companies that have transitioned from R&D to Product focused. 
• Have built a quality org and QMS from zero and can explain your design choices.

What We Need

• Build the quality team from scratch, including org design, hiring, and cross‑functional ownership.
• Own the QMS, including ISO 9001, documentation, audits, KPIs, and continuous improvement.
•  Drive Design for Quality for hardware and silicon, from bring‑up through post‑silicon validation.
•  Define manufacturing controls, FMEAs, control plans, NPI quality gates, and supplier quality programs.

What You Will Learn

• How to apply open, state of art compute to demanding hardware and silicon quality problems.
• To shape quality culture, metrics, and supplier relationships for a fast‑growing silicon company.
• How reliability data, field returns, and standards like JEDEC and IPC drive product decisions.
• To scale quality systems that support hyperscaler, cloud, and semiconductor startup customers.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Join our innovative team as a Director, Systems & Solutions where you'll play a pivotal role in deploying and optimizing cutting-edge computer systems and AI hardware. If you have a passion for hardware technologies, including accelerators, CPUs, GPUs, and thrive in a dynamic, hands-on technical environment, we would love to hear from you. In this role you will be leading a team and helping us scale our customer base.

This role is hybrid, based out of Santa Clara, CA; Austin, TX or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on manager with a deep understanding of computer systems and AI hardware, driven by curiosity and a passion for performance.
• You’re comfortable getting into the technical details - from CPU and GPU architecture to firmware and drivers and thrive in dynamic, hands-on environments.
• You excel at problem solving and enjoy working directly with customers to implement and optimize advanced computing solutions.
• You communicate clearly, collaborate effectively across teams, and take pride in delivering reliable, high-quality systems.
• You’re motivated by impact - eager to see your work come to life in the next generation of AI and high-performance compute deployments.

What We Need

• Strong experience with computer hardware and system architecture, including CPUs, GPUs, FPGAs, and AI accelerators.
• Deep understanding of Linux operating systems, with experience in configuration, performance optimization, and administration.
• Proficiency in system software, including drivers, firmware, and related hardware-level tools.
• Working knowledge of electrical systems, including wiring, cabling, and thermal management.
• The ability to travel up to 50% of the time both domestically and internationally. 

What You Will Learn

• How to deploy, validate, and optimize AI compute systems at scale across diverse customer environments.
• End-to-end exposure to hardware-software integration, from firmware and drivers to full system bring-up.
• Hands-on experience with accelerator-based architectures and cutting-edge hardware design.
• Collaboration with world-class engineering teams building open, high-performance systems based on RISC-V and modular chiplet architectures.
• The opportunity to directly shape how customers adopt and scale next-generation AI and HPC hardware, helping push the boundaries of performance and efficiency.
  
  

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a high impact Emulation Engineer to help bring our SiP based AI or ML engines to life through scalable, high performance emulation platforms. This role is ideal for someone who thrives on technical ownership, solves system level problems, and wants to influence silicon debug, DV, and performance from the ground up. You will build the infrastructure that allows our chiplet based systems to be explored, tested, and validated across hardware, software, and architectural layers.

This role is remote, based in Munich, Germany.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Bring 10+ years of SoC or ASIC experience, including a deep understanding of logic design, verification, and emulation platforms.
• Fluent in Verilog or SystemVerilog, C or C++, and SystemC, with hands-on experience using commercial emulators such as ZeBu, Palladium, or Veloce.
• Confident in architecting DV and emulation environments, from transactors to monitors to debug hooks, and automate everything you can.
• Collaborative and self driven, with a passion for mentoring junior engineers and working cross functionally with architecture, software, and DV teams.

What We Need

• A passion to build and scale a multi chiplet emulation ecosystem that supports DV, software development, and power or performance debug.
• Comfort in developing testbenches, transactors, monitors, and support systems to enable high quality, high efficiency emulation usage.
• Experience in driving emulation coverage from functional and performance to low level software enablement, and automate as much of the flow as possible.
• To optimize the platform for frequency, resource sharing, and end user support, ensuring Tenstorrent teams get the most from emulation.

What You Will Learn

• Building an emulation flow that supports chiplet based SiPs at scale, spanning AI workloads, interconnects, and system level power.
• How Tenstorrent integrates AI engines, RISC V CPUs, die to die links, PCIe, UCIe, and memory controllers into one unified platform.
• To align virtual prototyping, power analysis, and emulation into a full stack validation solution.
• How emulation sits at the core of a cross functional silicon bring up strategy, from RTL to post silicon debug and customer delivery.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a driven Engineering Program Manager—or a hands-on technical lead ready to step into program management—to help lead the charge on our RISC-V CPU team. In this role, you’ll be at the center of the action, working across architecture, design, verification, physical design, and DFT to drive the full lifecycle of a high-performance CPU—from spec to tapeout to post-silicon debug. You’ll partner with key stakeholders to define bold objectives, lock in milestones, and align the resources needed to bring next-gen compute to life.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A technically strong leader with experience in CPU, SoC, or silicon development.
• Skilled in aligning cross-functional teams to deliver complex, high-performance hardware programs.
• Proactive problem solver who thrives in dynamic, fast-paced environments.
• A clear communicator who can engage engineers and executives alike.

What We Need

• Ownership of full-cycle CPU program management—from spec to tapeout and post-silicon debug.
• Ability to define scope, schedule, and resources, and lead execution across architecture, design, verification, and DFT teams.
• Proven experience driving silicon development, managing risk, and delivering milestones.
• Experience with Functional Safety (FuSa) standards and implementation, especially ISO 26262 and an understanding of automotive industry requirements and standards for hardware development is highly desirable.

What You Will Learn

• How to lead the delivery of cutting-edge RISC-V CPU IP at scale, both internally and for external customers.
• Partnering with top engineers to resolve real-time design challenges, drive schedule trade-offs, and push forward high-impact decisions.
• Leading project reviews and reporting to senior leadership on metrics, risks, and mitigation plans.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Curious about how cutting-edge hardware actually comes to life? We're looking for someone who’s excited to dive into the core of next-gen systems and help make them real. In this role, you’ll validate high-speed interfaces, solve complex system-level puzzles, and collaborate across teams to shape the future of AI/ML computing. If firmware, hardware, and hands-on debugging sound like your kind of fun — let’s chat!

This role is hybrid and based in Vancouver, Canada. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You love bringing hardware to life and enjoy the thrill of solving tricky problems across the hardware–firmware boundary.
• You’re hands-on in the lab and comfortable with tools like oscilloscopes, protocol analyzers, and JTAG — digging deep doesn’t scare you.
• You’re comfortable jumping into unfamiliar problems and figuring things out — whether it’s in the lab or in firmware.
• You’re curious, collaborative, and excited to work on technology that pushes the boundaries of performance.

What We Need

• Someone to take the lead in validating our next-gen PCIe interfaces — from controller to PHY, and everything in between.
• A strong collaborator who can work across hardware, firmware, and software teams to bring up new features and solve problems.
• A sharp debugger who’s comfortable triaging issues across hardware, firmware, and software layers.
• A detail-oriented thinker who thrives in fast-paced environments and enjoys seeing ideas come to life in real systems.

What You Will Learn

• How to work at the cutting edge of compute — validating next-gen hardware and making it production-ready.
  How different pieces of a system come together — from multi-die chiplets to firmware integration and beyond.
  How to use advanced tools and techniques to debug and tune complex system interactions.
  How to shape emerging technology in a collaborative, fast-moving engineering environment.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Experienced Technical Recruiter - Serbia

People are at the center of this mission. Building the right team is existential. As an Experienced Technical Recruiter, you will play a critical role in identifying the engineers who define where AI goes next and who gets to benefit from it. This is a high-visibility role serving as the recruiting lead and sole talent owner for a critical Tenstorrent site.

This is not about filling seats. It is about building the infrastructure of intelligence with intention, clarity, and reach.

Who You Are

• Technical Expert: 7+ years of experience hiring for deeply technical roles across AI, ML, systems, hardware, or infrastructure. You know how to skill up fast on complex new specs.
• Owner & Pilot: You think independently and take deep ownership. You don't wait for direction; you seek signal, act on insight, and aren't afraid to pilot new strategies to find talent.
• Strategist: You understand how to map a region and nurture passive talent. Sourcing is your primary lever, not an afterthought.
• Trusted Advisor: A thoughtful communicator with the presence to influence stakeholders and maintain a high hiring bar while driving decisions.
• Principled: Grounded in the belief that who we hire shapes what we build. You have excellent judgment and can be trusted to negotiate fairly and handle compensation issues with nuance.

What We Need

• Site Ownership: Full-cycle ownership of critical searches across our Belgrade engineering and operations teams.
• Proactive Sourcing: Identifying talent beyond obvious pools and engaging passive candidates with authenticity.
• Influence & Partnership: Close collaboration with hiring managers to define roles, prioritize needs, and hold the line on quality.
• Operational Excellence: High-quality screening and candidate experience from first outreach to final offer.
• Data Integrity: Proactive communication with management and a commitment to data accuracy. "Not great with data" is not an option here; you will maintain the required reporting and use data to drive your engine.
• Independent Execution: The ability to align quickly with our vision and mission, making sound decisions on the fly.

What You Will Learn

• How to hire for one of the most ambitious technical missions in AI today.
• What world-class talent looks like across disciplines and how to recognize it early.
• How hiring choices shape organizational capabilities, long-term leverage, and company trajectory.
• How to balance urgency with care, and growth with focus, in a rapidly evolving space.
• How to build a talent engine that ensures AI is more open, inclusive, and broadly beneficial.

At Tenstorrent, we’re building cutting-edge hardware and software solutions that power AI, HPC, and general-purpose workloads. As a Performance Architect on our Platform Architecture team, you’ll work across ML software stacks, compilers, CPU design, cache coherency protocols, and interconnect fabrics to shape the future of high-performance systems. This role is all about bridging software execution and silicon design—making data-driven decisions that directly influence our SoC performance.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Passionate about solving complex system-level performance problems.
• Comfortable working across hardware and software boundaries.
• Analytical and data-driven, with a talent for turning workloads into architectural insights.
• Collaborative, thriving in cross-functional teams spanning compilers, CPU, and interconnect.
• Excited to shape the future of AI/HPC platforms through performance architecture.

What We Need

• BS/MS/PhD in EE, ECE, CE, or CS
• Deep understanding of NoC topologies, routing algorithms, QoS, and traffic scheduling.
• Expertise in cache coherency protocols (AMBA CHI/AXI) and modern memory/IO technologies (DDR, LPDDR, GDDR, PCIe, CCIX, CXL).
• Proficiency in C/C++ programming, with experience in building efficient performance models.
• Familiarity with ML/AI traffic patterns or formal verification of cache coherence protocols is a strong plus.

What You Will Learn

• How real ML/AI traffic patterns influence SoC interconnect and cache design.
• The art of balancing performance vs. complexity in coherence and memory hierarchies.
• How performance models feed into CPU and accelerator microarchitecture decisions.
• Best practices for correlating pre-silicon and post-silicon performance.
• Cutting-edge approaches to integrating heterogeneous compute systems at scale.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

As a pivotal member of our European expansion and a key bridge between our customers and engineering teams, you'll be at the forefront of deploying Tenstorrent's AI solutions across the EMEA region. This is a unique customer-facing technical role that combines systems engineering expertise across hardware, software, and firmware with customer success leadership. You'll serve as the trusted technical advisor to our enterprise customers throughout Europe, Middle East, and Africa, helping them successfully deploy and optimize Tenstorrent Galaxy servers and AI infrastructure.

This role is remote, based out of Munich, Germany. with regular travel throughout the EMEA region (30-40%) to support customer deployments and regional team collaboration.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned systems engineer with 8+ years across hardware, software, and firmware in HPC, AI, or high-performance computing environments.
• Customer-focused technologist who can translate complex technical concepts into business value and build trusted relationships with enterprise customers.
• Skilled at system-level problem solving—comfortable debugging issues across the full stack from silicon to application layer.
• Strong technical communicator who can present solutions to both engineering teams and customer executives.
• Comfortable with regular travel (30-40%) across Germany, Europe, Middle East, and Africa.
• German and English fluency required; additional European languages a strong plus.

What We Need

• Serve as the primary technical point of contact for enterprise EMEA customers, leading deployments, integrations, performance tuning, and troubleshooting.
• Build and maintain strategic relationships with key European customers, delivering trainings and workshops on Tenstorrent architecture, system integration, and best practices.
• Own technical execution for Galaxy server deployments from PoC through production, including system architecture (memory, storage, networking, clusters) and complex system-level debug.
• Collaborate closely with global Systems Engineering, Sales, Product, and Customer Success teams to resolve issues, improve product quality, and support business growth in EMEA.
• Act as the voice of the customer by translating feedback into engineering improvements, influencing roadmap and feature priorities, and mentoring junior engineers as the EMEA CS organization scales.

What You Will Learn

• End-to-end experience supporting enterprise AI deployments from proof-of-concept through production at scale
• Deep understanding of Tenstorrent's AI accelerator architecture and how to optimize systems for diverse customer workloads
• How to balance technical depth with customer relationship management in a fast-growing startup environment
• European AI market dynamics: automotive AI, research institutions, sovereign AI initiatives, and enterprise adoption patterns
• Cross-cultural business practices and technical collaboration across diverse European and Middle Eastern markets
• How to build and scale a regional Customer Success organization from the ground up
• Advanced system integration techniques for AI data center infrastructure

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is leading the industry on state of art AI technology, having developed high performance RISC V CPUs from scratch and fostering a deep passion for building the best AI platforms. We are now extending this philosophy to our Open Chiplet Atlas initiative, an open ecosystem built to connect diverse partners around a shared architecture. This role sits at the front line of that effort, driving real adoption with customers and partners.

This role is remote, based out of Munich, Germany.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Comfortable operating at the intersection of technology, ecosystem partners, and business strategy.
• A strong communicator who ensures alignment across technical, business, and partner teams.
• Proactive, adaptable, and capable of thriving in the ambiguity of building a new ecosystem.
• Driven by impact and motivated to shape the future of chiplet based computing platforms.

What We Need

• Bachelor’s degree in a technical field, for example, Engineering or Computer Science, or equivalent practical experience demonstrating deep technical understanding. An MBA is a strong plus.
• 5+ years of experience in technical marketing, technical support, and customer engagement within the semiconductor industry.
• Good understanding of chiplet or SoC architecture, silicon design flows, and system level tradeoffs.
• Experience with HDLs (Verilog/VHDL), industry standard ASIC SoC design tools and flows, familiarity with chip packaging technologies, and chiplets is a plus
• Familiarity with the semiconductor industry, including industry standards bodies, for example, PCI SIG or CXL Consortium, or interconnect protocols, for example, UCIe or AMBA. Experience working with open source hardware projects is a plus.
• Exceptional communication and presentation skills, with the ability to influence both technical and executive audiences.

What You Will Learn

• How an open chiplet ecosystem integrates diverse IP, designs, and software from multiple partners.
• The strategic balance of market requirements, partner needs, and technical tradeoffs, including performance, cost, and interoperability, for an open standard.
• Best practices for launching, managing, and scaling an industry wide compliance and certification program.
• Insights into emerging business models and technologies in heterogeneous computing and open hardware.
• How to build consensus and drive adoption across a diverse, global community of partners and customers.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will own end-to-end technical engagements, translating complex architectural advantages into customer wins while shaping our product roadmap through direct market feedback. If you combine deep technical expertise with exceptional customer engagement skills and want to drive the adoption of next-generation compute IP, join our team.

This role is hybrid, based out of the United States or Canada near one of our main office locations.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with proven success in CPU/GPU/NPU IP sales engagements.
• Technical expert who can articulate complex architectural benefits and conduct deep-dive analyses.
• Self-driven professional who independently manages multiple customer relationships from discovery to win.
• Strategic thinker who identifies customer pain points and positions solutions effectively.

What We Need

• 7+ years in the semiconductor industry with a degree in EE or related field including customer-facing roles in CPU IP.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Deep technical knowledge of CPU architectures, semiconductor technologies, and system-level design.
• Exceptional presentation and communication skills with ability to engage all organizational levels.
• Proven track record of technical wins and managing multiple simultaneous accounts.

What You Will Learn

• How to position cutting-edge RISC-V and AI accelerator IP against industry incumbents.
• Advanced customer engagement strategies for complex technical sales in the semiconductor industry.
• Direct influence on product development through customer feedback and market insights.
• The complete IP business cycle from evaluation through design win and production success.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The Mixed Signal IC Layout Design Engineer role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs.

This role is remote, based out of anywhere in the United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).
• Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).
• Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon and a strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.
• Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with circuit designers; typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.

What we need

• Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.
• Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.
• Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.
• Support post-layout extraction and simulation and, as a bonus, contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.

What you will learn

• Deep, hands-on experience with cutting-edge FinFET technologies (down to 2nm) and the nuances of mixed-signal layout at these nodes.
• How to integrate high-speed analog/mixed-signal IP into a complex D2D PHY, including interactions across digital, analog, and I/O domains.
• Advanced approaches for managing EM/IR, ESD, latch-up, and physical-verification closure in dense mixed-signal environments.
• How to influence and evolve layout flows, methodologies, and automation, shaping how the broader team delivers high-quality silicon.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we are creating state‑of‑the‑art compute solutions that push the boundaries of AI and high‑performance computing, and this role is central to that mission. As the Munich site lead, you will guide program planning and execution for major silicon and platform initiatives while serving as the key bridge between Germany‑based engineering efforts and Tenstorrent’s global priorities. You will help establish and grow Munich as a high‑impact innovation hub, shaping its technical direction, strengthening cross‑regional collaboration, and driving the execution needed to advance Tenstorrent’s next generation of compute technology.

This role is remote, based in Munich, Germany.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in end to end program management across hardware and software teams.
• Comfortable driving schedules, dependencies, and risk for complex silicon and system programs.
• Strong in technical communication with engineers, leaders, customers, and vendors.
• At ease leading cross functional teams through ambiguity to clear, measurable outcomes.

What We Need

• Ownership of program planning and execution for key silicon and platform initiatives.
• Structure for tracking milestones, managing dependencies, and surfacing risks early.
• Coordination across engineering, operations, sites, and external partners to keep work aligned.
• Clear communication of status, tradeoffs, and decisions to leadership and stakeholders.
• A site lead who can build and grow the Munich engineering presence, coordinate with global leadership, and ensure alignment on technical priorities.
• A partner who can represent Tenstorrent in the local ecosystem in Germany, supporting collaborations, recruiting, and customer engagements as needed.

What You Will Learn

• How Tenstorrent builds state of art RISC V and AI systems from concept to production.
• How to scale program execution across multiple geographies, vendors, and product lines.
• How to connect roadmap, resourcing, and execution for high stakes customer programs.
• How open hardware and software shape our product strategy and partner ecosystem.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a Layout Engineer with expertise in board layout for high-performance computing and  AI hardware. This role requires direct experience with multi-layer boards, HDI vias, blind vias, back drilling, DFM, DFA and routing / layout of interfaces like GDDR, LPDDR, DDR, PCIe Gen 5 & 6, Ethernet IEEE 802.3bj, cd, cf, USB, etc. The ideal candidate will work closely with cross-functional teams consisting of engineers from systems, power, signal integrity and mechanical to ensure that our products meet the layout margins and cutting-edge specifications for mass production boards for data centers, workstations, and consumer computing applications.

This role is hybrid, based out of Toronto, ON or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• Experienced board layout engineer with ~8+ years in PCB design (Cadence Allegro; Altium a plus).
• Hold a B.S. in EE, CS, or equivalent experience.
• Strong background in high-speed, complex PCBs (high layer count, HDI, multi-lamination, VIPPO, back drilling).
• Comfortable defining and applying layout rules (physical, spacing, length-matching) for high-speed designs.
• Confident working with fabricators on stackups, capabilities, and resolving DFM/DFA/DFT feedback.
• Detail-oriented owner of designs with strong communication skills and the ability to work with an international, cross-functional team.

What we need

• A Layout Engineer to own multi-layer PCB layouts for high-performance computing and AI hardware.
• Expertise routing GDDR, LPDDR, DDR, PCIe Gen 5/6, Ethernet (IEEE 802.3bj/cd/cf), USB and other high-speed interfaces.
• Proficiency with Cadence schematic/layout tools (v25.1) in the Cadence Pulse environment.
• Ability to choose appropriate advanced fabrication technologies (HDI, blind/buried vias, VIPPO, back drilling) balancing performance and cost.
• Skill in floorplanning, component placement, board connectivity, and creation of power/ground planes.
• Collaboration with power, signal integrity, and mechanical engineers to meet PDN, SI, mechanical, thermal, and regulatory (IPC, UL, CE, RoHS, FCC) requirements.

What you will learn

• How to design boards for cutting-edge AI and high-performance computing systems in data center, workstation, and consumer products.
• Techniques to optimize signal integrity, power delivery, and manufacturability for mass-production hardware.
• Best practices for working in a deeply cross-functional environment across systems, power, SI, and mechanical teams.
• Practical experience building around a from-scratch, high-performance RISC-V CPU and AI-first compute platform.
• How to navigate and integrate global industry and regulatory standards while pushing performance limits.
• The direct impact of your layout work on the roadmap and success of a fast-growing AI silicon and systems company.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced EDA/PDK CAD Engineer to build and maintain world-class design infrastructure that accelerates our silicon innovation. In this role, you'll install and optimize PDKs, manage EDA tool flows, and partner with analog, digital, and software teams to continuously improve design efficiency. If you're passionate about solving complex CAD challenges and enabling cutting-edge chip design, we want you on our team.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A self-driven problem solver with deep knowledge of PDKs, EDA tools, and IC design flows.
• Experienced in troubleshooting complex CAD issues and developing creative work-around solutions.
• Collaborative communicator who actively seeks feedback to improve team productivity.
• Passionate about challenging industry-leading tools and methodologies to drive continuous improvement.

What We Need

• BS, MS, or Ph.D. in Electrical Engineering and/or Computer Science with 5+ years of industry experience.
• Hands-on expertise installing, configuring, and maintaining PDKs and EDA environments.
• Strong background supporting physical verification flows (DRC, LVS, EM/IR, extraction) and mixed-signal simulation.
• Proven ability to work with vendors, foundries, and cross-functional teams to resolve technical issues.

What You Will Learn

• How to architect and scale design infrastructure for state-of-the-art AI silicon development.
• Advanced techniques for optimizing EDA flows across analog, digital, and mixed-signal domains.
• Direct collaboration with world-class engineers to shape tools and methodologies that define industry standards.
• Best practices for proactive CAD support and continuous flow improvement in a fast-paced innovation environment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The Tensix team is building the high-performance compute fabric that powers Tenstorrent’s AI and ML workloads. As an AI Performance Architect, you will model, analyze, and optimize how real AI workloads run on the Tensix architecture, shaping future hardware features and ensuring every design decision delivers measurable performance gains. This role connects architecture, software, and RTL to push the limits of efficiency and scalability across next-generation AI systems.

This role is hybrid, based out of Toronto, ON; Austin, TX; or remote.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deeply analytical engineer with strong intuition for AI workload behavior and system-level performance bottlenecks.
• Experienced in C++ and Python for simulation, modeling, and performance analysis across heterogeneous compute systems.
• Adept at bridging software and hardware teams—translating deep learning workloads into architectural insight and measurable design tradeoffs.
• Curious, data-driven, and comfortable pushing the limits of efficiency, scalability, and accuracy in high-performance AI systems.
  
  

What We Need

• Benchmark and analyze complex AI workloads across single and multi-node hardware configurations to guide next-gen architecture.
• Develop and maintain performance models, simulators, and micro-benchmark suites to drive feature evaluation and design optimization.
• Conduct detailed PPA (Performance, Power, Area) studies to assess design tradeoffs and inform hardware-software co-design decisions.
• Collaborate closely with RTL, Compiler, and Runtime teams to instrument and correlate performance models with silicon results.
  
  

What You’ll Learn

• Advanced modeling techniques for large-scale AI systems, including multi-chip and distributed performance analysis.
• How architectural choices propagate through the software stack—from compiler and runtime layers down to custom AI accelerators.
• Emerging deep learning trends and their impact on compute architecture design and performance tuning.
• How to define and validate performance features that directly translate to measurable gains across real-world AI workloads.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with industry-standard tools (FusionCompiler, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
• Experience driving physical design requirements from early architecture through final signoff.

What You Will Learn

• How to implement cutting-edge AI accelerators, high-performance CPUs and the SOCs that host them on the most advanced process nodes.
• Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
• End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
• Direct impact on products that are redefining the landscape of AI and high-performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking  a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures.

This role is remote role open to any location in the U.S.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts.
• Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off.
• Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity).
• Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs.
• A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues.

What We Need

• Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout.
• Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off.
• Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS.
• Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure.
• Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug).
• Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification.
• Bring a solid academic foundation: B.S./M.S. in EE/CE or related field.

What You’ll Learn

• How to implement and close cutting-edge D2D interfaces in advanced multi-die/chiplet architectures.
• Advanced strategies for co-optimizing routing, power grid, and timing for high-speed links across dies.
• Deeper integration techniques working with analog PHY teams, including model handoff (LEF/LIB) and constraint-driven interface design.
• How to drive repeatable, scalable PD methodologies for high-speed interfaces that can be leveraged across future chiplets and products.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
• Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability.
• Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST).

What we need

• Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC.
• Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.

What you will learn

• How to implement and close AI SoC partitions end-to-end, including power intent, timing, and physical signoff in a modern Synopsys-based flow.
• Deeper expertise across signoff domains: EM/IR, DRC/LVS, logical equivalence (LEC/Formality), and CDC-aware implementation on meaningful production blocks.
• Practical integration of analog/mixed-signal macros (PLL/DLL), DFT features (OCC/MBIST), and SoC interface IP within advanced physical design flows and collaborative tapeout environments.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes.

This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in STA and passionate about enabling silicon to meet aggressive performance goals.
• Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies.
• A collaborative team player who works well across logic, DFT, and physical design boundaries.
• Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows.

What We Need

• 7+ years of industry experience and a proven record of successful tapeouts.
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
• Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
• Familiarity with SPICE modeling and worst-case corner analysis.

What You Will Learn

• How to close timing on Tenstorrent’s high-performance RISC-V CPUs and AI SoCs.
• Advanced STA methodologies tailored to modern sub-micron process technologies.
• How to collaborate with world-class engineers across RTL, DFT, and physical design teams.
• How to influence chip performance through timing methodology innovation and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Our Tensix Team is building the next generation of high-performance AI compute systems. We’re looking for a Power Architect to drive architectural strategy, modeling, and design decisions that shape how power is understood and optimized across our products. This is a hands-on role with massive influence over how we build power-aware systems from the ground up.

This role is hybrid, based out of Toronto, ON or Austin, TX.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• 10+ years experience with power estimation tools like PowerArtist, PtPX, RTL Architect, and PrimePower.
• Skilled in modeling and optimizing power at the architectural level, with deep knowledge of power-gating, voltage domains, and leakage control.
• Track record of influencing architectural and micro-architectural changes that meaningfully reduced design power.
• Proficient in Verilog HDL, Design Compiler, C/C++ and Python.
• Background in power-optimization of compute datapath  and/or interconnects.

What We Need

• Predict power consumption early in architecture and track it through RTL evolution.
• Propose architectural changes for power optimization across server and non-server markets.
• Build workloads that stress real-world use cases and guide thermal and power-delivery solutions.
• Correlate pre-silicon estimates to silicon measurements and drive power efficiency improvements.

What You Will Learn

• How AI workloads impact power at every layer of the stack — from circuit to software.
• Challenges in building accurate, CI-integrated power modeling infrastructure.
• Techniques for aligning design tradeoffs to the realities of AI model execution.
• How Tenstorrent approaches full-stack power optimization across chiplet-based systems.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Are you passionate about scaling AI deployment through enhancing energy efficiency of RISC-V based CPUs and AI Data Centers? Would you like to be part of Open Chiplet Architecture to bring architectural flexibility tailored towards making our customers' experience great with low cost product solutions that are simpler, faster, and open? Are you an expert in Power Management and Optimization of SoCs and Chiplets? Do you enjoy working in a fast paced technical environment with multi-disciplinary teams of smart engineers to tackle the challenging energy efficiency of Data Center Products? At Tenstorrent, we own our Silicon future and provide a comprehensive solution through making our own IPs, Chiplets. Chips, Boards, and Systems. If you said yes to the above questions, we want to work with you.

This role is hybrid based out of Santa Clara, CA. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on expert in Power Management and SoC Power Architecture, with proven experience in data center power optimization.
• Skilled at debugging, experimentation, and root cause analysis, thriving in fast-paced, technically challenging environments.
• A strong collaborator and communicator, comfortable working with multidisciplinary teams across silicon, firmware, and systems.
• Passionate, optimistic, and driven to make bold contributions that push the boundaries of AI hardware.
• Committed to execution and impact — you enjoy doing, not just talking, and are motivated to leave your mark on the future of AI.

What We Need

• Deep expertise in Power Management, SoC Power Architecture, Power Delivery Networks, Thermal Analysis, and Performance Trade-offs
• Proficiency in Power Estimation Methodologies (e.g., using PTPX inputs) and trade-off modeling
• Experience with silicon PVT corners, process node trade-offs, binning, voltage droop mitigation techniques
• Ability to analyze AI and ML workloads for performance and efficiency
• Strong debugging skills and ability to design experiments to root cause issues
• Great interpersonal and collaboration skills to work with diverse engineering teams

What You Will Learn

• Hands-on experience working on the cutting edge of AI hardware design—from chiplets to full systems
• Exposure to Open Chiplet Architecture and the chance to contribute to industry-shaping standards like OCMI
• Opportunities to collaborate across Silicon, Firmware, and System teams, solving some of the most complex energy efficiency challenges in data centers
• A front-row seat to the scaling of AI through RISC-V–based solutions, shaping products that are simpler, faster, and more open
• The chance to leave your mark on the future of AI with a team that values bold ideas, fast execution, and long-term impact

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. This is a CPU tech-leadership role focused on driving power analysis and projections for the development of CPU chiplet with an emphasis on power analysis. The role involves defining CPUrail planning while collaborating closely with SoC and Board teams. Responsibilities include optimizing the system PDN for Block rails, and managing the power vector plan for comprehensive coverage of Chip level. The position requires driving power analysis on RTL and Netlist using tools like Joules and PrimePower, working with RTL design, synthesis, and physical design teams to measure and optimize power, and evaluating new power optimization techniques at various design stages. Additionally, the role involves tabulating metrics results for analysis comparison and workingwith post-silicon teams to correlate projections with silicon power measurements.

This role is hybrid, based out of Tokyo, Japan

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Extensive experience in power analysis and optimization for complex ASICs (typically 10+ years of ASIC or related design experience).
• Comfortable working across RTL, synthesis, and physical design stages, including low‑power implementation techniques and ECO‑based timing closure.
• Proficient with power analysis tools (e.g., Joules, PrimePower) and scripting (Tcl plus at least one of Python or similar).
• Strong analytical and problem‑solving skills, with clear written and verbal communication when collaborating across SoC, board, and post‑silicon teams.
• Nice to have: familiarity with UPF/CPF low‑power intent, Verilog/SystemVerilog, CPU micro‑architecture and its power challenges, and basic thermal analysis.

What We Need

• Own power analysis and projections for the CPU chiplet, with emphasis on defining and tracking power metrics throughout the design cycle.
• Define and maintain the power vector plan for comprehensive chiplet‑level and chip‑level coverage.
• Drive power analysis on RTL and netlist using tools such as Joules and PrimePower, partnering with RTL design, synthesis, and physical design teams to measure and optimize power.
• Evaluate and propose new power optimization techniques at RTL, synthesis, and physical design stages, and implement changes via timing ECO and flow updates.
• Tabulate and compare power metrics and reports across design iterations, and work with post‑silicon teams to correlate projections with silicon measurements.

What You Will Learn

• How to define and execute a power strategy for a 2nm CPU chiplet within a multi‑chiplet system‑in‑package, including rail planning and system‑level PDN optimization.
• Best practices for end‑to‑end power closure, from RTL through netlist and physical design, in collaboration with global RTL, SoC, and board teams.
• How to correlate pre‑silicon power models with real silicon behavior and feed lessons learned back into next‑generation CPU and SiP architectures.
• How Tenstorrent integrates CPU chiplets, AI accelerators, and board‑level power delivery into a cohesive high‑performance platform.

This is a 12 month contract position, with the possibility of a contract extension or conversion to a full time role based on performance and business needs. 

As a Recruiting Coordinator at Tenstorrent, you'll focus on making the candidate experience seamless and positive. This role is all about managing interview logistics, keeping communication clear, and supporting the recruiting team so everything runs smoothly and efficiently.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A highly organized multitasker who finds satisfaction in keeping things running smoothly.
• A clear, thoughtful communicator who keeps candidates and teammates informed and supported.
• Comfortable navigating G-Suite and applicant tracking systems like Greenhouse or Lever—or eager to learn quickly.
• Team-first, proactive, and energized by working in a fast-paced, collaborative environment.

What We Need

• Coordinate and schedule interviews—both virtual and in-person—with precision and attention to detail.
• Keep communication with candidates and hiring managers dialed in and timely.
• Maintain clean, organized candidate data in our applicant tracking system.
• Support team documentation, templates, and general admin tasks to keep everything running smoothly.

What You Will Learn

• What it takes to create a standout candidate experience from start to finish.
• How recruiting operations fuel a growing tech company—and how to scale them.
• Hands-on experience with tools and systems used by top recruiting teams.
• Ways to collaborate with recruiters, hiring managers, and interviewers to move fast without missing a beat.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a part of Tenstorrent’s Automotive and Robotics team, you will lead the definition of fully enabled software stacks for ADAS, IVI, and robotics domains across applications processors, microcontrollers and AI accelerators in advanced heterogenous edge computing environments.  You will be an industry leader in enabling wide adoption of the Risc-V architecture into these spaces. You will work across domains and across partners to define and coordinate how software will enable the next generation of open compute architectures.

This role is remote, based out of Munich, Germany.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You are an expert in software architecture for automotive and/or robotics.
• You understand software architecture, operating systems, hypervisors, middleware and applications.
• You understand heterogeneous compute architectures and how to enable them with full software support. 
• You are familiar with software development flows using for ISO26262, IEC61508 and ASPICE.  

What We Need

• Lead the definition and development of software stacks for chiplet-based SoCs in automotive ADAS and Infotainment as well as various robotics applications.
• 5+ years of experience working across multiple software development teams to coordinate efforts. 
• Work with customers and partners to align on a software strategy. 

What You Will Learn

• How to enable fully working software stacks in a multi-vendor environment.
• How to enable different automotive and robotics architectures and software stacks using the same silicon and base software enablement.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrentについて

Tenstorrentは、最先端のAIテクノロジーで業界をリードし、パフォーマンス、ユーザビリティ、コスト効率を再定義しています。当社のチームは、高性能なRISC-V CPUを一から構築しており、AIに対する深い情熱と、世界最高のAIプラットフォームを構築するという目的で団結しています。私たちは、コラボレーション、好奇心、そして困難な技術的問題を解決するという強いコミットメントを大切にしています。

募集ポジションについて

機械学習分野で学び、成長したいという意欲を持つエンジニアを募集しています。本ポジションでは、経験豊富なエンジニアと共に働きながら、当社独自のハードウェアプラットフォーム上でのMLモデルの開発・最適化を実践的に学ぶことができます。機械学習分野での業務経験は必須ではありません。必要な知識は入社後に習得していただけます。

必須要件

• C++およびPythonにおける強固なプログラミング基礎
• 機械学習およびAIに対する高い関心
• 学習意欲があり、困難な技術課題に挑戦できること
• 英語でグローバルチームとコミュニケーションが取れること

歓迎要件

• コンピュータサイエンス、工学、数学、物理学、または関連するSTEM分野の学士号以上
• 機械学習に関する基礎的な知識や経験（大学での履修、個人プロジェクト、研究など）

働き方

• Hybridで在宅勤務も、オフィス出社も可能です。
• 勤務時間も柔軟に対応しています

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

• Leadership to drive compiler development across multiple layers of the stack, including custom dialects, transformation passes, and runtime integration.
• Alignment with hardware, software, and ML teams to ensure the compiler supports realistic performance and deployment needs.
• Technical ownership of roadmap priorities, planning, and mentorship for a high-performing engineering team.
• Insight to identify bottlenecks, debug performance issues, and improve developer workflows across the stack.

• Experience building compilers or similar systems, with strong fluency in C++ and Python.
• Strong knoweledge of MLIR, LLVM, or related infrastructure, with hands-on work in dialect design or optimization passes.
• You have a strong understanding of modern AI frameworks like PyTorch, TensorFlow, or JAX, including how models are transformed and executed.
• A background in working across teams to ship reliable, scalable tools in fast-paced engineering environments.

• How to build compiler infrastructure that supports both training and inference at scale across custom chip architectures.
• New approaches for human-in-the-loop optimization using TT-Explorer and other internal tooling.
• Best practices for evolving MLIR dialects like TTIR, TTNN, and TTKernel to support next-generation AI workloads.
• How Tenstorrent delivers open, performant, and developer-friendly AI infrastructure that scales with industry demands.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Austin, TX, Fort Collins, CO or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is building next-generation AI hardware and software. This role focuses on the user-mode driver and interface layer that enables communication, resource management, and performance across our devices. You will play a key role in defining how our software stack interacts with both internal and third-party hardware.

This role is hybrid, based out of Belgrade, Serbia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deep systems engineer with 7+ years experience in user-mode drivers or low-level systems programming.
• Strong proficiency in C and C++ with solid understanding of hardware-software interfaces.
• Familiar with Linux kernel concepts and how kernel and user-space components interact.
• Experience working with external customers or partners to define and support driver or hardware interfaces.
• Exposure to safety-critical systems, automotive platforms, or Functional Safety standards such as ISO 26262 is a strong plus.

What We Need

• Design and evolve the user-mode driver layer that provides high-performance APIs for Tenstorrent devices.
• Define driver interfaces and specifications that enable the broader software stack to run across internal and third-party hardware.
• Collaborate with kernel and hardware teams to ensure efficient cross-layer design and performance.
• Drive performance engineering efforts, including benchmarking, profiling, and optimization of APIs.
• Support external integrations by defining hardware-software boundaries and enabling reliable deployment in customer environments, including safety-critical use cases where applicable.

What You Will Learn

• How user-mode and kernel-level drivers are designed for high-performance AI hardware.
• How hardware-software interfaces are defined to support scalable and portable systems.
• How performance is optimized across memory, compute, and communication layers.
• How third-party hardware integrations are enabled through well-defined driver and interface layers.
• How safety and reliability requirements influence modern driver architecture, including in automotive and mission-critical systems.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V–based SoCs. This role sits at the intersection of silicon, firmware, and system software, and requires hands-on lab experience and understanding of SoC architectures.

You will own post-silicon validation from first-silicon bring-up through production readiness, working closely with design, pre-silicon verification, firmware, and software teams.

This role is hybrid , based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You are a seasoned post-silicon engineer with 10+ years of experience in SoC bring-up, validation, and silicon debug.
• You have a strong grasp of CPU and SoC architectures, including RISC-V privilege modes, caches, coherency, and memory systems.
• You are comfortable debugging complex hardware/software interaction issues using lab tools and low-level software.
• You thrive in cross-functional environments and enjoy working closely with RTL, firmware, and software teams to solve hard problems.

What We Need

• Lead first-silicon bring-up of RISC-V CPU–based SoCs and execute post-silicon validation plans.
• Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals, and high-speed interfaces.
• Develop and debug bare-metal tests, boot flows, and collaborate on Linux bring-up and driver validation.
• Provide actionable feedback, support ECO validation, and drive fixes for future silicon revisions.

What You Will Learn

• Deep hands-on exposure to cutting-edge RISC-V SoCs, AI accelerators, and high-performance compute platforms.
• End-to-end ownership across the silicon lifecycle—from first silicon to stable production.
• Advanced silicon debug techniques spanning hardware, firmware, and operating systems.
• Opportunities to influence architecture, validation strategy, and future silicon direction in a highly visible role.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance-aware design.

This role is hybrid, based out of Toronto, Ottawa, Boston, or Austin. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.

What We Need

• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Strong synthesis and timing closure awareness to support backend teams.
• Prior experience in on-chip fabric and interconnect designs is an asset.

What You Will Learn

• How cutting-edge AI chips are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How to blend custom logic with standard SoC elements for power and scale.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Sr. Staff HR Business Partner, you are not an administrator - you are a high-level architect of organizational health. You will act as the primary strategic advisor to our executive leaders, sitting at the table as a core member of their leadership teams. You will be expected to challenge the status quo, drive radical accountability, and execute people strategies that enable fast, focused growth.

This role is hybrid, based out of Santa Clara, CA, Austin, TX, Boston, MA, or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You are a seasoned HRBP from the high-growth tech or AI space who influences senior technical leaders and excels at driving complex people projects to completion.
• You take personal responsibility for the health of your organizations. If there is a problem, you own the solution from start to finish.
• You skip the fluff. You are comfortable having difficult conversations and providing clear, actionable recommendations to executives.
• Someone who understands how a tech company operates. You make HR decisions based on what helps the company win, not just what is standard practice.
• Can move between high-level strategy and day-to-day execution without losing momentum. You thrive in environments that aren't yet fully defined.

What We Need

• Partner with leaders at all levels to align their team structures and talent plans with Tenstorrent’s product roadmap.
• Act as a candid sounding board for senior leaders, helping them build high-performing teams and navigate complex management challenges.
• Use organizational data and metrics to diagnose issues, identify trends, and provide evidence-based recommendations. You won't just report data; you will use it to tell a story and drive action.
• Act as the ultimate collaborator across the company. You will work seamlessly with Finance, Legal, Recruitment, and Compensation to ensure people initiatives are integrated and scalable.
• Lead the thinking on how our teams should evolve as we scale. You’ll identify gaps in the organization and propose structural changes to keep us moving fast.
• Take full responsibility for global programs, like performance and engagement surveys, ensuring they are executed with precision and fairness.
  
  

What You Will Learn 

• How to build and iterate on HR systems that don't just support but actually accelerate a rapidly scaling, product-first AI hardware company.
• How our commitment to open hardware and software translates into a unique, high-transparency talent strategy and leadership model.
• How to move beyond standard reporting to use real-time experimentation and feedback loops to pivot people strategies at the speed of our roadmap.
• How to maintain the art of enterprise-level influence while staying deeply embedded in the day-to-day execution and high-stakes decisions of our engineering teams.
• How to dismantle standard practices that don't work and replace them with lean, high-impact solutions that help the company win.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As part of Tenstorrent’s Automotive RTL team, you will help design and deliver the core hardware modules inside our next generation chiplet based SoC. This is a hands on role where your RTL will ship in silicon, powering real automotive systems under strict performance and safety constraints. If you are looking to build silicon that actually matters, not just compile, this is where you want to be.

This role is remote, based in Munich, Germany.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Design-first, spec-driven, and used to debugging silicon the hard way. 
• Know how to translate system requirements into clean, testable RTL. 
• Have experience writing and maintaining configurable, modular code. 
• Interested in building silicon that will run critical workloads in safety-sensitive environments. 
• Background with high-speed die-to-die interfaces preferred (UCIe, BoW, etc).

What We Need

• An engineer with 5+ years of experience to develop and own RTL for key modules in Tenstorrent’s automotive SoC chiplets. 
• Someone who can collaborate with IP vendors and internal teams to configure and integrate complex subsystems. 
• Detail-oriented in writing microarchitecture specs and translating them into clean, efficient RTL. 
• Passion to jump into chiplet-level integration, testing, and bring-up from day one.

What You Will Learn

• How automotive-grade RTL differs from consumer silicon and why it matters. 
• What it takes to bring up a custom chiplet in a real automotive use case. 
• Why chiplets demand more ownership and reward deeper engineering. 
• How cross-functional communication accelerates hardware development.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This role owns the technical strategy and architecture behind Tenstorrent’s core business applications, from ERP and CRM to the integrations that connect everything together. The focus is on building scalable, secure systems and integrations that hold up as the company grows, while providing hands-on technical leadership across SaaS, middleware, and custom services.

This role is hybrid, based out of Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Technical leader who enjoys owning architecture decisions and setting engineering standards.
• Comfortable moving between strategy and hands-on execution across enterprise systems.
• Naturally collaborative, able to guide teams and partners through complex integration work.
• Motivated by building systems that scale cleanly and stay reliable under change.

What We Need

• Ownership of development, customization, and technical oversight for core business applications and integrations.
• Leadership of middleware and integration architecture across ERP, CRM, SaaS platforms, APIs, and iPaaS solutions.
• Design and review of scalable, secure APIs, microservices, and cloud-based integration patterns.
• Proactive management of system performance, upgrades, risk mitigation, and long-term technical health.

What You Will Learn

• How a fast-growing technology company scales its enterprise application ecosystem end to end.
• How integration strategy shapes operational efficiency across finance, sales, and go-to-market systems.
• How to influence tooling, architecture, and standards across a diverse SaaS and cloud environment.
• How to balance speed, reliability, and security in a constantly evolving business systems landscape.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Santa Clara, CA or Austin, TX

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM.
• You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
• You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams.

What We Need

• Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
• Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

What You Will Learn

• How to drive DFT for industry-leading AI/ML architectures, working on high-performance chips with aggressive performance and power targets.
• Practical strategies to reduce test cost while maintaining coverage, and to design DFT hooks that accelerate silicon bring-up and yield learning.
• How to minimize DFT intrusions while integrating cleanly with RTL, verification, physical design, and production test flows.
• How a senior, cross-functional ASIC team collaborates across design, PD, verification, and manufacturing to achieve first-pass silicon success on advanced nodes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors. This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.
• Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).
• Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.
• Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

What We Need

• Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST).
• Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc).
• Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.
• Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness.
• Participate in ATE targeted test patterns, validation and silicon- debug
• Work closely with test and product engineering teams on silicon characterization and validation.

What You Will Learn

• Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies
• In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes
• Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success
• Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we build open, state of art compute for real workloads and real developers.

You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You bring 8+ years in CPU verification or closely related digital design.
• You know high‑performance out‑of‑order CPU microarchitecture in depth.
• You work comfortably with RTL, waveforms, logs, and complex debug scenarios.
• You communicate clearly across design, DV, emulation, and post‑silicon teams.

What We Need 

• Plan and drive functional verification for CPU core features and microarchitectural scenarios.
• Develop UVM, assembly, and C/C++ stimulus for ISA and microarchitectural coverage.
• Develop/debug C++ functional models of RISC-V extensions and un-core components such as APIC and IOMMU.
• Debug simulation and emulation regressions using waveforms, logs, and RTL understanding.
• Build and refine coverage models to track and close architectural and microarchitectural coverage.
• Improve core, cluster, and chip‑level testbenches and debug infrastructure.
• Support design bring‑up across simulation, emulation, and post‑silicon environments.
• Collaborate with design, test, and validation to deliver robust CPU cores and clusters.

What You Will Learn 

• How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.
• Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.
• Ways to scale coverage, debug, and infrastructure across multiple CPU programs.
• How open hardware and software fit into Tenstorrent’s broader compute roadmap.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking a highly skilled and independent Design Verification Engineer to join our RISC-V CPU team. In this role, you will be responsible for the block-level verification of high-performance Cache and Coherence units. You will lead the development of sophisticated UVM environments to ensure the quality and reliability of our next-generation IP solutions.

This role is hybrid, based out of Bangalore, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have strong hands-on experience with SystemVerilog and UVM and enjoy building verification environments from the ground up.
• You are comfortable driving complex DV efforts independently, from strategy definition to coverage closure.
• You have a solid understanding of RTL verification, debugging, and coverage analysis.
• You bring curiosity and strong problem-solving skills, with exposure to cache, interconnects, or memory systems being a plus.

What We Need

• Define comprehensive verification strategies and architect robust DV environments for block and sub-system level IPs.
• Develop reusable UVCs and execute constrained-random test plans to validate complex corner cases.
• Perform RTL-level functional verification, improve functional and code coverage, and debug complex failures.
• Collaborate closely with design and cross-functional teams to drive verification projects to completion.

What You Will Learn

• Deep hands-on exposure to cache pipelines, memory subsystems, and high-performance interconnects.
• Advanced verification techniques to improve efficiency, scalability, and reliability across IPs.
• Practical experience working with AXI/CHI protocols, cache coherence, and memory consistency models.
• End-to-end ownership of complex DV projects in a fast-paced, high-performance compute environment.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we build computers for AI, and the developers shaping its future.

Our high-performance RISC-V CPUs, modular chiplets, and scalable compute systems give developers full control at every layer of the stack, at any scale from a single-node experimentation to data center-scale deployment.

We believe in an open future. Our architecture and software are designed to be edited, forked, and owned. Our team of engineers, dreamers, and first-principle thinkers is redefining how hardware and software converge to accelerate innovation.

As part of a new organization focused on experience, we need engineers for our Developer Relations team that deeply understand developers’ trials , tribulations, and wins. You'll build, present, and contextualize the tools, demos, and interfaces developers need to navigate and fully utilize Tenstorrent hardware and software. You'll meet developers where they are, understand their needs, and partner with them to build an open future. 

This role is remote, but you're welcome to work from one of our offices if you're nearby. We encourage candidates of all experience levels to apply. Your interview will determine the best fit, and offers will reflect that assessment.

Who You Are

• Passionate tool builder. You're comfortable creating things developers love to use  like command-line utilities, SDKs, dashboards, service integrations, content management systems, and microsites. 
• Curious and explore how AI can augment and enhance your development capabilities. 
• Want to share that experience to empower today's and tomorrow's developers. 
• Believe that being open is a key advantage and wayfinder in how to act and what to do next.

What We Need

• A Bachelor's degree in Computer Science, Engineering, or a related field, or equivalent experience.
• A proven track record building great experiences for a developer audience.
• Strong skills across multiple parts of a developer’s stack.
• Fluency with open source development practices and tools, for example, Git, GitHub, CI, VSCode.
• Strong product instincts.
• Interest and experience working at varying levels of the AI engineering stack.

What You Will Learn

• Build web-based tools, demos, and playgrounds, letting developers explore our offerings.
• Translate complex platform capabilities into intuitive user and developer experiences. We improve the developer experience by reducing friction and improving education throughout.
• Partner closely with Marketing, Creative, Engineering, and Product to connect narrative with function.
• Advocate for seamless UX, from box to screen.
• The state-of-the-art in AI inside a growing, international community of open computing enthusiasts.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This role sits at the intersection of embedded systems, silicon validation, and advanced networking. You'll work with best-in-class IP from leading vendors and in-house designs, bringing up and validating these IPs in silicon, and building robust validation infrastructure that ensures performance, interoperability, and reliability at scale.

This role is hybrid, based out of Toronto, Canada, Vancouver Canada, Santa Clara, California or Austin, Texas.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Passionate about low-level software that brings hardware to life—seeing it run on real systems never gets old.
• Drawn to complex, cross-disciplinary problems at the intersection of hardware and software.
• Excited by high-speed networking challenges like SerDes tuning, link training, and Ethernet MAC/PHY.
• Have pride in hands-on debugging and working across teams to make systems fast, reliable, and ready for the real world.

What We Need

• A passion for breaking and fixing complex hardware-software systems.
• Comfort with designing tests that push things to their limits: functional, performance, integration—you name it.
• Experience in lab work—system bring-up, running experiments, and working with emulation tools.
• A love for writing firmware and scripts to automate testing, dig into issues, and keep things running smoothly.

What You Will Learn

• What it means to shape AI acceleration hardware from the ground up—starting at first principles.
• How to validate complex Ethernet IP from simulation all the way to production silicon.
• The mastery of collaborating with world-class silicon, systems, and software teams to tackle frontier engineering challenges.
• How to define the networking architecture that will power the next era of AI platforms.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As part of Tenstorrent’s Automotive Robotics team, you will help design and deliver the core hardware modules inside our next generation chiplet based SoCs for automotive products. You will be the bridge between silicon design, DFT, OSAT partners, and customers to ensure our multi die SiP platforms meet aggressive performance, quality, and safety targets.

This role is remote, based in Munich, Germany.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced with industry standard ATPG and DFx insertion CAD tools.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Able to translate system and safety requirements into concrete constraints on package architecture, DFT insertion, and support test engineering with planning, patterns, and debug.
• Comfortable working in a cross functional role that extends beyond DFT, including low power designs with multiple clock domains.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.

What We Need

• Define DFx strategy for multi chiplet packages from architecture through high volume production.
• 10+ years of experience working across multiple teams and multiple companies to coordinate test, yield, and quality efforts.
• Feed lessons learned back into next generation SiP architectures, DFT strategy, and test content.
• MBIST, LBIST, IST planning, implementation, and verification.
• JTAG, Scan Compression, and ASST implementation.
• ATPG and test coverage analysis using industry standard tools.

What You Will Learn

• How to bring a SiP to high volume, automotive grade production.
• How chiplets, RISC V CPUs, AI accelerators, and die to die links come together in a unified automotive platform.
• How to trade off package architecture, DFT, and test cost to hit aggressive performance, quality, and reliability targets.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an Physical Design Engineer to lead  cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. 

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes.
• Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs.
• Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows.
• Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independently.

What we need

• Lead and contribute to cross-functional efforts solving complex physical design challenges across IPs, projects, and advanced technology nodes.
• Develop and enhance RTL-to-GDS methodologies, including floorplanning, synthesis, P&R, STA, signoff, and assembly.
• Architect and deploy AI/ML-driven solutions in production flows to improve engineering efficiency, turnaround time, and QoR.
• Optimize EDA tools and custom CAD flows using data-driven and ML-based techniques, in close collaboration with verification, extraction, timing, DFT, and EDA vendors.

What you will learn

• How to scale AI/ML-driven methodologies across diverse products and advanced technology nodes in real production flows.
• New ways to blend classical EDA algorithms with modern ML techniques to push PPA and runtime limits.
• Best practices for deploying, validating, and monitoring ML models in production CAD environments.
• How to influence next-generation ML-enabled EDA tools and collaborate deeply with cross-functional teams (PV, extraction, timing, DFT).

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is seeking an AI Performance Simulation Architect to help shape the future of our AI computing.  In this role, you’ll architect and build scalable cycle-accurate AI accelerator performance models that can run representative AI workloads.  Your work will directly inform how we design and optimize future hardware platforms, from high-level performance models to cycle-accurate simulations.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You’re a senior technical leader with deep experience in AI accelerator architecture and micro-architecture, performance simulation, and system-level modeling.
• You’re comfortable switching between abstraction layers—from C++ performance models to software frameworks and system requirements.
• You have a strong grasp of AI workloads and how to distill them into inputs for performance models.
• You understand how system design affects the performance and scalability of AI workloads.
• You collaborate well across hardware, software, and research domains—and enjoy mentoring others along the way.

What We Need

• Architect and develop simulation environments for AI systems—spanning accelerators, NoCs, and memory hierarchies.
• Define and implement abstraction layers, from high-level analytical models to detailed simulations using tools like GEM5 or SST.
• Lead performance modeling and bottleneck analysis to guide architectural design and system optimization.
• Lead integration of the AI accelerator performance model into a larger heterogeneous simulation modeling environment to examine system performance.
• Deep experience with parallel programming (OpenMP, MPI, CUDA, OpenCL) and system analysis tools.

What You Will Learn

• How Tenstorrent is building next-gen AI infrastructure at datacenter scale.
• How to influence silicon and system-level decisions using simulation-driven insights.
• How to collaborate with vendors and technology partners to assess emerging processors, accelerators, and interconnects.
• How to bridge simulation and deployment by working across hardware, dev tools, software stacks, and customer use cases.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is accelerating the future of AI and high-performance compute by building industry-leading CPU and AI architectures. As an Automotive and Robotics SoC Architect, you will define scalable, top-down system architectures that unify our CPU and AI technologies for next-generation automotive applications. This senior technical role shapes the architectural direction of our automotive and robotics portfolio, ensuring our products meet the industry's highest expectations for performance, safety, reliability, and security. This position is central to how Tenstorrent delivers world-class automotive solutions and requires strong technical leadership, systems thinking, and cross-functional collaboration.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A systems thinker who can architect complex SoCs from concept to execution.
• A strong communicator who can articulate technical direction across engineering teams and external partners.
• Someone with deep knowledge of safety-critical systems and the unique needs of automotive environments.
• An innovator who can identify future use cases and propose next-generation architectural solutions.
• A leader who thrives in a highly technical, cross-functional, fast-moving environment.

What We Need

• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or related field.
• Extensive experience designing complex SoCs, ideally in automotive applications.
• Proficiency in hardware description languages such as Verilog or VHDL.
• Experience with hardware/software co-design and co-verification.
• Knowledge of automotive safety standards (e.g., ISO 26262) and security principles.
• Someone comfortable with up to 25% international travel. 
• Experience with both cameras, sensors, and others is a plus.

What You Will Learn

• How cutting-edge CPU and AI architectures are adapted for automotive-grade environments.
• Best-in-class methodologies for safety-critical SoC design, verification, and system integration.
• How to translate emerging automotive use cases into scalable, future-proof SoC architectures.
• Approaches to hardware-level security, robustness, and cyber-resilience in automotive compute systems.
• Cross-functional collaboration strategies that drive innovation across architecture, software, DV, and product teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The BD Lead will support the amplification of this sovereign AI strategy by identifying opportunities, managing client relationships, and supporting go-to-market execution across the India. Reporting to the BD Lead for GCC region, this position will work closely with both regional leadership and global counterparts to build an Open Future.

This role is hybrid, based out of Bengaluru, IN.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Passionate about sovereign AI solutions and open source software.
• Commercially minded with strong business development and client engagement skills.
• Thrive in fast-paced, high-growth environments and can balance strategic thinking with hands-on execution.
• A confident communicator, able to engage and collaborate effectively with senior stakeholders, partners, and customers.
• Results-oriented, organized, and capable of managing multiple opportunities simultaneously.

What We Need

• Experience in the AI hardware or software market, with an understanding of ecosystem dynamics and emerging trends, including enterprise, government, and strategic partner landscapes.
• Strong relationships with India-based clients, system integrators (SIs), and independent software vendors (ISVs) 
• Proven track record in pipeline development, client relationship management, and closing commercial opportunities.
• Experience working with cross-border teams and managing multi-stakeholder initiatives.
• Fluency in English is required. Proficiency in Arabic is highly preferred.

What You Will Learn

• To throw out the old playbook and drive strategic growth in the rapidly evolving AI hardware and software ecosystem.
• Go-to-market strategies across India from start to finish
• Negotiating strategic partnerships with enterprises, governments, and ecosystem partners.
• Building a regional network while collaborating with global BD, product, and technical teams.
• Deeper expertise in market analysis, sales operations, and deal execution.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You’ll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced physical design engineer who thrives in complex, multi-stakeholder projects.
• Detail-driven, with a strong sense of ownership from synthesis through design closure.
• Comfortable working at advanced nodes (3nm and below) and multi-GHz designs.
• A collaborative team player who enjoys mentoring others and influencing methodology.
• Clear communicator who can balance technical depth with schedule and resource constraints.

What We Need

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of industry experience in physical design for CPU, or GPU products.
• Strong hands-on experience with Synopsys and/or Cadence tools across synthesis, P&R, and closure.
• Proven expertise in timing closure, ECO flows, and PV convergence at block and chip level.
• Proficiency in scripting (TCL required; Python or similar strongly preferred) and strong English communication skills.

What You Will Learn

• How large-scale chiplet-based systems are architected, implemented, and integrated into SiP solutions.
• Best practices for achieving timing and power convergence on advanced silicon technologies.
• How physical design decisions impact system-level performance and scalability.
• Effective collaboration across global teams and external partners.
• How Tenstorrent evolves and standardizes physical design methodologies across projects.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a C++ Machine Learning Engineer on the AI Models team at Tenstorrent, you’ll work on the training framework behind our most advanced models. You’ll write high-performance C++ code, shape how new layers and operators are implemented, and help models scale across our custom silicon. If you enjoy building the guts of ML systems and seeing them run fast, this role is for you.

This role is hybrid, based out of Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong in C++ and low-level systems programming, especially in performance-critical code.
• Comfortable thinking in tensors, memory layout, and compiler graphs.
• Familiar with PyTorch and curious about how frameworks map to hardware.
• A builder who enjoys solving technical puzzles and digging into the details.

What We Need

• Extend and optimize our ML training framework with new ops, layers, and training features.
• Debug and tune model performance on Tenstorrent chips.
• Work with compiler and kernel teams to make sure models compile and run as expected.
• Support integration of real-world models and help bring them into production.

What You Will Learn

• How ML frameworks and compilers connect at the system level.
• How to translate training workloads into low-level operations optimized for custom silicon.
• How large-scale model training works under the hood, from memory layout to operator fusion.
• What it takes to build infrastructure that supports fast iteration in research and production.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.