The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Implementation of DFT features into RTL using verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in finFET technologies.
• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

The BD Lead will support the amplification of this sovereign AI strategy by identifying opportunities, managing client relationships, and supporting go-to-market execution across the India. Reporting to the BD Lead for GCC region, this position will work closely with both regional leadership and global counterparts to build an Open Future.

This role is hybrid, based out of Bengaluru, IN.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Passionate about sovereign AI solutions and open source software.
• Commercially minded with strong business development and client engagement skills.
• Thrive in fast-paced, high-growth environments and can balance strategic thinking with hands-on execution.
• A confident communicator, able to engage and collaborate effectively with senior stakeholders, partners, and customers.
• Results-oriented, organized, and capable of managing multiple opportunities simultaneously.

What We Need

• Experience in the AI hardware or software market, with an understanding of ecosystem dynamics and emerging trends, including enterprise, government, and strategic partner landscapes.
• Strong relationships with India-based clients, system integrators (SIs), and independent software vendors (ISVs) 
• Proven track record in pipeline development, client relationship management, and closing commercial opportunities.
• Experience working with cross-border teams and managing multi-stakeholder initiatives.
• Fluency in English is required. Proficiency in Arabic is highly preferred.

What You Will Learn

• To throw out the old playbook and drive strategic growth in the rapidly evolving AI hardware and software ecosystem.
• Go-to-market strategies across India from start to finish
• Negotiating strategic partnerships with enterprises, governments, and ecosystem partners.
• Building a regional network while collaborating with global BD, product, and technical teams.
• Deeper expertise in market analysis, sales operations, and deal execution.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We're looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You thrive in building robust verification environments using SystemVerilog, UVM and C++, and can define and drive verification plans independently.
• You bring a system-level mindset, with experience integrating multiple IPs into clusters or SoCs and verifying their interactions.
• You have a strong grasp of stimulus planning, debug techniques, and coverage closure for verifying complex hardware subsystems like caches, NoCs, and memory hierarchies.
• You’re comfortable working on features that span multiple IPs — such as coherence, security — and ensuring their correct behavior at the cluster or SoC level.

What We Need

• A Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• Strong experience with System Verilog and UVM-based verification.
• Proven ability to drive subsystem or SoC-level DV projects with integration and system feature validation responsibilities.
• Familiarity with AXI/CHI protocols, System IPs flows (like debug/trace, power management), and integration flows for multi-IP verification environments.

What You Will Learn

• Techniques to scale DV infrastructure for verifying high-performance RISC-V clusters and SoCs.
• How to verify multi-agent interactions across CPUs, system IPs and NoC or fabric components.
• Best practices for cross-IP feature convergence, integration-level planning, and reuse across cluster/SOC programs.
• How to collaborate with global teams across RTL, DV, software, and validation for cohesive system-level bring-up.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking a highly skilled and independent Design Verification Engineer to join our RISC-V CPU team. In this role, you will be responsible for the block-level verification of high-performance Cache and Coherence units. You will lead the development of sophisticated UVM environments to ensure the quality and reliability of our next-generation IP solutions.

This role is hybrid, based out of Bangalore, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have strong hands-on experience with SystemVerilog and UVM and enjoy building verification environments from the ground up.
• You are comfortable driving complex DV efforts independently, from strategy definition to coverage closure.
• You have a solid understanding of RTL verification, debugging, and coverage analysis.
• You bring curiosity and strong problem-solving skills, with exposure to cache, interconnects, or memory systems being a plus.

What We Need

• Define comprehensive verification strategies and architect robust DV environments for block and sub-system level IPs.
• Develop reusable UVCs and execute constrained-random test plans to validate complex corner cases.
• Perform RTL-level functional verification, improve functional and code coverage, and debug complex failures.
• Collaborate closely with design and cross-functional teams to drive verification projects to completion.

What You Will Learn

• Deep hands-on exposure to cache pipelines, memory subsystems, and high-performance interconnects.
• Advanced verification techniques to improve efficiency, scalability, and reliability across IPs.
• Practical experience working with AXI/CHI protocols, cache coherence, and memory consistency models.
• End-to-end ownership of complex DV projects in a fast-paced, high-performance compute environment.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking an exceptional and highly motivated leader to take on a dual role, serving as both the System IP Leader for our global product lines and the India Site Lead for our growing engineering design center. This critical position requires a blend of deep technical expertise in complex System IP development, strategic business acumen, and proven experience in managing and growing a high-performing site/office.

The successful candidate will drive the technical direction and execution of our flagship IP portfolio while simultaneously being responsible for the operational success, cultural health, and strategic growth of our entire India office. This role demands a leader who can operate effectively at both a highly granular technical level and a broad organizational level, acting as the primary representative for Tenstorrent’s executive leadership in India.

This role is on-site, based out of Bangalore, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You are a seasoned semiconductor professional with over 15 years of experience specializing in SoC architecture and System IP development.
• You are an expert in high-speed interconnects, memory subsystems, and security implementations for next-generation products.
• You are a proven technical leader with more than 5 years of experience managing large-scale cross-functional engineering teams through complex delivery cycles.
• You are an experienced site leader with a strong track record of partnering with global operations and driving strategic growth for the engineering center in India.
• You are a strategic communicator capable of bridging the gap between local technical execution and global executive leadership.
• You are a dedicated mentor focused on fostering high-performance cultures and driving career growth within multi-national organizations.

What We Need 

• You will define and execute a long-term technical roadmap for System IP that ensures optimal performance, power, and area.
• You will oversee the end-to-end delivery of high-quality IP components while enforcing best practices for documentation and reusability.
• You will implement rigorous verification methodologies to ensure first-pass silicon success across all system-level integrations.
• You will drive the strategic expansion of the India site by aligning local talent acquisition with global business objectives.
• You will manage site operations and budgets to maintain a collaborative and compliant environment for all functional groups.
• You will act as the primary liaison between the India office and global leadership to advocate for local capabilities and needs.

What You Will Learn 

• You will master the specific architectural requirements and proprietary workflows used in your next-generation product lines.
• You will identify the unique cultural strengths of the current India team to further enhance local employee engagement.
• You will adapt your leadership style to the organization's specific internal processes for cross-functional synergy and resource allocation.
• You will gain deeper exposure to the specific implementation of advanced process nodes and emerging chiplet technologies.
• You will learn the nuances of the global vendor relationships to better manage external IP integrations.
• You will explore new ways to expand functional ownership within the India site to maximize its contribution to the global roadmap.

We are looking for a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V–based SoCs. This role sits at the intersection of silicon, firmware, and system software, and requires hands-on lab experience and understanding of SoC architectures.

You will own post-silicon validation from first-silicon bring-up through production readiness, working closely with design, pre-silicon verification, firmware, and software teams.

This role is hybrid , based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You are a seasoned post-silicon engineer with 10+ years of experience in SoC bring-up, validation, and silicon debug.
• You have a strong grasp of CPU and SoC architectures, including RISC-V privilege modes, caches, coherency, and memory systems.
• You are comfortable debugging complex hardware/software interaction issues using lab tools and low-level software.
• You thrive in cross-functional environments and enjoy working closely with RTL, firmware, and software teams to solve hard problems.

What We Need

• Lead first-silicon bring-up of RISC-V CPU–based SoCs and execute post-silicon validation plans.
• Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals, and high-speed interfaces.
• Develop and debug bare-metal tests, boot flows, and collaborate on Linux bring-up and driver validation.
• Provide actionable feedback, support ECO validation, and drive fixes for future silicon revisions.

What You Will Learn

• Deep hands-on exposure to cutting-edge RISC-V SoCs, AI accelerators, and high-performance compute platforms.
• End-to-end ownership across the silicon lifecycle—from first silicon to stable production.
• Advanced silicon debug techniques spanning hardware, firmware, and operating systems.
• Opportunities to influence architecture, validation strategy, and future silicon direction in a highly visible role.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.