We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance.

The ideal candidate has a strong background in DevOps, workload porting, or application enablement. While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale.

This role is remote, based in the United States or Australia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware.
• Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier.
• A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through strategic IT and DevOps enablement.
• Collaborative & Cross-Functional: You enjoy acting as the "technical glue" between IT, DevOps, and AI teams, coordinating complex efforts across boundaries to ensure seamless workload transitions.
• Architecture Agnostic: You are a systems thinker who understands how to bridge the gap between infrastructure and core silicon engineering.

What We Need

• Education: BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
• Workload Expertise: Extensive experience in workload porting, DevOps engineering, or application enablement.
• Systems Fluency: Strong familiarity with CPU architectures and systems design, with a proven track record of troubleshooting and optimizing performance across new architectures.
• Leadership Qualities: Ability to coordinate across multiple technical teams and the potential to mentor or grow a small engineering pod.
• Execution Focus: A mindset geared toward technical delivery and methodology development rather than broad community networking.

What You Will Learn

• Gain deep expertise in bleeding-edge RISC-V system software across server and AI-accelerated environments.
• Directly influence an upcoming project, a high-visibility initiative shaping the future of our internal compute infrastructure.
• Work at the intersection of AI/ML workloads and hardware/software co-design.
• Shape the technical roadmap for how the industry adopts RISC-V for high-performance compute.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We're looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You thrive in building robust verification environments using SystemVerilog, UVM and C++, and can define and drive verification plans independently.
• You bring a system-level mindset, with experience integrating multiple IPs into clusters or SoCs and verifying their interactions.
• You have a strong grasp of stimulus planning, debug techniques, and coverage closure for verifying complex hardware subsystems like caches, NoCs, and memory hierarchies.
• You’re comfortable working on features that span multiple IPs — such as coherence, security — and ensuring their correct behavior at the cluster or SoC level.

What We Need

• A Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• Strong experience with System Verilog and UVM-based verification.
• Proven ability to drive subsystem or SoC-level DV projects with integration and system feature validation responsibilities.
• Familiarity with AXI/CHI protocols, System IPs flows (like debug/trace, power management), and integration flows for multi-IP verification environments.

What You Will Learn

• Techniques to scale DV infrastructure for verifying high-performance RISC-V clusters and SoCs.
• How to verify multi-agent interactions across CPUs, system IPs and NoC or fabric components.
• Best practices for cross-IP feature convergence, integration-level planning, and reuse across cluster/SOC programs.
• How to collaborate with global teams across RTL, DV, software, and validation for cohesive system-level bring-up.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a driven Engineering Program Manager—or a hands-on technical lead ready to step into program management—to help lead the charge on our RISC-V CPU team. In this role, you’ll be at the center of the action, working across architecture, design, verification, physical design, and DFT to drive the full lifecycle of a high-performance CPU—from spec to tapeout to post-silicon debug. You’ll partner with key stakeholders to define bold objectives, lock in milestones, and align the resources needed to bring next-gen compute to life.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A technically strong leader with experience in CPU, SoC, or silicon development.
• Skilled in aligning cross-functional teams to deliver complex, high-performance hardware programs.
• Proactive problem solver who thrives in dynamic, fast-paced environments.
• A clear communicator who can engage engineers and executives alike.

What We Need

• Ownership of full-cycle CPU program management—from spec to tapeout and post-silicon debug.
• Ability to define scope, schedule, and resources, and lead execution across architecture, design, verification, and DFT teams.
• Proven experience driving silicon development, managing risk, and delivering milestones.
• Experience with Functional Safety (FuSa) standards and implementation, especially ISO 26262 and an understanding of automotive industry requirements and standards for hardware development is highly desirable.

What You Will Learn

• How to lead the delivery of cutting-edge RISC-V CPU IP at scale, both internally and for external customers.
• Partnering with top engineers to resolve real-time design challenges, drive schedule trade-offs, and push forward high-impact decisions.
• Leading project reviews and reporting to senior leadership on metrics, risks, and mitigation plans.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we are building open, state of art compute for AI and RISC‑V CPUs. You will lead the technical efforts and strategy around our existing emulation infrastructure for high‑performance CPUs that power these products. Your work will directly enable silicon bring‑up, validation, and customer‑ready systems.

This role is hybrid, based out of Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have strong background in CPU verification, emulation, and debug.
• You are fluent in Verilog and SystemVerilog for complex SoC designs.
• You are a technical leader who drives complex debug efforts, solves ambiguous technical problems, and mentors younger engineers.
• Experience with Zebu emulation platforms is a significant plus.
• You collaborate closely with design, verification, and vendors to move fast and unblock teams.

What We Need

• Lead the technical strategy and execution to scale and optimize existing emulation infrastructure on commercial and open‑source platforms.
• Enable the emulation infrastructure and workflow, including producing reliable emulation builds.
• Drive and lead complex cross-functional debug and root cause analysis efforts.
• Optimize emulation performance and regression flows with Design Verification teams and tool vendors.

What You Will Learn

• How to bring state of art AI and CPU architectures to life on emulation.
• How to design large‑scale emulation regressions that mirror real customer workloads.
• How to tune emulation performance across different vendors and hardware platforms.
• How open hardware and software come together across Tenstorrent’s full compute stack.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Bengaluru, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Austin, TX, Fort Collins, CO or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As the RISC-V software release and packaging engineer you will be responsible for building, packaging, and releasing the software that enables our customers to succeed with our RISC-V and system IP products. Our software combines Linux and many other open source software packages with our own software to accelerate customer use of our IP.

This role is remote or hybrid in the North America or Australia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Background in Linux and open source development.
• Interested in creating and improving automated processes to deliver quality products.
• Have a collaborative work style with the ability to work across team and technology boundaries.

What We Need

• Experience working with Linux system creation tools such as Yocto or Buildroot, or packaging software for other distributions.
• Hands on usage of CI/CD systems and software build tools.
• Proficiency with scripting languages such as Python and Bash for automation.
• Experience with Git, release management, and branching methodologies.

What You Will Learn

• How cutting edge silicon IP is created and delivered.
• How Tenstorrent uses open source to enable new technologies and empower customers.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we build open, state of art compute for real workloads and real developers.

You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You bring 8+ years in CPU verification or closely related digital design.
• You know high‑performance out‑of‑order CPU microarchitecture in depth.
• You work comfortably with RTL, waveforms, logs, and complex debug scenarios.
• You communicate clearly across design, DV, emulation, and post‑silicon teams.

What We Need 

• Plan and drive functional verification for CPU core features and microarchitectural scenarios.
• Develop UVM, assembly, and C/C++ stimulus for ISA and microarchitectural coverage.
• Develop/debug C++ functional models of RISC-V extensions and un-core components such as APIC and IOMMU.
• Debug simulation and emulation regressions using waveforms, logs, and RTL understanding.
• Build and refine coverage models to track and close architectural and microarchitectural coverage.
• Improve core, cluster, and chip‑level testbenches and debug infrastructure.
• Support design bring‑up across simulation, emulation, and post‑silicon environments.
• Collaborate with design, test, and validation to deliver robust CPU cores and clusters.

What You Will Learn 

• How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.
• Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.
• Ways to scale coverage, debug, and infrastructure across multiple CPU programs.
• How open hardware and software fit into Tenstorrent’s broader compute roadmap.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V–based SoCs. This role sits at the intersection of silicon, firmware, and system software, and requires hands-on lab experience and understanding of SoC architectures.

You will own post-silicon validation from first-silicon bring-up through production readiness, working closely with design, pre-silicon verification, firmware, and software teams.

This role is hybrid , based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You are a seasoned post-silicon engineer with 10+ years of experience in SoC bring-up, validation, and silicon debug.
• You have a strong grasp of CPU and SoC architectures, including RISC-V privilege modes, caches, coherency, and memory systems.
• You are comfortable debugging complex hardware/software interaction issues using lab tools and low-level software.
• You thrive in cross-functional environments and enjoy working closely with RTL, firmware, and software teams to solve hard problems.

What We Need

• Lead first-silicon bring-up of RISC-V CPU–based SoCs and execute post-silicon validation plans.
• Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals, and high-speed interfaces.
• Develop and debug bare-metal tests, boot flows, and collaborate on Linux bring-up and driver validation.
• Provide actionable feedback, support ECO validation, and drive fixes for future silicon revisions.

What You Will Learn

• Deep hands-on exposure to cutting-edge RISC-V SoCs, AI accelerators, and high-performance compute platforms.
• End-to-end ownership across the silicon lifecycle—from first silicon to stable production.
• Advanced silicon debug techniques spanning hardware, firmware, and operating systems.
• Opportunities to influence architecture, validation strategy, and future silicon direction in a highly visible role.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking an exceptional and highly motivated leader to take on a dual role, serving as both the System IP Leader for our global product lines and the India Site Lead for our growing engineering design center. This critical position requires a blend of deep technical expertise in complex System IP development, strategic business acumen, and proven experience in managing and growing a high-performing site/office.

The successful candidate will drive the technical direction and execution of our flagship IP portfolio while simultaneously being responsible for the operational success, cultural health, and strategic growth of our entire India office. This role demands a leader who can operate effectively at both a highly granular technical level and a broad organizational level, acting as the primary representative for Tenstorrent’s executive leadership in India.

This role is on-site, based out of Bangalore, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You are a seasoned semiconductor professional with over 15 years of experience specializing in SoC architecture and System IP development.
• You are an expert in high-speed interconnects, memory subsystems, and security implementations for next-generation products.
• You are a proven technical leader with more than 5 years of experience managing large-scale cross-functional engineering teams through complex delivery cycles.
• You are an experienced site leader with a strong track record of partnering with global operations and driving strategic growth for the engineering center in India.
• You are a strategic communicator capable of bridging the gap between local technical execution and global executive leadership.
• You are a dedicated mentor focused on fostering high-performance cultures and driving career growth within multi-national organizations.

What We Need 

• You will define and execute a long-term technical roadmap for System IP that ensures optimal performance, power, and area.
• You will oversee the end-to-end delivery of high-quality IP components while enforcing best practices for documentation and reusability.
• You will implement rigorous verification methodologies to ensure first-pass silicon success across all system-level integrations.
• You will drive the strategic expansion of the India site by aligning local talent acquisition with global business objectives.
• You will manage site operations and budgets to maintain a collaborative and compliant environment for all functional groups.
• You will act as the primary liaison between the India office and global leadership to advocate for local capabilities and needs.

What You Will Learn 

• You will master the specific architectural requirements and proprietary workflows used in your next-generation product lines.
• You will identify the unique cultural strengths of the current India team to further enhance local employee engagement.
• You will adapt your leadership style to the organization's specific internal processes for cross-functional synergy and resource allocation.
• You will gain deeper exposure to the specific implementation of advanced process nodes and emerging chiplet technologies.
• You will learn the nuances of the global vendor relationships to better manage external IP integrations.
• You will explore new ways to expand functional ownership within the India site to maximize its contribution to the global roadmap.

We are seeking a highly skilled and independent Design Verification Engineer to join our RISC-V CPU team. In this role, you will be responsible for the block-level verification of high-performance Cache and Coherence units. You will lead the development of sophisticated UVM environments to ensure the quality and reliability of our next-generation IP solutions.

This role is hybrid, based out of Bangalore, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have strong hands-on experience with SystemVerilog and UVM and enjoy building verification environments from the ground up.
• You are comfortable driving complex DV efforts independently, from strategy definition to coverage closure.
• You have a solid understanding of RTL verification, debugging, and coverage analysis.
• You bring curiosity and strong problem-solving skills, with exposure to cache, interconnects, or memory systems being a plus.

What We Need

• Define comprehensive verification strategies and architect robust DV environments for block and sub-system level IPs.
• Develop reusable UVCs and execute constrained-random test plans to validate complex corner cases.
• Perform RTL-level functional verification, improve functional and code coverage, and debug complex failures.
• Collaborate closely with design and cross-functional teams to drive verification projects to completion.

What You Will Learn

• Deep hands-on exposure to cache pipelines, memory subsystems, and high-performance interconnects.
• Advanced verification techniques to improve efficiency, scalability, and reliability across IPs.
• Practical experience working with AXI/CHI protocols, cache coherence, and memory consistency models.
• End-to-end ownership of complex DV projects in a fast-paced, high-performance compute environment.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Our diverse team of technologists have developed a high performance RISC-V-based CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Great at identifying problems and developing solutions.
• Enjoys building tools and optimizing work flows.
• Skilled in C++ and Python, with an understanding of industry-standard tools for compilation, simulation and emulation.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre-silicon environments.
• Knowledgeable in architecture and microarchitecture of high-performance CPU cores.
• Ideal candidates would possess experience in infrastructure, methodology and performance verification.

What We Need

• Join a team driving improvements in CPU microarchitecture, verify performance and correlate with the RTL.
• Enhance design environment, tools, and methodologies to improve development efficiency.
• Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.
• Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through performance convergence and validation.
• Hands-on experience optimizing CPU designs in both pre-silicon and post-silicon phases.
• Integration of open-source and industry-standard tools to improve flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.