We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance.

The ideal candidate has a strong background in DevOps, workload porting, or application enablement. While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale.

This role is remote, based in the United States or Australia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware.
• Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier.
• A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through strategic IT and DevOps enablement.
• Collaborative & Cross-Functional: You enjoy acting as the "technical glue" between IT, DevOps, and AI teams, coordinating complex efforts across boundaries to ensure seamless workload transitions.
• Architecture Agnostic: You are a systems thinker who understands how to bridge the gap between infrastructure and core silicon engineering.

What We Need

• Education: BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
• Workload Expertise: Extensive experience in workload porting, DevOps engineering, or application enablement.
• Systems Fluency: Strong familiarity with CPU architectures and systems design, with a proven track record of troubleshooting and optimizing performance across new architectures.
• Leadership Qualities: Ability to coordinate across multiple technical teams and the potential to mentor or grow a small engineering pod.
• Execution Focus: A mindset geared toward technical delivery and methodology development rather than broad community networking.

What You Will Learn

• Gain deep expertise in bleeding-edge RISC-V system software across server and AI-accelerated environments.
• Directly influence an upcoming project, a high-visibility initiative shaping the future of our internal compute infrastructure.
• Work at the intersection of AI/ML workloads and hardware/software co-design.
• Shape the technical roadmap for how the industry adopts RISC-V for high-performance compute.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a skilled and experienced Senior Tax Manager to be responsible for leading all aspects of Tenstorrent’s tax function including federal, state, and international income tax filings, annual audits, sales tax reporting and remittance, and strategic tax planning. This role will report to the VP of Finance and key external partners. You should expect to play a meaningful role in building - and sustaining - a world class finance team.

This role is an exciting position that demands excellence in technical skills, execution, and a proven track record of leading sophisticated projects across diverse subject areas. The Senior Tax Manager keeps Tenstorrent compliant, crafts and owns scalable financial processes, and is a financial linchpin for the organization.

This role is remote, based out of United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• 8+ years of relevant experience at some combination of public accounting firm, private company, or start-up, showing progressive complexity in scope and responsibilities.
• Bachelor's degree in Accounting, Business Administration, or a related field.
• CPA or CA with a general understanding of income tax compliance and accounting for various types of legal entities, including exposure to ASC 740.
• Strong project management skills encompassing attention to detail and ability to prioritize and lead high priority tasks on concurrent timelines.
• Strong interpersonal, verbal, and written communication skills as demonstrated by the ability to translate complex concepts across multiple audiences.

What We Need

• Oversight of our core tax responsibilities including corporate income taxes, sales and use tax, local business taxes, employee-facing taxes, and more.
• Managing the relationship and workflow with outside tax consultants, advisors, and strategic partners.
• Finding opportunities for efficiency improvements and driving implementation of the solutions.
• Educating cross-functional teams about tax risk and issues / opportunities arising from our activity.
• Supporting new and existing research and products by working cross-functionally to manage risk and build and maintain scalable tax processes.
• Research, analyze, document, and share the latest developments in global tax legislation and their accompanying impact on Tenstorrent.

What You Will Learn

• How a high-growth AI and semiconductor company builds a world-class tax function.
• How global tax strategy supports rapid innovation in software, hardware, and R&D.
• How to design scalable financial processes that stand up as the company expands.
• How tax considerations shape decision-making across product, operations, and finance.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking  a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures.

This role is remote role open to any location in the U.S.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts.
• Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off.
• Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity).
• Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs.
• A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues.

What We Need

• Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout.
• Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off.
• Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS.
• Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure.
• Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug).
• Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification.
• Bring a solid academic foundation: B.S./M.S. in EE/CE or related field.

What You’ll Learn

• How to implement and close cutting-edge D2D interfaces in advanced multi-die/chiplet architectures.
• Advanced strategies for co-optimizing routing, power grid, and timing for high-speed links across dies.
• Deeper integration techniques working with analog PHY teams, including model handoff (LEF/LIB) and constraint-driven interface design.
• How to drive repeatable, scalable PD methodologies for high-speed interfaces that can be leveraged across future chiplets and products.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

This is a 12 month contract position, with the possibility of a contract extension or conversion to a full time role based on performance and business needs. 

As a Recruiting Coordinator at Tenstorrent, you'll focus on making the candidate experience seamless and positive. This role is all about managing interview logistics, keeping communication clear, and supporting the recruiting team so everything runs smoothly and efficiently.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A highly organized multitasker who finds satisfaction in keeping things running smoothly.
• A clear, thoughtful communicator who keeps candidates and teammates informed and supported.
• Comfortable navigating G-Suite and applicant tracking systems like Greenhouse or Lever—or eager to learn quickly.
• Team-first, proactive, and energized by working in a fast-paced, collaborative environment.

What We Need

• Coordinate and schedule interviews—both virtual and in-person—with precision and attention to detail.
• Keep communication with candidates and hiring managers dialed in and timely.
• Maintain clean, organized candidate data in our applicant tracking system.
• Support team documentation, templates, and general admin tasks to keep everything running smoothly.

What You Will Learn

• What it takes to create a standout candidate experience from start to finish.
• How recruiting operations fuel a growing tech company—and how to scale them.
• Hands-on experience with tools and systems used by top recruiting teams.
• Ways to collaborate with recruiters, hiring managers, and interviewers to move fast without missing a beat.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We're looking for a Staff Software Engineer with a platform infrastructure / Site Reliability Engineering (SRE) background to join us to work on infrastructure automation, integration, and operations. Work covers backend development, service integrations, infrastructure-as-code, and site reliability engineering aspects. Adjacent experience up or down the stack is also highly valuable.

This role is hybrid OR remote, based out of the United States or Toronto.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Fluent in Python, Infrastructure-as-Code (Ansible), shell scripting, Linux SysOps, and CI/CD.
• DevOps mindset with experience in software integrations and operational infrastructure.
• Experienced in observability, including hardware, system, and application level telemetry, monitoring, and alerting (Prometheus, Loki, Alloy, Grafana, Sentry, SNMP, Redfish, IPMI).
• Familiarity with Bare Metal, Virtual Machine and Kubernetes provisioning and operations.
• Neocloud / CSP background is a plus.

What We Need

• Hands-on software engineering to push infrastructure and operational excellence further.
• Effective collaboration with end-users, peers, domain experts, and stakeholders.
• Leadership to grow teams’ capabilities and eagerness to learn more.

What You Will Learn

• Close-up experience to work with everything from data center hardware to user interfaces.
• Leverage the latest AI tools in your day-to-day work.
• Collaborate closely with a diverse range of experts, from HW, SW, AI/ML, and ops backgrounds.
• Expand your expertise to adjacent areas of interest with no siloes inside the team.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we’re building cutting-edge hardware and software solutions that power AI, HPC, and general-purpose workloads. As a Performance Architect on our Platform Architecture team, you’ll work across ML software stacks, compilers, CPU design, cache coherency protocols, and interconnect fabrics to shape the future of high-performance systems. This role is all about bridging software execution and silicon design—making data-driven decisions that directly influence our SoC performance.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Passionate about solving complex system-level performance problems.
• Comfortable working across hardware and software boundaries.
• Analytical and data-driven, with a talent for turning workloads into architectural insights.
• Collaborative, thriving in cross-functional teams spanning compilers, CPU, and interconnect.
• Excited to shape the future of AI/HPC platforms through performance architecture.

What We Need

• BS/MS/PhD in EE, ECE, CE, or CS
• Deep understanding of NoC topologies, routing algorithms, QoS, and traffic scheduling.
• Expertise in cache coherency protocols (AMBA CHI/AXI) and modern memory/IO technologies (DDR, LPDDR, GDDR, PCIe, CCIX, CXL).
• Proficiency in C/C++ programming, with experience in building efficient performance models.
• Familiarity with ML/AI traffic patterns or formal verification of cache coherence protocols is a strong plus.

What You Will Learn

• How real ML/AI traffic patterns influence SoC interconnect and cache design.
• The art of balancing performance vs. complexity in coherence and memory hierarchies.
• How performance models feed into CPU and accelerator microarchitecture decisions.
• Best practices for correlating pre-silicon and post-silicon performance.
• Cutting-edge approaches to integrating heterogeneous compute systems at scale.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The Mixed Signal IC Layout Design Engineer role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs.

This role is remote, based out of anywhere in the United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).
• Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).
• Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon and a strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.
• Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with circuit designers; typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.

What we need

• Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.
• Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.
• Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.
• Support post-layout extraction and simulation and, as a bonus, contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.

What you will learn

• Deep, hands-on experience with cutting-edge FinFET technologies (down to 2nm) and the nuances of mixed-signal layout at these nodes.
• How to integrate high-speed analog/mixed-signal IP into a complex D2D PHY, including interactions across digital, analog, and I/O domains.
• Advanced approaches for managing EM/IR, ESD, latch-up, and physical-verification closure in dense mixed-signal environments.
• How to influence and evolve layout flows, methodologies, and automation, shaping how the broader team delivers high-quality silicon.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As the RISC-V software release and packaging engineer you will be responsible for building, packaging, and releasing the software that enables our customers to succeed with our RISC-V and system IP products. Our software combines Linux and many other open source software packages with our own software to accelerate customer use of our IP.

This role is remote or hybrid in the North America or Australia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Background in Linux and open source development.
• Interested in creating and improving automated processes to deliver quality products.
• Have a collaborative work style with the ability to work across team and technology boundaries.

What We Need

• Experience working with Linux system creation tools such as Yocto or Buildroot, or packaging software for other distributions.
• Hands on usage of CI/CD systems and software build tools.
• Proficiency with scripting languages such as Python and Bash for automation.
• Experience with Git, release management, and branching methodologies.

What You Will Learn

• How cutting edge silicon IP is created and delivered.
• How Tenstorrent uses open source to enable new technologies and empower customers.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is building next-generation RISC-V CPUs optimized for AI, high-performance computing, and emerging autonomous AI systems. As the RISC-V AI / HPC & Agentic Software Engineering Lead, you will operate at the hardware–software boundary, enabling AI, HPC, and agentic AI software stacks on Tenstorrent’s RISC-V processors. This role is responsible for integrating and optimizing Tenstorrent’s LLK (Low-Level Kernel) infrastructure for CPU execution, while leading the bring-up of a RISC-V-native agentic AI software stack — including runtime orchestration, distributed execution frameworks, memory systems, and developer tools required for goal-driven AI systems. You will work closely with CPU architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A systems-oriented software engineer with deep experience in HPC and AI software stacks.
• Experienced with distributed AI systems, orchestration frameworks, or agentic AI architectures.
• Comfortable working close to hardware and instruction-level programming.
• Skilled at translating performance targets into architectural and software requirements.
• Experienced in runtime systems, profiling, and low-level optimization.
• Motivated by hardware–software co-design and scaling next-generation AI infrastructure.

What We Need

• Strong background in HPC and AI software development.
• Solid understanding of RISC-V architecture (ISA, extensions, micro-architectural implications).
• Proficiency in C/C++ and systems programming.
• Experience optimizing performance-critical code paths.
• Experience with agentic AI frameworks, distributed execution systems, or orchestration platforms.
• Familiarity with compiler toolchains (LLVM, GCC).
• Experience with vectorization, custom ISA extensions, or accelerator integration.

What You Will Learn

• How AI and agentic workloads map to RISC-V microarchitecture.
• Custom ISA extension design for AI acceleration.
• End-to-end HPC/AI/agentic stack integration.
• Runtime orchestration for distributed AI systems.
• Hardware–software co-design for scalable AI-native CPU platforms.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is building a world-class AI ecosystem, and ISV partnerships are at the center of that strategy. As Head of ISV Partnerships, this role will define and scale global relationships with software partners—driving co-innovation, ecosystem adoption, and meaningful revenue impact across AI and compute platforms.

This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Boston, MA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strategic ecosystem builder with a track record of growing ISV partnerships in AI, cloud, or infrastructure environments.
• Technically fluent in AI/ML stacks and developer ecosystems, with the ability to connect software to hardware value.
• Strong executive communicator, comfortable influencing C-level stakeholders and navigating complex partnerships.
• Commercially minded operator who balances long-term strategy with measurable business outcomes.

What We Need

• Ownership of Tenstorrent’s global ISV strategy, driving ecosystem growth, software enablement, and indirect revenue.
• Development of high-impact partnerships across AI/ML frameworks, enterprise software, and vertical solutions.
• Leadership of joint GTM efforts, including co-marketing, technical integration, and sales alignment with clear KPIs.
• Close collaboration with product, engineering, and sales teams to align partner priorities with roadmap and customer needs.

What You Will Learn

• How to shape and scale a global AI ecosystem at the intersection of hardware, software, and infrastructure.
• Deep exposure to leading ISVs, developer platforms, and emerging AI workloads across industries.
• Experience driving co-innovation and GTM strategy in a high-growth, category-defining company.
• Opportunities to influence product direction, ecosystem strategy, and long-term market positioning.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.