As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You’ll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced physical design engineer who thrives in complex, multi-stakeholder projects.
• Detail-driven, with a strong sense of ownership from synthesis through design closure.
• Comfortable working at advanced nodes (3nm and below) and multi-GHz designs.
• A collaborative team player who enjoys mentoring others and influencing methodology.
• Clear communicator who can balance technical depth with schedule and resource constraints.

What We Need

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of industry experience in physical design for CPU, or GPU products.
• Strong hands-on experience with Synopsys and/or Cadence tools across synthesis, P&R, and closure.
• Proven expertise in timing closure, ECO flows, and PV convergence at block and chip level.
• Proficiency in scripting (TCL required; Python or similar strongly preferred) and strong English communication skills.

What You Will Learn

• How large-scale chiplet-based systems are architected, implemented, and integrated into SiP solutions.
• Best practices for achieving timing and power convergence on advanced silicon technologies.
• How physical design decisions impact system-level performance and scalability.
• Effective collaboration across global teams and external partners.
• How Tenstorrent evolves and standardizes physical design methodologies across projects.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a senior physical design engineer to join Tenstorrent’s AIDC Yayoi project, driving chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a cutting-edge system-in-package environment.

This role is hybrid, based out of Tokyo, Japan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or computer science, with extensive experience (typically 10+ years) in SoC/ASIC/GPU/CPU physical design on taped-out designs.
• You are highly skilled with industry-standard tools (e.g., Synopsys/Cadence) and physical verification, and comfortable scripting in TCL and at least one other language (e.g., Python).
• You are a strong collaborator who can guide and mentor junior engineers, communicate clearly with global stakeholders, and navigate complex technical trade-offs to drive designs to closure.
• You are organized and data-driven, able to build implementation plans, monitor PPA and schedule metrics, communicate resource needs, and proactively identify and manage risks.

What We Need

• Lead chiplet and chip-top implementation for a high-profile, multi-chiplet System-in-Package project and place and route for high-speed CPU core designs in advanced nodes (5nm and below).
• Own chip-top floorplanning and integration: BUS and fabric planning, bump and IO placement, and hierarchical top/bottom floorplanning to achieve timing and PPA closure at chip level.
• Drive full physical verification and convergence, electrical rules, DRC/LVS, noise, and electromigration checks
• Take ownership of chip-level synthesis, BUS and bump planning, SoC floorplanning, and chip-top PV and EMIR, while providing technical leadership and mentoring to junior team members.

What You Will Learn

• Deep expertise in system-in-package design and multi-chiplet integration, working hands-on project with complex chip-top interfaces and constraints.
• Best practices for high-frequency, advanced-node (5nm and below) CPU design implementation, including cutting-edge timing closure, EMIR, and sign-off methodologies.
• How to operate in a highly collaborative global environment, partnering daily with Tenstorrent experts and leaders across Japan, the USA, and other regions, as well as external stakeholders.
• Advanced strategies for scaling physical design flows, improving reproducibility of convergence, and optimizing project PPA and schedule across multiple tapeouts.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is building next-generation RISC-V CPUs optimized for AI, high-performance computing, and emerging autonomous AI systems. As the RISC-V AI / HPC & Agentic Software Engineering Lead, you will operate at the hardware–software boundary, enabling AI, HPC, and agentic AI software stacks on Tenstorrent’s RISC-V processors. This role is responsible for integrating and optimizing Tenstorrent’s LLK (Low-Level Kernel) infrastructure for CPU execution, while leading the bring-up of a RISC-V-native agentic AI software stack — including runtime orchestration, distributed execution frameworks, memory systems, and developer tools required for goal-driven AI systems. You will work closely with CPU architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features.

This role is remote, based out of Taiwan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A systems-oriented software engineer with deep experience in HPC and AI software stacks.
• Experienced with distributed AI systems, orchestration frameworks, or agentic AI architectures.
• Comfortable working close to hardware and instruction-level programming.
• Skilled at translating performance targets into architectural and software requirements.
• Experienced in runtime systems, profiling, and low-level optimization.
• Motivated by hardware–software co-design and scaling next-generation AI infrastructure.

What We Need

• Strong background in HPC and AI software development.
• Solid understanding of RISC-V architecture (ISA, extensions, micro-architectural implications).
• Proficiency in C/C++ and systems programming.
• Experience optimizing performance-critical code paths.
• Experience with agentic AI frameworks, distributed execution systems, or orchestration platforms.
• Familiarity with compiler toolchains (LLVM, GCC).
• Experience with vectorization, custom ISA extensions, or accelerator integration.

What You Will Learn

• How AI and agentic workloads map to RISC-V microarchitecture.
• Custom ISA extension design for AI acceleration.
• End-to-end HPC/AI/agentic stack integration.
• Runtime orchestration for distributed AI systems.
• Hardware–software co-design for scalable AI-native CPU platforms.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a Interconnect and Compute Architect  to help define and build next-generation CPU networking architecture for both datacenter and emerging robotics/automotive applications. You will contribute to our current datacenter networking efforts while also helping to seed and specify future medium- to low-power robotics/automotive devices for AI/ML compute and sensor ingest. The initial focus will be datacenter networking, with robotics as the first target within the automotive/robotics space.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You thrive while navigating multiple priorities and ambiguous, evolving requirements.
• You have knowledge of Ethernet  network architecture and how performance is modeled..
• You have experience with die-to-die interfaces and understand associated protocols and design tradeoffs.
• You understand Ethernet networking concepts and how they map onto on-chip and off-chip fabrics
• You have experience with datacenter scale up architectures like UALink, NVLink, and Broadcom SUE.
• You have experience with scale out RDMA protocols like RoCE, Infiniband, and others.

What We Need

• A Interconnect and Compute designer who can contribute to both datacenter networking.
• Someone comfortable with the intersection of forwarding, buffering, modeling and RTL design to guide architectural decisions
• An engineer who can collaborate across hardware, software, and systems teams to define and refine networking requirements.
• A contributor who can help drive forward next-generation CPU networking architecture for AI/ML workloads.

What You Will Learn

• How to build next-generation CPU networking architectures for both high-performance datacenters. 
• AI/ML specific protocols and implementations. 
• Learn how to build extreme low latency networks across ethernet topologies and high performance computing (HPC) topologies.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. This is a CPU tech-leadership role focused on driving power analysis and projections for the development of CPU chiplet with an emphasis on power analysis. The role involves defining CPUrail planning while collaborating closely with SoC and Board teams. Responsibilities include optimizing the system PDN for Block rails, and managing the power vector plan for comprehensive coverage of Chip level. The position requires driving power analysis on RTL and Netlist using tools like Joules and PrimePower, working with RTL design, synthesis, and physical design teams to measure and optimize power, and evaluating new power optimization techniques at various design stages. Additionally, the role involves tabulating metrics results for analysis comparison and workingwith post-silicon teams to correlate projections with silicon power measurements.

This role is hybrid, based out of Tokyo, Japan

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Extensive experience in power analysis and optimization for complex ASICs (typically 10+ years of ASIC or related design experience).
• Comfortable working across RTL, synthesis, and physical design stages, including low‑power implementation techniques and ECO‑based timing closure.
• Proficient with power analysis tools (e.g., Joules, PrimePower) and scripting (Tcl plus at least one of Python or similar).
• Strong analytical and problem‑solving skills, with clear written and verbal communication when collaborating across SoC, board, and post‑silicon teams.
• Nice to have: familiarity with UPF/CPF low‑power intent, Verilog/SystemVerilog, CPU micro‑architecture and its power challenges, and basic thermal analysis.

What We Need

• Own power analysis and projections for the CPU chiplet, with emphasis on defining and tracking power metrics throughout the design cycle.
• Define and maintain the power vector plan for comprehensive chiplet‑level and chip‑level coverage.
• Drive power analysis on RTL and netlist using tools such as Joules and PrimePower, partnering with RTL design, synthesis, and physical design teams to measure and optimize power.
• Evaluate and propose new power optimization techniques at RTL, synthesis, and physical design stages, and implement changes via timing ECO and flow updates.
• Tabulate and compare power metrics and reports across design iterations, and work with post‑silicon teams to correlate projections with silicon measurements.

What You Will Learn

• How to define and execute a power strategy for a 2nm CPU chiplet within a multi‑chiplet system‑in‑package, including rail planning and system‑level PDN optimization.
• Best practices for end‑to‑end power closure, from RTL through netlist and physical design, in collaboration with global RTL, SoC, and board teams.
• How to correlate pre‑silicon power models with real silicon behavior and feed lessons learned back into next‑generation CPU and SiP architectures.
• How Tenstorrent integrates CPU chiplets, AI accelerators, and board‑level power delivery into a cohesive high‑performance platform.

We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better.

In this role, you will ensure functionality and performance of the system.

This role is based out of Tokyo, Japan and offer flexible Hybrid work style.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Verify Tenstorrent’s digital IP and SoC logic at chiplet integration level, using industry standard verification methodologies
• Build and improve components of verification infrastructure including model builds and simulation/regression runs,
• Create verification components like testbenches, checkers and test generators,
• Add assertions and coverages along associated methodologies,
• Build verification test plans for subsystems, align them with project stakeholders, implement test suites, summarize the results and share feedback with project stakeholders
• Publish and review verification metrics and drive convergence towards tape-out,
• Work across boundaries with architects, software and design/emulation teams,
• Guide and mentor junior engineers.

Experience & Qualifications:

• Advanced degree in electrical, computer engineering or computer science
• Proven experience in CPU or SoC verification
• Over 10 years of experience with verification flows, scripting and automation
• Good knowledge of logic design
• Knowledge of Verilog//v2k/system Verilog
• Strong problem solving skills
• Excellent organizational and communication skills
• Good English language skills (written and spoken)

Nice to Have:

• Knowledge of RISC-V, machine learning, die-to-die, memory controllers, PCIe, UCIe
• Knowledge of low level drivers and firmware in C
• Fluency in Japanese
• Japanese work visa

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Job title

Senior DFT Engineer

Job description

We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better.

In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. 

Your responsibilities

Integrate and verify test features in digital designs for effective manufacturing testing and silicon debug. Key responsibilities include:

• Building entire chip-level DFT strategies
• Inserting DFTs, including scan chains, memory BIST, and JTAG
• Collaborating with RTL, physical design, and verification teams for testability throughout the design flow
• Scripting and automating DFT flows using industry-standard EDA tools (e.g., Cadence, Synopsys, Siemens)
• Running and analyzing ATPG and fault coverage reports
• Supporting silicon bring-up and debug related to test features
• Knowledge of advanced silicon technologies and methodologies for test coverage optimization
• Experience with formal verification and signoff of inserted DFT logic
• Strong communication and collaboration skills for cross-functional teamwork

Experience and qualifications

• Bachelor, Master or PhD degree in electrical, computer engineering or computer science.
• At least 10 years of relevant industry experience.
• Experience with DFT standard tools (e.g. Synopsys/Siemens), scripting languages (e.g., TCL, Python) is required.
• Experience with DFT planning, debug silicon by making SOC
• Willingness to work with others in a highly complex decision space.
• Skills at developing an DFT plan, monitoring key indicators and communicating resource needs, as well as scoping risk to deliver value on schedule.
• Excellent verbal and written communication in English, and collaboration skills.

Nice to have

• Fluency in Japanese.
• Japanese work visa.

Tenstorrent is at the forefront of AI technology, building next-generation computers where memory is a key component. We're seeking an innovative Memory Architect to push the boundaries of our memory chiplet architecture for AI and CPU applications. You'll work closely with fellow architects, cross-functional teams, and external partners to explore advanced memory technologies.

This role is remote or hybrid, based out of North America or South Korea.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a deep understanding of JEDEC standard DRAMs (GDDR, HBM, LPDDR, DDR) and their specifications.Experience with 3D-stacking, advanced packaging, custom memory, DFI, die-to-die interfaces, storage, and I/O protocols is a huge plus.
• You bring 10+ years of experience in memory system architecture, scheduling algorithms, and controller architecture exploration and design. You have hands-on experience building performance/power simulators or developing memory IPs in HDL. A deep understanding of memory reliability and security is a strong plus.
• You are a collaborative team player with excellent communication skills and a history of mentoring junior engineers.
• A PhD with a focus on computer architecture or a strong research background (or a publication track record) is a strong plus.

What We Need

• Define the architecture and micro-architecture specifications for memory and I/O chiplets, focusing on state-of-the-art memory technology for AI and CPU applications.
• Explore and evaluate next-generation memory technologies, analyzing trade-offs across key metrics like bandwidth, latency, and power to develop a strategic roadmap.
• Develop and own a detailed performance and power modeling infrastructure to enable data-driven decisions for high-throughput, low-latency memory architectures.
• Work closely with SoC design/verification, physical design, packaging, and systems engineering teams to ensure seamless integration. You will also communicate frequently with external partners and customers.

What You Will Learn

• How to lead architectural decisions and drive alignment across IP, SoC, and system software teams in a fast-paced and rapidly growing environment.
• How complex chiplets are brought to life, from architecture specifications all the way to silicon fabrication, packaging, and mass production.
• How Tenstorrent is designing next-generation chiplet-based SoCs that unify AI, CPU, Memory, I/O, and scale-out elements.
• How to optimize data movement across the entire software-hardware stack.
• You will exchange your expertise in the memory subsystem with fellow expert architects in AI, CPU, fabric, security, power, reliability, debug, system design, and scale-out.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we’re building cutting-edge hardware and software solutions that power AI, HPC, and general-purpose workloads. As a Performance Architect on our Platform Architecture team, you’ll work across ML software stacks, compilers, CPU design, cache coherency protocols, and interconnect fabrics to shape the future of high-performance systems. This role is all about bridging software execution and silicon design—making data-driven decisions that directly influence our SoC performance.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Passionate about solving complex system-level performance problems.
• Comfortable working across hardware and software boundaries.
• Analytical and data-driven, with a talent for turning workloads into architectural insights.
• Collaborative, thriving in cross-functional teams spanning compilers, CPU, and interconnect.
• Excited to shape the future of AI/HPC platforms through performance architecture.

What We Need

• BS/MS/PhD in EE, ECE, CE, or CS
• Deep understanding of NoC topologies, routing algorithms, QoS, and traffic scheduling.
• Expertise in cache coherency protocols (AMBA CHI/AXI) and modern memory/IO technologies (DDR, LPDDR, GDDR, PCIe, CCIX, CXL).
• Proficiency in C/C++ programming, with experience in building efficient performance models.
• Familiarity with ML/AI traffic patterns or formal verification of cache coherence protocols is a strong plus.

What You Will Learn

• How real ML/AI traffic patterns influence SoC interconnect and cache design.
• The art of balancing performance vs. complexity in coherence and memory hierarchies.
• How performance models feed into CPU and accelerator microarchitecture decisions.
• Best practices for correlating pre-silicon and post-silicon performance.
• Cutting-edge approaches to integrating heterogeneous compute systems at scale.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance chiplet based SoC architectures. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance and power aware design.

This role is hybrid, based out of Tokyo.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.
• Strong synthesis and timing closure awareness to support backend teams.

What We Need

• Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.
• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Prior experience in on-chip fabric and interconnect designs and basic understanding of RISC-V Architecture and debug experience is preferable.

What You Will Learn

• How cutting-edge chiplet design are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is building next-generation RISC-V CPUs optimized for AI, high-performance computing, and emerging autonomous AI systems. As the RISC-V AI / HPC & Agentic Software Engineering Lead, you will operate at the hardware–software boundary, enabling AI, HPC, and agentic AI software stacks on Tenstorrent’s RISC-V processors. This role is responsible for integrating and optimizing Tenstorrent’s LLK (Low-Level Kernel) infrastructure for CPU execution, while leading the bring-up of a RISC-V-native agentic AI software stack — including runtime orchestration, distributed execution frameworks, memory systems, and developer tools required for goal-driven AI systems. You will work closely with CPU architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A systems-oriented software engineer with deep experience in HPC and AI software stacks.
• Experienced with distributed AI systems, orchestration frameworks, or agentic AI architectures.
• Comfortable working close to hardware and instruction-level programming.
• Skilled at translating performance targets into architectural and software requirements.
• Experienced in runtime systems, profiling, and low-level optimization.
• Motivated by hardware–software co-design and scaling next-generation AI infrastructure.

What We Need

• Strong background in HPC and AI software development.
• Solid understanding of RISC-V architecture (ISA, extensions, micro-architectural implications).
• Proficiency in C/C++ and systems programming.
• Experience optimizing performance-critical code paths.
• Experience with agentic AI frameworks, distributed execution systems, or orchestration platforms.
• Familiarity with compiler toolchains (LLVM, GCC).
• Experience with vectorization, custom ISA extensions, or accelerator integration.

What You Will Learn

• How AI and agentic workloads map to RISC-V microarchitecture.
• Custom ISA extension design for AI acceleration.
• End-to-end HPC/AI/agentic stack integration.
• Runtime orchestration for distributed AI systems.
• Hardware–software co-design for scalable AI-native CPU platforms.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Are you passionate about scaling AI deployment through enhancing energy efficiency of RISC-V based CPUs and AI Data Centers? Would you like to be part of Open Chiplet Architecture to bring architectural flexibility tailored towards making our customers' experience great with low cost product solutions that are simpler, faster, and open? Are you an expert in Power Management and Optimization of SoCs and Chiplets? Do you enjoy working in a fast paced technical environment with multi-disciplinary teams of smart engineers to tackle the challenging energy efficiency of Data Center Products? At Tenstorrent, we own our Silicon future and provide a comprehensive solution through making our own IPs, Chiplets. Chips, Boards, and Systems. If you said yes to the above questions, we want to work with you.

This role is hybrid based out of Santa Clara, CA. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on expert in Power Management and SoC Power Architecture, with proven experience in data center power optimization.
• Skilled at debugging, experimentation, and root cause analysis, thriving in fast-paced, technically challenging environments.
• A strong collaborator and communicator, comfortable working with multidisciplinary teams across silicon, firmware, and systems.
• Passionate, optimistic, and driven to make bold contributions that push the boundaries of AI hardware.
• Committed to execution and impact — you enjoy doing, not just talking, and are motivated to leave your mark on the future of AI.

What We Need

• Deep expertise in Power Management, SoC Power Architecture, Power Delivery Networks, Thermal Analysis, and Performance Trade-offs
• Proficiency in Power Estimation Methodologies (e.g., using PTPX inputs) and trade-off modeling
• Experience with silicon PVT corners, process node trade-offs, binning, voltage droop mitigation techniques
• Ability to analyze AI and ML workloads for performance and efficiency
• Strong debugging skills and ability to design experiments to root cause issues
• Great interpersonal and collaboration skills to work with diverse engineering teams

What You Will Learn

• Hands-on experience working on the cutting edge of AI hardware design—from chiplets to full systems
• Exposure to Open Chiplet Architecture and the chance to contribute to industry-shaping standards like OCMI
• Opportunities to collaborate across Silicon, Firmware, and System teams, solving some of the most complex energy efficiency challenges in data centers
• A front-row seat to the scaling of AI through RISC-V–based solutions, shaping products that are simpler, faster, and more open
• The chance to leave your mark on the future of AI with a team that values bold ideas, fast execution, and long-term impact

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.