At Tenstorrent, we build computers for AI, and the developers shaping its future.

Our high-performance RISC-V CPUs, modular chiplets, and scalable compute systems give developers full control at every layer of the stack, at any scale from a single-node experimentation to data center-scale deployment.

We believe in an open future. Our architecture and software are designed to be edited, forked, and owned. Our team of engineers, dreamers, and first-principle thinkers is redefining how hardware and software converge to accelerate innovation.

As part of a new organization focused on experience, we need engineers for our Developer Relations team that deeply understand developers’ trials , tribulations, and wins. You'll build, present, and contextualize the tools, demos, and interfaces developers need to navigate and fully utilize Tenstorrent hardware and software. You'll meet developers where they are, understand their needs, and partner with them to build an open future. 

This role is remote, but you're welcome to work from one of our offices if you're nearby. We encourage candidates of all experience levels to apply. Your interview will determine the best fit, and offers will reflect that assessment.

Who You Are

• Passionate tool builder. You're comfortable creating things developers love to use  like command-line utilities, SDKs, dashboards, service integrations, content management systems, and microsites. 
• Curious and explore how AI can augment and enhance your development capabilities. 
• Want to share that experience to empower today's and tomorrow's developers. 
• Believe that being open is a key advantage and wayfinder in how to act and what to do next.

What We Need

• A Bachelor's degree in Computer Science, Engineering, or a related field, or equivalent experience.
• A proven track record building great experiences for a developer audience.
• Strong skills across multiple parts of a developer’s stack.
• Fluency with open source development practices and tools, for example, Git, GitHub, CI, VSCode.
• Strong product instincts.
• Interest and experience working at varying levels of the AI engineering stack.

What You Will Learn

• Build web-based tools, demos, and playgrounds, letting developers explore our offerings.
• Translate complex platform capabilities into intuitive user and developer experiences. We improve the developer experience by reducing friction and improving education throughout.
• Partner closely with Marketing, Creative, Engineering, and Product to connect narrative with function.
• Advocate for seamless UX, from box to screen.
• The state-of-the-art in AI inside a growing, international community of open computing enthusiasts.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a driven Engineering Program Manager—or a hands-on technical lead ready to step into program management—to help lead the charge on our RISC-V CPU team. In this role, you’ll be at the center of the action, working across architecture, design, verification, physical design, and DFT to drive the full lifecycle of a high-performance CPU—from spec to tapeout to post-silicon debug. You’ll partner with key stakeholders to define bold objectives, lock in milestones, and align the resources needed to bring next-gen compute to life.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A technically strong leader with experience in CPU, SoC, or silicon development.
• Skilled in aligning cross-functional teams to deliver complex, high-performance hardware programs.
• Proactive problem solver who thrives in dynamic, fast-paced environments.
• A clear communicator who can engage engineers and executives alike.

What We Need

• Ownership of full-cycle CPU program management—from spec to tapeout and post-silicon debug.
• Ability to define scope, schedule, and resources, and lead execution across architecture, design, verification, and DFT teams.
• Proven experience driving silicon development, managing risk, and delivering milestones.
• Experience with Functional Safety (FuSa) standards and implementation, especially ISO 26262 and an understanding of automotive industry requirements and standards for hardware development is highly desirable.

What You Will Learn

• How to lead the delivery of cutting-edge RISC-V CPU IP at scale, both internally and for external customers.
• Partnering with top engineers to resolve real-time design challenges, drive schedule trade-offs, and push forward high-impact decisions.
• Leading project reviews and reporting to senior leadership on metrics, risks, and mitigation plans.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will own end-to-end technical engagements, translating complex architectural advantages into customer wins while shaping our product roadmap through direct market feedback. If you combine deep technical expertise with exceptional customer engagement skills and want to drive the adoption of next-generation compute IP, join our team.

This role is hybrid, based out of the United States or Canada near one of our main office locations.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with proven success in CPU/GPU/NPU IP sales engagements.
• Technical expert who can articulate complex architectural benefits and conduct deep-dive analyses.
• Self-driven professional who independently manages multiple customer relationships from discovery to win.
• Strategic thinker who identifies customer pain points and positions solutions effectively.

What We Need

• 7+ years in the semiconductor industry with a degree in EE or related field including customer-facing roles in CPU IP.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Deep technical knowledge of CPU architectures, semiconductor technologies, and system-level design.
• Exceptional presentation and communication skills with ability to engage all organizational levels.
• Proven track record of technical wins and managing multiple simultaneous accounts.

What You Will Learn

• How to position cutting-edge RISC-V and AI accelerator IP against industry incumbents.
• Advanced customer engagement strategies for complex technical sales in the semiconductor industry.
• Direct influence on product development through customer feedback and market insights.
• The complete IP business cycle from evaluation through design win and production success.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an Physical Design Engineer to lead  cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. 

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes.
• Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs.
• Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows.
• Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independently.

What we need

• Lead and contribute to cross-functional efforts solving complex physical design challenges across IPs, projects, and advanced technology nodes.
• Develop and enhance RTL-to-GDS methodologies, including floorplanning, synthesis, P&R, STA, signoff, and assembly.
• Architect and deploy AI/ML-driven solutions in production flows to improve engineering efficiency, turnaround time, and QoR.
• Optimize EDA tools and custom CAD flows using data-driven and ML-based techniques, in close collaboration with verification, extraction, timing, DFT, and EDA vendors.

What you will learn

• How to scale AI/ML-driven methodologies across diverse products and advanced technology nodes in real production flows.
• New ways to blend classical EDA algorithms with modern ML techniques to push PPA and runtime limits.
• Best practices for deploying, validating, and monitoring ML models in production CAD environments.
• How to influence next-generation ML-enabled EDA tools and collaborate deeply with cross-functional teams (PV, extraction, timing, DFT).

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors. This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.
• Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).
• Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.
• Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

What We Need

• Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST).
• Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc).
• Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.
• Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness.
• Participate in ATE targeted test patterns, validation and silicon- debug
• Work closely with test and product engineering teams on silicon characterization and validation.

What You Will Learn

• Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies
• In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes
• Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success
• Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a Interconnect and Compute Architect  to help define and build next-generation CPU networking architecture for both datacenter and emerging robotics/automotive applications. You will contribute to our current datacenter networking efforts while also helping to seed and specify future medium- to low-power robotics/automotive devices for AI/ML compute and sensor ingest. The initial focus will be datacenter networking, with robotics as the first target within the automotive/robotics space.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You thrive while navigating multiple priorities and ambiguous, evolving requirements.
• You have knowledge of Ethernet  network architecture and how performance is modeled..
• You have experience with die-to-die interfaces and understand associated protocols and design tradeoffs.
• You understand Ethernet networking concepts and how they map onto on-chip and off-chip fabrics
• You have experience with datacenter scale up architectures like UALink, NVLink, and Broadcom SUE.
• You have experience with scale out RDMA protocols like RoCE, Infiniband, and others.

What We Need

• A Interconnect and Compute designer who can contribute to both datacenter networking.
• Someone comfortable with the intersection of forwarding, buffering, modeling and RTL design to guide architectural decisions
• An engineer who can collaborate across hardware, software, and systems teams to define and refine networking requirements.
• A contributor who can help drive forward next-generation CPU networking architecture for AI/ML workloads.

What You Will Learn

• How to build next-generation CPU networking architectures for both high-performance datacenters. 
• AI/ML specific protocols and implementations. 
• Learn how to build extreme low latency networks across ethernet topologies and high performance computing (HPC) topologies.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a Physical Design Engineer – EMIR to join our silicon team. In this role, you’ll lead EM and IR-drop simulations to ensure robust power delivery, signal integrity, and long-term reliability for high-performance ICs. You’ll work with RTL, physical design, and analysis teams to implement power grid strategies that optimize performance, power, and area (PPA), particularly at advanced nodes like 7nm and below. You’ll also support EMIR sign-off and waiver methodologies across the chip hierarchy.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A physical design specialist with deep experience in EMIR analysis and signoff.
• Comfortable navigating advanced technology nodes and power integrity challenges.
• Proactive and detail-oriented, with a passion for pushing performance and reliability boundaries.
• Collaborative and effective across teams working on RTL, physical design, packaging, and reliability.

What We Need

• 7+ years of experience in physical design or signoff, with a focus on EMIR.
• Hands-on with RedHawk, Voltus, or equivalent industry-standard EMIR tools.
  Strong understanding of IR-drop mitigation, EM compliance, and power grid design.
• Proficiency with layout extraction flows, RC modeling, and metal density checks.
• Experience working in advanced nodes (7nm, 5nm, 3nm), and with scripting languages like TCL, Python, Perl, or Shell.
• Knowledge of floorplanning, bump/RDL design, and sign-off flows (DRC/LVS, timing closure).

What You Will Learn

• How to architect and analyze robust power delivery for Tenstorrent’s RISC-V CPUs and AI chips.
• How to integrate EMIR signoff into fast-paced, high-performance chip design cycles.
• Best practices for hierarchical analysis and EMIR methodology across pre- and post-layout flows.
• Cross-functional collaboration for optimizing PPA while meeting stringent reliability goals.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.
  
  

What We Need

• BS or MS in Engineering (Electrical, Electronics, or related field).
• 7–14 years of hands-on experience in CPU/IP/SoC physical verification.
• Strong command of industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification.
• Solid understanding of advanced node challenges (7nm, 5nm, 3nm) and FinFET design considerations.
• Scripting proficiency (Python, TCL) for automation and flow optimization.
• Familiarity with ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).
  
  

What You Will Learn

• Advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Integration and verification strategies for full-chip signoff across advanced process technologies.
• Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.
  
  

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This role owns the technical strategy and architecture behind Tenstorrent’s core business applications, from ERP and CRM to the integrations that connect everything together. The focus is on building scalable, secure systems and integrations that hold up as the company grows, while providing hands-on technical leadership across SaaS, middleware, and custom services.

This role is hybrid, based out of Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Technical leader who enjoys owning architecture decisions and setting engineering standards.
• Comfortable moving between strategy and hands-on execution across enterprise systems.
• Naturally collaborative, able to guide teams and partners through complex integration work.
• Motivated by building systems that scale cleanly and stay reliable under change.

What We Need

• Ownership of development, customization, and technical oversight for core business applications and integrations.
• Leadership of middleware and integration architecture across ERP, CRM, SaaS platforms, APIs, and iPaaS solutions.
• Design and review of scalable, secure APIs, microservices, and cloud-based integration patterns.
• Proactive management of system performance, upgrades, risk mitigation, and long-term technical health.

What You Will Learn

• How a fast-growing technology company scales its enterprise application ecosystem end to end.
• How integration strategy shapes operational efficiency across finance, sales, and go-to-market systems.
• How to influence tooling, architecture, and standards across a diverse SaaS and cloud environment.
• How to balance speed, reliability, and security in a constantly evolving business systems landscape.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Software Engineer on the Metal Runtime team at Tenstorrent, you’ll work on the low-level software that powers our AI accelerators. You’ll build and optimize high-performance runtime systems that execute directly on the hardware, focusing on scheduling, memory movement, and efficient execution across massively parallel processors. We believe runtime systems are a core part of performance: they determine how hardware resources are utilized, how data flows through the system, and how efficiently workloads are executed at scale.

If you enjoy pushing performance, working close to the metal, and solving complex systems challenges at the hardware/software boundary, this is your kind of role.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong coder in C or C++, and love working close to hardware.
• Comfortable thinking in terms of threads, processors, and memory movement, and experienced writing fast, parallel code across multiple processors.
• Enjoy optimizing execution, scheduling, and memory systems for performance at scale.
• Comfortable debugging at the hardware/software boundary and reasoning about system behavior end-to-end.
• Curious about how runtimes and bare-metal software come together to power AI.
• Collaborative by nature and enjoy solving tough problems with smart people.

What We Need

• Build and optimize the Metal runtime that executes directly on our AI accelerators.
• Develop bare-metal systems that manage compute execution, scheduling, and resource utilization.
• Optimize memory movement and data flow across massively parallel hardware.
• Work closely with hardware teams to maximize performance and efficiency of our architecture.
• Debug, analyze, and tune runtime behavior across complex, distributed systems.

What You Will Learn

• How to design high-performance runtime systems for cutting-edge AI hardware.
• How execution, scheduling, and memory systems interact at scale.
• How to make custom ASICs and co-processors work efficiently across the chip.
• Best practices for debugging complex, performance-critical software.
• How software and hardware co-evolve in a fast-paced AI startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Formal Verification Engineer at Tenstorrent, you will be at the forefront of applying advanced formal verification methods to thoroughly verify intricate CPUs and chiplets. This role involves driving the formal verification strategy, mentoring engineers, and fostering cross-team collaboration to uphold rigorous quality standards and functional specifications. Your direct contributions will be vital to developing groundbreaking technologies and ensuring their seamless and efficient operation.

This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Bangalore, IN.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A formal methods practitioner who enjoys pushing the boundaries of formal methods to solve difficult verification problems.
• Demonstrated experience in applying formal methods to sign off designs or sub-components of designs.
• Detail-oriented with a desire to overcome complex challenges.
• Comfortable collaborating across design, microarchitecture, and verification teams to identify subtle logic bugs.
• Possess strong communication and excellent interpersonal skills for effective team collaboration.

What We Need

• Lead with 5+ years of hands-on experience in formal methods applied to hardware verification.
• B.S. or M.S. (or higher degree) in Computer Engineering, Electrical Engineering, or Mathematics with 5+ years of relevant work experience.
• Strong background and hands-on experience with formal methods and their application to hardware, software, or systems.
• Hands-on experience with VLSI, digital logic design, and verification techniques. Knowledge of digital logic is required.
• Proficiency in temporal logic assertion-based languages like SVA or PSL.
• Experience using EDA formal tools such as Jasper, VC-Formal, Questa, or Yosys for property checking and formal regression. Tool development experience is a plus.

What You Will Learn

• Leverage formal verification algorithms and techniques to prove correctness and identify bugs in design specifications and RTL for high-performance CPUs and chiplets.
• Collaborate with architects to develop formal micro-architecture and architectural specifications for intricate designs, including crafting innovative solutions for complex challenges.
• Prove the robustness of complex design micro-architectures.
• Architect correct-by-construction design methodologies to enhance formal verification efficiency and productivity and contribute to the evolution of formal methodologies.
• Apply artificial intelligence techniques to improve specifications, formal methods applications, and formal verification.
• Contribute to cross-functional product development across CPU, AI, and interconnect domains, and with partners.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a Layout Engineer with expertise in board layout for high-performance computing and  AI hardware. This role requires direct experience with multi-layer boards, HDI vias, blind vias, back drilling, DFM, DFA and routing / layout of interfaces like GDDR, LPDDR, DDR, PCIe Gen 5 & 6, Ethernet IEEE 802.3bj, cd, cf, USB, etc. The ideal candidate will work closely with cross-functional teams consisting of engineers from systems, power, signal integrity and mechanical to ensure that our products meet the layout margins and cutting-edge specifications for mass production boards for data centers, workstations, and consumer computing applications.

This role is hybrid, based out of Toronto, ON or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• Experienced board layout engineer with ~8+ years in PCB design (Cadence Allegro; Altium a plus).
• Hold a B.S. in EE, CS, or equivalent experience.
• Strong background in high-speed, complex PCBs (high layer count, HDI, multi-lamination, VIPPO, back drilling).
• Comfortable defining and applying layout rules (physical, spacing, length-matching) for high-speed designs.
• Confident working with fabricators on stackups, capabilities, and resolving DFM/DFA/DFT feedback.
• Detail-oriented owner of designs with strong communication skills and the ability to work with an international, cross-functional team.

What we need

• A Layout Engineer to own multi-layer PCB layouts for high-performance computing and AI hardware.
• Expertise routing GDDR, LPDDR, DDR, PCIe Gen 5/6, Ethernet (IEEE 802.3bj/cd/cf), USB and other high-speed interfaces.
• Proficiency with Cadence schematic/layout tools (v25.1) in the Cadence Pulse environment.
• Ability to choose appropriate advanced fabrication technologies (HDI, blind/buried vias, VIPPO, back drilling) balancing performance and cost.
• Skill in floorplanning, component placement, board connectivity, and creation of power/ground planes.
• Collaboration with power, signal integrity, and mechanical engineers to meet PDN, SI, mechanical, thermal, and regulatory (IPC, UL, CE, RoHS, FCC) requirements.

What you will learn

• How to design boards for cutting-edge AI and high-performance computing systems in data center, workstation, and consumer products.
• Techniques to optimize signal integrity, power delivery, and manufacturability for mass-production hardware.
• Best practices for working in a deeply cross-functional environment across systems, power, SI, and mechanical teams.
• Practical experience building around a from-scratch, high-performance RISC-V CPU and AI-first compute platform.
• How to navigate and integrate global industry and regulatory standards while pushing performance limits.
• The direct impact of your layout work on the roadmap and success of a fast-growing AI silicon and systems company.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with industry-standard tools (FusionCompiler, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
• Experience driving physical design requirements from early architecture through final signoff.

What You Will Learn

• How to implement cutting-edge AI accelerators, high-performance CPUs and the SOCs that host them on the most advanced process nodes.
• Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
• End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
• Direct impact on products that are redefining the landscape of AI and high-performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we build computers for AI, and the developers shaping its future.

Our high-performance RISC-V CPUs, modular chiplets, and scalable compute systems give developers full control at every layer of the stack, at any scale from a single-node experimentation to data center-scale deployment.

We believe in an open future. Our architecture and software are designed to be edited, forked, and owned. Our team of engineers, dreamers, and first-principle thinkers is redefining how hardware and software converge to accelerate innovation.

As part of a new organization focused on experience, we need engineers for our Developer Relations team that deeply understand developers’ trials , tribulations, and wins. While you’ll certainly build on Tenstorrent hardware and software, your focus will be on working with developers directly online and at in person events. You'll meet developers where they are, understand their needs, and partner with them to manifest an open future we can all be proud of. 

This role is remote, but you're welcome to work from one of our offices if you're nearby. We encourage candidates of all experience levels to apply. Your interview will determine the best fit, and offers will reflect that assessment.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Inspire developers and builders to reach their goals using tools well-suited to their needs.
• Are comfortable talking to developers online, on stage, or in written content developed to connect, instruct, and inspire.
• Explore how AI can augment and enhance your development capabilities and want to share your experience to empower the developers of today and tomorrow.

What You Bring 

• Bachelor’s degree in Computer Science, Engineering, or a related field, or equivalent practical experience.
• Experience managing developer communities.
• Strong skills across multiple parts of a developer’s stack.
• Passion about AI and compute.
• Fluency with open source development practices and tools, e.g., Git, GitHub, CI, VSCode.

What You Will Learn

• Foster meaningful interactions online and offline between Tenstorrent and developers.
• Partner closely with Comms and Marketing to ensure narrative alignment.
• Initiate and nurture VIP dev relationships that scale trust, not just reach.
• Monitor discussions and sentiment within community channels, identify key trends, opportunities, and blocks.
• What you don’t know while working with a team of enthusiastic operators of varying experience levels.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking a highly motivated and passionate CPU Architect to join our processor architecture team, focusing on the CPU’s load-store unit. In this role, you will contribute to the design, analysis, and optimization of cutting-edge CPU architectures with an emphasis on a high-performance load-store unit. This is an excellent opportunity to work alongside world class architects in high-performance computing and processor design.

This role is Remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Drive the architecture, micro-architecture, design and optimization of the CPU load-store unit for Tenstorrent’s high-performance out-of-order RISCV CPUs
• Propose new implementations to optimize load-store PPA
• Perform simulations, modeling, and performance analysis of advanced CPU features and state-of-the-art data prefetchers
• Collaborate with hardware and software teams to optimize memory access patterns and system performance.
• Stay up to date with industry trends and emerging technologies in CPU architecture and the memory subsystem
• Support documentation and presentation of architectural decisions, trade-offs, and findings.

Experience & Qualifications:

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience).
• Strong understanding of computer architecture fundamentals, including memory hierarchy, cache coherence, and data prefetching
• Familiarity with performance modeling and simulation tools (e.g., Gem5, SimpleScalar, or similar).
• Basic knowledge of hardware description languages (e.g., Verilog, VHDL) and system-level programming (C, C++).
• Problem-solving skills and ability to analyze complex system interactions.
• Excellent communication and teamwork abilities.
• Hands-on experience with performance profiling tools and benchmarking methodologies.
• Exposure to parallel processing architectures and multi-core systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced Silicon Validation Engineer to validate and qualify our cutting-edge die-to-die (D2D) subsystem, AI, and Processor IP testchips for the rapidly growing chiplet ecosystem. You'll develop hardware infrastructure for validation platforms, perform comprehensive electrical characterization, and support customer silicon bring-up. If you’re passionate about hands-on silicon testing and want to help usher in the chiplet era of semiconductor products, join us.

This role is on-site, based out of Santa Clara, CA; or Toronto, Canada. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with 5+ years of silicon test and characterization experience in lab environments.
• Expert with oscilloscopes, BERTs, and test equipment who can independently debug complex validation challenges.
• Self-driven problem solver with strong EE fundamentals in both digital and analog circuit design.
• Excellent communicator who collaborates effectively with design teams and tracks progress meticulously.

What We Need

• BS/MS in Electrical Engineering with 5+ years of hands-on silicon validation using Keysight/Tektronix equipment.
• Proven experience with high-speed measurements (Tx jitter, Rx JTOL) and test automation scripting (Python, Perl, LabVIEW).
• Strong understanding of datacomm circuits (amplifiers, PLLs, equalizers) and signal integrity concepts.
• Track record of independently running validation tests and driving issue resolution with design teams.

What You Will Learn

• State-of-the-art die-to-die chiplet validation methodologies for next-generation semiconductor architectures.
• How to build and evolve hardware infrastructure for advanced D2D validation and demo platforms.
• Customer-facing silicon bring-up techniques and product qualification best practices.
• The opportunity to shape validation standards in the emerging chiplet ecosystem at a fast-moving startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a highly skilled and experienced Engineer to lead post-silicon power characterization and correlation activities for cutting-edge semiconductor products. In this role, you will be responsible for developing and executing detailed power measurement strategies on silicon, correlating results with pre-silicon models, and driving improvements across power architecture, design, and modeling methodologies. You will serve as a key technical leader, interfacing across design, architecture, validation, and systems teams to ensure silicon meets power and performance specifications under all operating conditions.

This role is hybrid, based out of Toronto, ON or Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• A Principal-level engineer with 8+ years in silicon power analysis and characterization, and a Master’s or PhD in EE, CE, or related field.
• Deep understanding of digital and mixed-signal power domains, including DVFS, leakage vs. dynamic power, and power gating.
• Highly proficient in lab-based power measurement using oscilloscopes, current probes, power analyzers, and SMUs, plus Python/Perl/MATLAB for automation and analytics.
• A strong debugger and collaborator, comfortable driving cross-functional investigations and clearly communicating technical findings.

What we need

• Own the post-silicon power measurement strategy end-to-end across operating modes, voltages, frequencies, and workloads.
• Build and maintain lab infrastructure, automated workflows, and data analysis pipelines for high-fidelity, repeatable power characterization.
• Correlate silicon power data to pre-silicon models (RTL, gate-level, sign-off), drive root-cause analysis, and refine power estimation methodologies with design and modeling teams.
• Characterize power across PVT corners and work with bring-up/validation teams to develop test content, debug power anomalies, and ensure products meet power and performance specs.

What you will learn

• How state-of-the-art SoCs behave in real silicon across diverse workloads, system configurations, and operating conditions.
• How to influence power architecture, RTL design, and modeling flows by feeding silicon insights directly back into early design phases.
• Best practices for building scalable, automated post-silicon power infrastructures that support multiple products and generations.
• Advanced correlation, margining, and variability analysis techniques that deepen your expertise in both SoC-level power and system-level behavior.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an Advanced Packaging Process Engineer with experience in 2.5D and 3D chiplet packaging to join Tenstorrent’s Packaging team. You will drive advanced package technology and reliability in close partnership with foundries and OSATs, helping push performance and manufacturability for next‑generation AI/ML products.

This role is hybrid, based out of Santa Clara, CA or Taipei City, TW.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are 

• Advanced packaging engineer with hands-on 2.5D/3D experience (CoWoS-R/L, FOCoS, EMIB, FCBGA, organic substrates, silicon interposers, embedded Si/eCB, micro-bumps, BGAs).
• Strong in reliability and failure analysis for advanced packaging, including qualification, root cause analysis, and corrective actions.
• Deep understanding of process flows and materials (polyimide, ABF, core, underfill, mold compound) and their interactions (warpage, stress, delamination, mechanical risk).
• Proven track record working with foundries/OSATs on NPI, design rules, excursions, yield/cost optimization, and production ramp, with clear communication and cross-functional collaboration.

What we need 

• Own advanced package technology implementation for 2.5D/3D chiplet products, including technology choices, process integration, and manufacturability.
• Act as primary technical interface to foundries/OSATs: align capabilities and design rules, manage excursions, drive yield, define/track test vehicles, and coordinate FA.
• Partner with design, reliability, and architecture teams to evaluate tradeoffs (bump pitch, stack-ups, embedded Si, etc.) and lead test vehicle planning to meet program needs.
• MS/PhD in a relevant field (Materials, Mechanical, Electrical, Physics, or related) and 5+ years in advanced packaging for high-performance semiconductors from NPI through production (2.5D/3D flows such as CoWoS, FOCoS, EMIB, FCBGA or equivalent).

What you will learn 

• Deeper exposure to leading-edge 2.5D/3D packaging for high-performance AI/ML and chiplet-based architectures.
• How to balance performance-driven architecture with mechanical and reliability constraints to make robust package technology decisions.
• Ways to use AI- and automation-driven methods to accelerate risk assessment, qualification planning, and technical documentation.
• Best practices for building strategic OSAT and foundry partnerships that enable new capabilities while scaling reliable high-volume production.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Join the team revolutionizing AI computing at Tenstorrent. You'll work on TT-Forge, our MLIR-based compiler that enables developers to run AI on all configurations of Tenstorrent hardware using an open-source, performant, and general-purpose compiler. You will be at the forefront of the AI hardware revolution, building compiler technologies that redefine what’s possible.

 This role is hybrid, and can be based out of Santa Clara, CA; Austin, TX; or Toronto; ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A passionate software engineer eager to work on compiler technologies and the challenges of AI hardware, whether from compilers, systems, or broader software backgrounds.
• Fluent in C++ and Python, with experience building complex systems that bridge high-level frameworks to low-level execution.
• Excited by compiler optimization and machine learning, with experience in PyTorch, JAX, TensorFlow, or deep systems programming.
• A collaborative problem-solver who thrives in open-source and enjoys working closely with hardware and software engineers.

What We Need

• A drive to solve novel challenges in AI compilation, from optimizing computational graphs to creating custom dialects and transformation passes.
• Experience or strong interest in MLIR and how modular compiler frameworks connect AI models to advanced hardware.
• Motivation to build technology that impacts the future of AI, knowing your work will enable the next wave of breakthroughs.

What You Will Learn

• How to build open-source compiler frameworks supporting diverse AI models and workloads, including training and multi-chip scaling.
• Deep expertise in compiler technologies including custom MLIR dialects (TTIR, TTNN, TTKernel) and transformation passes.
• New methods for human-in-the-loop compiler optimization using TT-Explorer, making advanced tuning tools usable by all developers.
• How compiler technology powers Tenstorrent’s mission to deliver affordable, open-source AI computing in a highly competitive space.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

As a Software Engineer on the Metal Runtime team at Tenstorrent, you’ll work on the low-level software that powers our AI accelerators. You’ll design fast, efficient runtime systems that run close to the hardware, and define the host and device APIs that expose these capabilities to the rest of the software stack. We believe APIs are a core part of systems design: they encode hardware semantics, performance tradeoffs, and concurrency models, and they live longer than any single implementation.

If you enjoy pushing performance, working close to the metal, and designing abstractions that make complex systems usable without sacrificing control, this is your kind of role.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong coder in C or C++, and enjoy working close to hardware.
• Comfortable thinking in terms of threads, processors, and memory movement.
• Care deeply about API design, abstraction boundaries, and developer experience in low-level systems.
• Experienced (or interested in) designing libraries or interfaces used by other engineers.
• Think about long-term maintainability, usability, and clarity when designing systems.
• Curious about how runtimes and bare-metal software come together to power AI.
• Collaborative by nature and enjoy solving tough problems with smart people.

What We Need

• Design and evolve host and device APIs that expose Metal runtime capabilities clearly and efficiently.
• Translate low-level hardware behavior into intuitive, high-performance abstractions.
• Collaborate closely with runtime, kernel, and higher-level software teams to align API design with real-world usage.
• Ensure APIs balance performance, control, safety, and ease of use.
• Contribute to runtime implementation where needed to support API design and integration.
• Debug, analyze, and improve usability and performance across the software stack.

Nice to have:

• Experience designing or evolving non-trivial C++ APIs used by other engineers.
• Familiarity with APIs for accelerator systems (e.g., CUDA, SYCL, Vulkan, or similar).

What You Will Learn

• How to design APIs and abstractions for cutting-edge AI hardware.
• How to balance performance, control, and usability in low-level system design.
• How to translate hardware capabilities into clean, developer-friendly interfaces.
• Best practices for building maintainable, high-performance systems software.
• How software and hardware co-evolve in a fast-paced AI startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned physical design engineer who thrives on complex, full-chip implementation challenges.
• Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams.
• Passionate about optimizing chip-level implementations for power, performance, and area.
• Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules.

What We Need

• 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
• Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
• Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
• Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.

What You Will Learn

• How to implement cutting-edge AI accelerators and high-performance CPUs at the SOC level.
• Advanced techniques for chiplet integration and next-generation packaging co-design.
• Strategies for optimizing massive designs with complex power domains and clock architectures.
• Methods for driving successful chip-level closure through effective cross-functional collaboration.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

As our TT-Distributed Software Engineer, you will develop and optimize distributed software systems that power the most efficient and highest-performing AI and HPC clusters. In this role, you'll work on distributed programming across multiple nodes, utilizing systems programming, inter-node communication, and Tenstorrent’s scalable architectures to advance the state-of-the-art distributed inference and training infrastructure.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong C or C++ engineer with solid foundations in systems programming, operating systems, and distributed systems principles.
• Enthusiastic about distributed computing, including IPC, socket programming, and cluster resource coordination.
• Comfortable reasoning about scalability, fault tolerance, and performance across multi-node environments.
• Curious and first-principles thinker who challenges conventional approaches to distributed system design.
• Motivated to grow into a deep technical expert in large-scale distributed AI infrastructure.

What We Need

• Architect, implement, and optimize distributed software systems that coordinate computation and communication across clusters of AI accelerators and CPUs.
• Design and build distributed APIs enabling data-parallel and tensor-parallel AI workloads.
• Leverage MPI-based technologies and related frameworks to scale programming models across multiple hosts and compute nodes.
• Develop robust systems using IPC, inter-node sockets, and distributed communication primitives to ensure reliability and high performance.
• Build and maintain testing, debugging, profiling, and monitoring tools for large-scale distributed workloads and collaborate with model and systems teams on cluster bring-up.

What You Will Learn

• How large-scale distributed inference and training systems are architected across thousands of accelerators.
• Advanced techniques in collective communication, synchronization, and parallel workload distribution.
• The performance characteristics of Tenstorrent hardware in multi-node cluster environments.
• How distributed programming models integrate with compilers, runtimes, and AI frameworks.
• The real-world challenges of deploying, debugging, and scaling next-generation AI clusters.

Tenstorrent is seeking an experienced EDA/PDK CAD Engineer to build and maintain world-class design infrastructure that accelerates our silicon innovation. In this role, you'll install and optimize PDKs, manage EDA tool flows, and partner with analog, digital, and software teams to continuously improve design efficiency. If you're passionate about solving complex CAD challenges and enabling cutting-edge chip design, we want you on our team.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A self-driven problem solver with deep knowledge of PDKs, EDA tools, and IC design flows.
• Experienced in troubleshooting complex CAD issues and developing creative work-around solutions.
• Collaborative communicator who actively seeks feedback to improve team productivity.
• Passionate about challenging industry-leading tools and methodologies to drive continuous improvement.

What We Need

• BS, MS, or Ph.D. in Electrical Engineering and/or Computer Science with 5+ years of industry experience.
• Hands-on expertise installing, configuring, and maintaining PDKs and EDA environments.
• Strong background supporting physical verification flows (DRC, LVS, EM/IR, extraction) and mixed-signal simulation.
• Proven ability to work with vendors, foundries, and cross-functional teams to resolve technical issues.

What You Will Learn

• How to architect and scale design infrastructure for state-of-the-art AI silicon development.
• Advanced techniques for optimizing EDA flows across analog, digital, and mixed-signal domains.
• Direct collaboration with world-class engineers to shape tools and methodologies that define industry standards.
• Best practices for proactive CAD support and continuous flow improvement in a fast-paced innovation environment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is looking for a Staff Product Development Engineer - ATE Content Developer, who will be focused on core content development for high-performance AI/ML silicon. They  will be responsible for developing production test programs on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions, and implementing Streaming Scan Network (SSN) architectures for efficient test data delivery. High level challenges include reducing test cost while maintaining coverage targets, optimizing test time for chiplet and multi-die architectures, and enabling rapid yield learning through robust test methodologies. The work is done collaboratively with a group of highly experienced engineers across DFT, design, product, and manufacturing domains.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced semiconductor test engineer with 7 years and a BS/MS in EE/ECE/CE and a track record testing complex digital devices on advanced nodes.
• Hands-on with Advantest V93K and/or Teradyne UltraFlex+ platforms, comfortable owning production test programs end‑to‑end.
• Deeply familiar with DFT/ATPG flows and test architectures: scan chains, MBIST, compression, JTAG/IEEE 1149.1, and common fault models (stuck‑at, transition, path delay, cell‑aware).
• Proficient in C/C++ or Java, with strong scripting skills in Python, Perl, or TCL to automate flows, pattern handling, and data analysis.
• Skilled at debugging across ATE hardware, test programs, and silicon, and at using data to drive root‑cause analysis and yield improvement.

What We Need

• Develop and optimize production test programs on Advantest V93K using the SmarTest 8 environment, from bring‑up through high‑volume manufacturing.
• Translate ATPG patterns (STIL/WGL) into production‑ready test content, balancing test time, coverage, and cost for chiplet and multi‑die AI/ML devices.
• Implement and debug Streaming Scan Network (SSN) based content for high‑speed scan delivery, ensuring robust and scalable scan test infrastructure.
• Own test content for scan, BIST, and memory test structures, collaborating with DFT teams on pattern debug, fault diagnosis, and coverage improvement.
• Support silicon bring‑up and debug in the lab and at manufacturing sites, including correlation, corner characterization, and PVT studies.
• Build and maintain automation scripts and test methods that improve productivity, repeatability, and quality across the test lifecycle.
• Document test architectures, flows, and debug procedures so they can be scaled across products, sites, and engineering teams.

What You Will Learn

• How to test and scale cutting‑edge AI/ML silicon with chiplet and multi‑die architectures, including exposure to 2.5D/3D packaging and HBM integration.
• Deeper expertise in SSN architectures, high‑speed scan delivery, and next‑generation DFT/test methodologies for complex HPC/AI devices.
• How to drive end‑to‑end yield learning: from ATE data and STDF analytics through to design, DFT, and manufacturing process feedback.
• How a fast‑growing AI hardware startup coordinates DFT, design, product, and manufacturing to bring new silicon from first silicon to high‑volume production.
• Opportunities to influence test strategy, infrastructure, and automation roadmaps for future products and platforms as Tenstorrent’s portfolio scales.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.
  
  

What We Need

• BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verification experience.
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
• Scripting proficiency in Python and TCL for automation and flow optimization.

What You Will Learn

• Advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Integration and verification strategies for full-chip signoff across advanced process technologies.
• Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

We are seeking a junior-to-mid level SOC Emulation Engineer to support our hardware emulation infrastructure and internal chip design teams. This role focuses on integrating vendor and custom hardware transactors, developing Python-based test frameworks, and providing technical support to emulation users across multiple chip projects.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Background in Electrical/Computer Engineering or Computer Science with 1-3 years of experience in chip design, verification, or emulation.
• Proficient in Python for automation and test development, with a working knowledge of C++ and the ability to navigate SystemVerilog RTL.
• Skilled at using modern AI tools (Claude, ChatGPT, Copilot) to accelerate code generation, debugging, and documentation analysis.
• Energetic about supporting diverse teams, from high-level software to low-level firmware, to solve complex runtime and build issues.

What We Need

• Ability to integrate vendor and custom transactors into RTL testbenches while handling clock domain and tri-state resolution.
• Experience building Python APIs (using pybind11) and maintaining CMake-based compilation flows for emulation libraries.
• Solid understanding of standard chip interfaces, bus protocols, and hardware synchronization (resets/clocking).
• A commitment to triaging and debugging the full stack, spanning from Python tests and C++ bindings down to hardware.

What You Will Learn

• Deepening your expertise with world-class platforms like Synopsys Zebu for massive-scale silicon validation.
• Gaining a holistic view of chip development by bridging the gap between hardware RTL and software drivers.
• Building and optimizing large-scale emulation build and run tooling for high-performance engineering teams.
• Refining your ability to gather requirements and facilitate communication between hardware designers and software engineers.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes.

This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in STA and passionate about enabling silicon to meet aggressive performance goals.
• Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies.
• A collaborative team player who works well across logic, DFT, and physical design boundaries.
• Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows.

What We Need

• 7+ years of industry experience and a proven record of successful tapeouts.
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
• Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
• Familiarity with SPICE modeling and worst-case corner analysis.

What You Will Learn

• How to close timing on Tenstorrent’s high-performance RISC-V CPUs and AI SoCs.
• Advanced STA methodologies tailored to modern sub-micron process technologies.
• How to collaborate with world-class engineers across RTL, DFT, and physical design teams.
• How to influence chip performance through timing methodology innovation and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
• Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability.
• Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST).

What we need

• Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC.
• Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.

What you will learn

• How to implement and close AI SoC partitions end-to-end, including power intent, timing, and physical signoff in a modern Synopsys-based flow.
• Deeper expertise across signoff domains: EM/IR, DRC/LVS, logical equivalence (LEC/Formality), and CDC-aware implementation on meaningful production blocks.
• Practical integration of analog/mixed-signal macros (PLL/DLL), DFT features (OCC/MBIST), and SoC interface IP within advanced physical design flows and collaborative tapeout environments.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent’s AI Software Infrastructure team builds the platforms that power internal development, workload orchestration, and hardware allocation across large-scale AI systems. This role focuses on designing and operating Kubernetes-based platforms on on-prem data centers, enabling engineers and customers to run workloads efficiently on Tenstorrent hardware.

This role is hybrid based out of Santa Clara, CA; Austin, TX; or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced backend or infrastructure engineer with a focus on platform development in large-scale environments.
• Strong expertise in Kubernetes, including cluster provisioning, operators, and production debugging.
• Proficient in Python or Go for building APIs and platform services.
• Comfortable working with Linux systems, networking fundamentals, and distributed systems.
• Collaborative and adaptable, able to work across engineering, infrastructure, and deployment teams.

What We Need

• Design and build platform services for workload orchestration, ML services, and internal development workflows.
• Develop APIs and systems that enable users and services to interact with infrastructure platforms.
• Own Kubernetes-based platforms including cluster lifecycle, scaling, and operational maturity.
• Integrate platform systems with CI/CD pipelines, GitOps workflows, and internal tooling.
• Partner with SRE, infrastructure, and deployment teams to support large-scale internal and external environments.

What You Will Learn

• How large-scale AI platforms are built and operated on custom accelerator hardware.
• Advanced Kubernetes patterns including operators, controllers, and cluster lifecycle management.
• How internal platforms evolve into production-grade systems used by customers.
• How orchestration, APIs, and infrastructure come together to support AI workloads.
• How platform engineering scales across on-prem and hybrid environments.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a Field Application Engineer who’s wired for AI/ML, fluent in real-world problem-solving, and excited to build with the people actually using what we make. You will collaborate closely with the sales team and enterprise customers, leveraging your deep technical knowledge in AI to drive the adoption of our products and solutions. This is a customer-facing role that requires both technical expertise and excellent communication skills to convey complex technical concepts to non-technical stakeholders.

This role is hybrid, based out of Santa Clara, CA.  

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You’ve lived in the AI/ML trenches, whether as a field engineer, a solutions architect, or the one tapped in when things needed to “just work.”
• You speak both machine and human. Whether it’s a researcher or a skeptical executive, you know how to break things down and bring them to life.
• You’re fired up about generative models, LLMs, and the edge of what’s possible when software meets purpose-built silicon.
• Work directly with customers in meetings, presentations, and workshops to understand their technical challenges and provide effective solutions.
• Partner closely with sales operations and product teams to provide feedback from customers and help shape future product enhancements.

What We Need

• Strong customer-facing skills with 5+ years of relevant technical, enterprise experience (such as Sales Engineer, Solutions Engineer, or Technical Account Manager).
• Your field insight will help shape our roadmap, our features, and the way we show up for developers.
• Proven expertise in AI technologies and frameworks, including machine learning, deep learning, natural language processing (NLP),computer vision, PyTorch or TensorFlow.
• Experience with embedded systems, FPGA Architecture or AI accelerators. Familiarity with hardware/software co-optimization is often critical for efficient inference at the edge.
• Good understanding of data center, server architecture and deployment, thermal/power, and infrastructure management.

What You Will Learn

• How to explore and push the boundaries of AI performance on custom silicon and help developers do the same.
• What it’s like to build the future from scratch, working alongside teams creating hardware, software, and everything in between.
• To master the craft of fine-tuning LLMs, optimizing vision models, and building AI pipelines that run at scale.
• An understanding of why field roles drive real impact turning on-the-ground insight into product breakthroughs and platform momentum.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for an ASIC Design Methodology Engineer to advance our design infrastructure and flows across RTL development, verification, and physical implementation. This role is ideal for engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate silicon success.

This role is hybrid, based out of Toronto, Ottawa, Austin, or Boston.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A strong advocate for design quality and productivity, with expertise in ASIC design flows.
• Skilled in RTL design and familiar with static and dynamic analysis tools.
• Comfortable automating design checks and improving methodology for scalability and reuse.
• A collaborative engineer who partners effectively across RTL, verification, and backend teams.

What We Need

• Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration.
• Own and evolve static code analysis (Lint, CDC, RDC, DFT) and RTL-netlist logic equivalency design methodologies
• Develop synthesis timing constraints (SDC) and low power design specifications (UPF)
• Support RTL-to-GDS flow enablement, ensuring clean handoffs and sign-off readiness.
• Collaborate with EDA vendors and internal tool owners to optimize performance, quality, and runtime.

What You Will Learn

• How large-scale AI SoCs are architected, integrated, and brought to silicon.
• How methodology choices directly impact design performance, power, and verification closure.
• How to build and scale ASIC design flows supporting cutting-edge compute architectures.
• How to integrate cross-functional workflows across design, DFT, DV, physical, and firmware teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is building the world’s fastest, most efficient AI compute clusters. TT-Fabric is the high-performance nervous system of this platform: the low-level networking layer that lets thousands of RISC-V and AI processors snap together into a single, massively parallel distributed supercomputer. If you love squeezing nanoseconds out of hot paths, designing protocols that move data at absurd scale, and turning messy hardware constraints into elegant distributed systems, this is an opportunity to shape the fabric that future AI models will run on

This role is hybrid based out of Santa Clara, CA; Austin, TX; or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who We Are

• Strong systems engineer with deep C or C++ experience and comfort working in low-level or bare-metal environments.
• Passionate about hardware-software interaction, performance tuning, and eliminating inefficiencies at the protocol level.
• Curious about networking, synchronization, and communication across large clusters.
• Comfortable reasoning from first principles and challenging industry conventions.
• Motivated by building infrastructure that directly impacts large-scale AI training and inference performance.

What We Need

• Architect, implement, and maintain TT-Fabric, our low-level networking library powering distributed inference and training.
• Design scalable communication systems capable of coordinating thousands of AI processors efficiently and reliably.
• Optimize protocols, synchronization strategies, and data movement to extract maximum hardware performance.
• Integrate TT-Fabric APIs into the broader programming model in collaboration with AI and hardware teams.
• Help define the long-term architecture of Tenstorrent’s distributed systems stack.

What You Will Learn

• How large-scale AI clusters are architected from the networking layer up.
• The performance characteristics of custom AI hardware and RISC-V processors at scale.
• Advanced synchronization, collective communication, and interconnect optimization techniques.
• How distributed systems design decisions directly influence model throughput and training efficiency.
• How hardware and networking software co-evolve in next-generation AI infrastructure.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Are you passionate about scaling AI deployment through enhancing energy efficiency of RISC-V based CPUs and AI Data Centers? Would you like to be part of Open Chiplet Architecture to bring architectural flexibility tailored towards making our customers' experience great with low cost product solutions that are simpler, faster, and open? Are you an expert in Power Management and Optimization of SoCs and Chiplets? Do you enjoy working in a fast paced technical environment with multi-disciplinary teams of smart engineers to tackle the challenging energy efficiency of Data Center Products? At Tenstorrent, we own our Silicon future and provide a comprehensive solution through making our own IPs, Chiplets. Chips, Boards, and Systems. If you said yes to the above questions, we want to work with you.

This role is hybrid based out of Santa Clara, CA. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on expert in Power Management and SoC Power Architecture, with proven experience in data center power optimization.
• Skilled at debugging, experimentation, and root cause analysis, thriving in fast-paced, technically challenging environments.
• A strong collaborator and communicator, comfortable working with multidisciplinary teams across silicon, firmware, and systems.
• Passionate, optimistic, and driven to make bold contributions that push the boundaries of AI hardware.
• Committed to execution and impact — you enjoy doing, not just talking, and are motivated to leave your mark on the future of AI.

What We Need

• Deep expertise in Power Management, SoC Power Architecture, Power Delivery Networks, Thermal Analysis, and Performance Trade-offs
• Proficiency in Power Estimation Methodologies (e.g., using PTPX inputs) and trade-off modeling
• Experience with silicon PVT corners, process node trade-offs, binning, voltage droop mitigation techniques
• Ability to analyze AI and ML workloads for performance and efficiency
• Strong debugging skills and ability to design experiments to root cause issues
• Great interpersonal and collaboration skills to work with diverse engineering teams

What You Will Learn

• Hands-on experience working on the cutting edge of AI hardware design—from chiplets to full systems
• Exposure to Open Chiplet Architecture and the chance to contribute to industry-shaping standards like OCMI
• Opportunities to collaborate across Silicon, Firmware, and System teams, solving some of the most complex energy efficiency challenges in data centers
• A front-row seat to the scaling of AI through RISC-V–based solutions, shaping products that are simpler, faster, and more open
• The chance to leave your mark on the future of AI with a team that values bold ideas, fast execution, and long-term impact

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

• Experienced compiler engineer with deep knowledge of GCC and LLVM internals, comfortable optimizing for custom hardware targets.
• Strong C/C++ developer with a solid grasp of algorithms, data structures, and performance analysis.
• Collaborative and analytical, able to work across hardware and software domains to deliver efficient, high-performance toolchains.
• Passionate about enabling breakthrough compute architectures through compiler innovation and software-hardware co-design.

• Design, develop, and optimize GCC and/or LLVM compilers for Tenstorrent’s custom RISC-V hardware and AI vector engines.
• Contribute to the co-design of Tenstorrent’s hardware and software stack to maximize performance and programmability.
• Benchmark, analyze, and tune performance of core applications across RISC-V and AI software environments.
• Collaborate with ML engineers to identify and implement compiler support for emerging AI workloads and frameworks.

• How compiler design directly impacts the performance and efficiency of next-generation RISC-V and AI architectures.
• Advanced techniques in hardware-software co-optimization and compiler-driven performance tuning.
• Integration of custom compilers with leading ML frameworks and runtime environments.
• The end-to-end toolchain flow that enables Tenstorrent’s scalable, high-performance AI compute systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an exceptional Senior-level SoC Physical Design Engineer to drive top-level implementation of our complex AI and CPU SoC designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Ft. Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned physical design engineer who thrives on complex, full-chip implementation challenges.
• Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams.
• Passionate about optimizing chip-level implementations for power, performance, and area.
• Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules

What We Need

• 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
• Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
• Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
• Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.

What You Will Learn

• How to implement cutting-edge AI accelerators and high-performance CPUs at the SOC level.
• Advanced techniques for chiplet integration and next-generation packaging co-design.
• Strategies for optimizing massive designs with complex power domains and clock architectures.
• Methods for driving successful chip-level closure through effective cross-functional collaboration.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a C++ Machine Learning Engineer on the AI Models team at Tenstorrent, you’ll work on the training framework behind our most advanced models. You’ll write high-performance C++ code, shape how new layers and operators are implemented, and help models scale across our custom silicon. If you enjoy building the guts of ML systems and seeing them run fast, this role is for you.

This role is hybrid, based out of Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong in C++ and low-level systems programming, especially in performance-critical code.
• Comfortable thinking in tensors, memory layout, and compiler graphs.
• Familiar with PyTorch and curious about how frameworks map to hardware.
• A builder who enjoys solving technical puzzles and digging into the details.

What We Need

• Extend and optimize our ML training framework with new ops, layers, and training features.
• Debug and tune model performance on Tenstorrent chips.
• Work with compiler and kernel teams to make sure models compile and run as expected.
• Support integration of real-world models and help bring them into production.

What You Will Learn

• How ML frameworks and compilers connect at the system level.
• How to translate training workloads into low-level operations optimized for custom silicon.
• How large-scale model training works under the hood, from memory layout to operator fusion.
• What it takes to build infrastructure that supports fast iteration in research and production.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking an IP Software Generalist to develop and optimize the software stack for our IP customers, enabling them to successfully integrate our AI and RISC-V hardware into their systems. In this role, you will build and support a versatile range of software components, from bare-metal firmware and drivers to system-level tools and APIs, ensuring a seamless customer experience. You will partner closely with hardware engineering, IP delivery, customer support, and product teams to deliver robust, scalable, and high-performance software solutions tailored to diverse customer architectures. Success in this role requires adaptability, strong system-level debugging skills, and the ability to bridge the gap between complex hardware IP and user-friendly software integration.

This role is hybrid, based out of Austin, TX; Toronto, ON; or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced software engineer with a strong foundation in C/C++, system programming, and low-level software design.
• Background in firmware, device drivers, embedded systems, or hardware-software co-design.
• Skilled at navigating and troubleshooting complex, full-stack software environments.
• Known for working effectively with cross-functional teams and external customers to resolve integration challenges.
• Able to balance versatile, hands-on coding with high-level architectural problem-solving.

What We Need

• Develop, optimize, and maintain software components for Tenstorrent’s hardware IP offerings.
• Define and build reference software, SDKs, and toolchains to streamline the customer integration process.
• Diagnose and resolve complex hardware/software interaction issues during customer bring-up and deployment.
• Drive the creation of high-quality documentation, test suites, and integration guides for IP software deliverables.
• Partner cross-functionally with hardware and architecture teams to ensure future IP designs are optimized for software usability.

What You Will Learn

• How to build and deploy robust software stacks for cutting-edge AI and RISC-V silicon IP.
• How to drive successful hardware-software integration across a diverse range of customer environments and architectures.
• Firsthand exposure to the complete silicon IP lifecycle, from initial bring-up to massive-scale customer deployment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a senior High Speed Interconnect / Signal Integrity Engineer to design and validate high-bandwidth links for large-scale AI systems. You will define, model, and qualify interconnect solutions across copper and optical technologies for next-generation AI inference and training clusters. 

This role is on-site in Santa Clara, CA, Austin, TX, or Toronto, Canada.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who You Are

• An experienced electrical engineer with a Bachelor’s or Master’s in Electrical Engineering.
• 5+ years working on high-speed communications (100G–1.6T), including signal integrity, channels, and links.
• Comfortable building and owning link and channel budgets and making clear tradeoffs between reach, loss, BER, and margin.
• Hands-on with SI tools and lab equipment such as Keysight ADS, VNAs, TDRs, BERTs, and protocol analyzers.
• Familiar with cable specification and testing, as well as accelerated life testing, mating life, and failure analysis.
• Able to collaborate across hardware, systems, and manufacturing teams; manufacturing/DFM/DTM experience is a plus.

What We Need

• Define and specify high-speed interconnect architectures between systems within large AI clusters.
• Develop requirements, validation plans, and test strategies for passive and active copper cables and optical transceivers at 100G, 400G, 800G, and 1.6T.
• Document topologies, routing assumptions, and cable requirements for internal and customer-facing clusters.
• Perform link and channel budget analysis, including loss, jitter, eye margin, and BER considerations across PVT and aging.
• Lead and execute qualification and reliability testing, including accelerated life testing, mating life, and failure analysis for interconnect components.
• Interface with key industry suppliers, track their roadmaps, and align Tenstorrent’s system designs to future interconnect capabilities.

What You Will Learn

• How to design and validate interconnects for large-scale AI training and inference clusters, spanning multiple generations of Tenstorrent silicon and systems.
• Practical methodologies for closing SI margins at cutting-edge speeds (up to 1.6T) across diverse media (backplane, copper cable, optics).
• How to translate supplier roadmaps and standards into concrete system requirements and deployment constraints for real customer workloads.
• End-to-end exposure to AI system architecture, from rack-level topology choices down to connector, cable, and transceiver details, in collaboration with world-class AI hardware and systems teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.