Sustaining Test Engineer providing on-site support at our OSAT partners in Taiwan. This engineer will be the primary technical interface for production test operations, driving yield improvements, resolving manufacturing issues, and ensuring successful deployment of test solutions across all test insertions.

This role is hybrid, based in Taiwan with regular presence at OSAT facilities.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• You hold a BS/MS in EE/ECE/CE and have 5+ years of experience in semiconductor test engineering.
• You have hands-on ATE experience with Teradyne and/or Advantest platforms, ideally across wafer probe, package test, and system-level test.
• You are a strong debugger across hardware, software, and DUT interfaces, comfortable working independently in a fast-paced production environment.
• You communicate clearly with both HQ and OSAT teams, and are fluent in Mandarin with strong English proficiency.
• Experience with advanced packaging and/or automotive quality (AEC-Q100/Q104) is a strong plus.

What we need

• An on-site engineering owner at OSAT to support yield issues, production debug, and NPI-to-volume ramp for multiple products.
• A test expert to validate, deploy, and maintain test programs for wafer sort, package test, and SLT, and to coordinate hardware maintenance, calibration, and equipment qualification with OSAT.
• Someone who can analyze large volumes of test data, perform yield and statistical analysis, and drive data-based decisions on test coverage, yield, and cost.
• A quality-focused engineer familiar with ISO 9001, IATF 16949, AEC-Q100/Q104, and 8D/CAPA, able to lead RMA and customer return investigations to closure.
• A proactive problem-solver who can manage business continuity (equipment failures, material shortages, capacity constraints) and drive quality containment for test escapes and new failure mechanisms.

What you will learn

• How to scale complex products in high-volume OSAT environments, owning the full loop from test program bring-up to mature production.
• Advanced techniques in test coverage optimization, yield improvement, and cost reduction across wafer, package, and system-level test insertions.
• Practical application of automotive and advanced packaging quality flows, including reliability testing and JEDEC qualification in a production context.
• How to operate as a bridge between HQ product/test engineering and OSAT operations, influencing decisions on design-for-test, test strategy, and quality.
• Best practices in building institutional knowledge: documenting failure modes, debug methodologies, and structured improvement plans that shape future product generations.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors. This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.
• Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).
• Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.
• Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

What We Need

• Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST).
• Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc).
• Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.
• Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness.
• Participate in ATE targeted test patterns, validation and silicon- debug
• Work closely with test and product engineering teams on silicon characterization and validation.

What You Will Learn

• Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies
• In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes
• Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success
• Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.