Tenstorrent is building next-generation RISC-V CPUs optimized for AI, high-performance computing, and emerging autonomous AI systems. As the RISC-V AI / HPC & Agentic Software Engineering Lead, you will operate at the hardware–software boundary, enabling AI, HPC, and agentic AI software stacks on Tenstorrent’s RISC-V processors. This role is responsible for integrating and optimizing Tenstorrent’s LLK (Low-Level Kernel) infrastructure for CPU execution, while leading the bring-up of a RISC-V-native agentic AI software stack — including runtime orchestration, distributed execution frameworks, memory systems, and developer tools required for goal-driven AI systems. You will work closely with CPU architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features.

This role is remote, based out of Taiwan.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A systems-oriented software engineer with deep experience in HPC and AI software stacks.
• Experienced with distributed AI systems, orchestration frameworks, or agentic AI architectures.
• Comfortable working close to hardware and instruction-level programming.
• Skilled at translating performance targets into architectural and software requirements.
• Experienced in runtime systems, profiling, and low-level optimization.
• Motivated by hardware–software co-design and scaling next-generation AI infrastructure.

What We Need

• Strong background in HPC and AI software development.
• Solid understanding of RISC-V architecture (ISA, extensions, micro-architectural implications).
• Proficiency in C/C++ and systems programming.
• Experience optimizing performance-critical code paths.
• Experience with agentic AI frameworks, distributed execution systems, or orchestration platforms.
• Familiarity with compiler toolchains (LLVM, GCC).
• Experience with vectorization, custom ISA extensions, or accelerator integration.

What You Will Learn

• How AI and agentic workloads map to RISC-V microarchitecture.
• Custom ISA extension design for AI acceleration.
• End-to-end HPC/AI/agentic stack integration.
• Runtime orchestration for distributed AI systems.
• Hardware–software co-design for scalable AI-native CPU platforms.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Sustaining Test Engineer providing on-site support at our OSAT partners in Taiwan. This engineer will be the primary technical interface for production test operations, driving yield improvements, resolving manufacturing issues, and ensuring successful deployment of test solutions across all test insertions.

This role is hybrid, based in Taiwan with regular presence at OSAT facilities.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• You hold a BS/MS in EE/ECE/CE and have 5+ years of experience in semiconductor test engineering.
• You have hands-on ATE experience with Teradyne and/or Advantest platforms, ideally across wafer probe, package test, and system-level test.
• You are a strong debugger across hardware, software, and DUT interfaces, comfortable working independently in a fast-paced production environment.
• You communicate clearly with both HQ and OSAT teams, and are fluent in Mandarin with strong English proficiency.
• Experience with advanced packaging and/or automotive quality (AEC-Q100/Q104) is a strong plus.

What we need

• An on-site engineering owner at OSAT to support yield issues, production debug, and NPI-to-volume ramp for multiple products.
• A test expert to validate, deploy, and maintain test programs for wafer sort, package test, and SLT, and to coordinate hardware maintenance, calibration, and equipment qualification with OSAT.
• Someone who can analyze large volumes of test data, perform yield and statistical analysis, and drive data-based decisions on test coverage, yield, and cost.
• A quality-focused engineer familiar with ISO 9001, IATF 16949, AEC-Q100/Q104, and 8D/CAPA, able to lead RMA and customer return investigations to closure.
• A proactive problem-solver who can manage business continuity (equipment failures, material shortages, capacity constraints) and drive quality containment for test escapes and new failure mechanisms.

What you will learn

• How to scale complex products in high-volume OSAT environments, owning the full loop from test program bring-up to mature production.
• Advanced techniques in test coverage optimization, yield improvement, and cost reduction across wafer, package, and system-level test insertions.
• Practical application of automotive and advanced packaging quality flows, including reliability testing and JEDEC qualification in a production context.
• How to operate as a bridge between HQ product/test engineering and OSAT operations, influencing decisions on design-for-test, test strategy, and quality.
• Best practices in building institutional knowledge: documenting failure modes, debug methodologies, and structured improvement plans that shape future product generations.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an Advanced Packaging Process Engineer with experience in 2.5D and 3D chiplet packaging to join Tenstorrent’s Packaging team. You will drive advanced package technology and reliability in close partnership with foundries and OSATs, helping push performance and manufacturability for next‑generation AI/ML products.

This role is hybrid, based out of Santa Clara, CA or Taipei City, TW.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are 

• Advanced packaging engineer with hands-on 2.5D/3D experience (CoWoS-R/L, FOCoS, EMIB, FCBGA, organic substrates, silicon interposers, embedded Si/eCB, micro-bumps, BGAs).
• Strong in reliability and failure analysis for advanced packaging, including qualification, root cause analysis, and corrective actions.
• Deep understanding of process flows and materials (polyimide, ABF, core, underfill, mold compound) and their interactions (warpage, stress, delamination, mechanical risk).
• Proven track record working with foundries/OSATs on NPI, design rules, excursions, yield/cost optimization, and production ramp, with clear communication and cross-functional collaboration.

What we need 

• Own advanced package technology implementation for 2.5D/3D chiplet products, including technology choices, process integration, and manufacturability.
• Act as primary technical interface to foundries/OSATs: align capabilities and design rules, manage excursions, drive yield, define/track test vehicles, and coordinate FA.
• Partner with design, reliability, and architecture teams to evaluate tradeoffs (bump pitch, stack-ups, embedded Si, etc.) and lead test vehicle planning to meet program needs.
• MS/PhD in a relevant field (Materials, Mechanical, Electrical, Physics, or related) and 5+ years in advanced packaging for high-performance semiconductors from NPI through production (2.5D/3D flows such as CoWoS, FOCoS, EMIB, FCBGA or equivalent).

What you will learn 

• Deeper exposure to leading-edge 2.5D/3D packaging for high-performance AI/ML and chiplet-based architectures.
• How to balance performance-driven architecture with mechanical and reliability constraints to make robust package technology decisions.
• Ways to use AI- and automation-driven methods to accelerate risk assessment, qualification planning, and technical documentation.
• Best practices for building strategic OSAT and foundry partnerships that enable new capabilities while scaling reliable high-volume production.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.