We are looking for an ASIC Design Methodology Engineer to advance our design infrastructure and flows across RTL development, verification, and physical implementation. This role is ideal for engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate silicon success.

This role is hybrid, based out of Toronto, Ottawa, Austin, or Boston.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A strong advocate for design quality and productivity, with expertise in ASIC design flows.
• Skilled in RTL design and familiar with static and dynamic analysis tools.
• Comfortable automating design checks and improving methodology for scalability and reuse.
• A collaborative engineer who partners effectively across RTL, verification, and backend teams.

What We Need

• Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration.
• Own and evolve static code analysis (Lint, CDC, RDC, DFT) and RTL-netlist logic equivalency design methodologies
• Develop synthesis timing constraints (SDC) and low power design specifications (UPF)
• Support RTL-to-GDS flow enablement, ensuring clean handoffs and sign-off readiness.
• Collaborate with EDA vendors and internal tool owners to optimize performance, quality, and runtime.

What You Will Learn

• How large-scale AI SoCs are architected, integrated, and brought to silicon.
• How methodology choices directly impact design performance, power, and verification closure.
• How to build and scale ASIC design flows supporting cutting-edge compute architectures.
• How to integrate cross-functional workflows across design, DFT, DV, physical, and firmware teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an engineer who will focus on pre-silicon verification of DFD logic in advanced AI SoCs, driving coverage of debug, test, and bring-up features critical to silicon success.

This role is hybrid, based out of Boston, MA; Toronto, Ottawa; or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deeply curious about silicon debug/test infrastructure and its verification.
• Expert in UVM and verification of DFT/DFD features, scan, and on-chip trace logic.
• Comfortable working with Siemens Tessent flows, iJTAG, and advanced verification automation.
• Proactive, detail-oriented, and thrives in cross-functional technical discussions.
• Ideally familiar with tools similar to CocoTB

What We Need

• Develop and own verification environments for DFD logic across AI chiplets and SoCs.
• Write, refine, and execute test scenarios for scan, MBIST, array dump, and clock-stop features.
• Analyze coverage gaps, debug failures, and collaborate closely with DFT and RTL teams.
• Automate flows for JTAG/scanchain testing and integrate AI productivity tools.

What You Will Learn

• In-depth DFD/DFT verification using cutting-edge Tessent workflows and scripting.
• Integration of pre-silicon DFD verification with silicon debug strategies.
• How AI-driven automation reshapes modern DV workflows.
• Exposure to security-conscious debug methodologies in advanced SoC designs.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking a junior-to-mid level SOC Emulation Engineer to support our hardware emulation infrastructure and internal chip design teams. This role focuses on integrating vendor and custom hardware transactors, developing Python-based test frameworks, and providing technical support to emulation users across multiple chip projects.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Background in Electrical/Computer Engineering or Computer Science with 1-3 years of experience in chip design, verification, or emulation.
• Proficient in Python for automation and test development, with a working knowledge of C++ and the ability to navigate SystemVerilog RTL.
• Skilled at using modern AI tools (Claude, ChatGPT, Copilot) to accelerate code generation, debugging, and documentation analysis.
• Energetic about supporting diverse teams, from high-level software to low-level firmware, to solve complex runtime and build issues.

What We Need

• Ability to integrate vendor and custom transactors into RTL testbenches while handling clock domain and tri-state resolution.
• Experience building Python APIs (using pybind11) and maintaining CMake-based compilation flows for emulation libraries.
• Solid understanding of standard chip interfaces, bus protocols, and hardware synchronization (resets/clocking).
• A commitment to triaging and debugging the full stack, spanning from Python tests and C++ bindings down to hardware.

What You Will Learn

• Deepening your expertise with world-class platforms like Synopsys Zebu for massive-scale silicon validation.
• Gaining a holistic view of chip development by bridging the gap between hardware RTL and software drivers.
• Building and optimizing large-scale emulation build and run tooling for high-performance engineering teams.
• Refining your ability to gather requirements and facilitate communication between hardware designers and software engineers.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.