Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with industry-standard tools (FusionCompiler, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
• Experience driving physical design requirements from early architecture through final signoff.

What You Will Learn

• How to implement cutting-edge AI accelerators, high-performance CPUs and the SOCs that host them on the most advanced process nodes.
• Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
• End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
• Direct impact on products that are redefining the landscape of AI and high-performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a Physical Design Engineer – EMIR to join our silicon team. In this role, you’ll lead EM and IR-drop simulations to ensure robust power delivery, signal integrity, and long-term reliability for high-performance ICs. You’ll work with RTL, physical design, and analysis teams to implement power grid strategies that optimize performance, power, and area (PPA), particularly at advanced nodes like 7nm and below. You’ll also support EMIR sign-off and waiver methodologies across the chip hierarchy.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A physical design specialist with deep experience in EMIR analysis and signoff.
• Comfortable navigating advanced technology nodes and power integrity challenges.
• Proactive and detail-oriented, with a passion for pushing performance and reliability boundaries.
• Collaborative and effective across teams working on RTL, physical design, packaging, and reliability.

What We Need

• 7+ years of experience in physical design or signoff, with a focus on EMIR.
• Hands-on with RedHawk, Voltus, or equivalent industry-standard EMIR tools.
  Strong understanding of IR-drop mitigation, EM compliance, and power grid design.
• Proficiency with layout extraction flows, RC modeling, and metal density checks.
• Experience working in advanced nodes (7nm, 5nm, 3nm), and with scripting languages like TCL, Python, Perl, or Shell.
• Knowledge of floorplanning, bump/RDL design, and sign-off flows (DRC/LVS, timing closure).

What You Will Learn

• How to architect and analyze robust power delivery for Tenstorrent’s RISC-V CPUs and AI chips.
• How to integrate EMIR signoff into fast-paced, high-performance chip design cycles.
• Best practices for hierarchical analysis and EMIR methodology across pre- and post-layout flows.
• Cross-functional collaboration for optimizing PPA while meeting stringent reliability goals.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.
  
  

What We Need

• BS or MS in Engineering (Electrical, Electronics, or related field).
• 7–14 years of hands-on experience in CPU/IP/SoC physical verification.
• Strong command of industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification.
• Solid understanding of advanced node challenges (7nm, 5nm, 3nm) and FinFET design considerations.
• Scripting proficiency (Python, TCL) for automation and flow optimization.
• Familiarity with ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).
  
  

What You Will Learn

• Advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Integration and verification strategies for full-chip signoff across advanced process technologies.
• Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.
  
  

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an exceptional Senior-level SoC Physical Design Engineer to drive top-level implementation of our complex AI and CPU SoC designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Ft. Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned physical design engineer who thrives on complex, full-chip implementation challenges.
• Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams.
• Passionate about optimizing chip-level implementations for power, performance, and area.
• Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules

What We Need

• 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
• Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
• Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
• Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.

What You Will Learn

• How to implement cutting-edge AI accelerators and high-performance CPUs at the SOC level.
• Advanced techniques for chiplet integration and next-generation packaging co-design.
• Strategies for optimizing massive designs with complex power domains and clock architectures.
• Methods for driving successful chip-level closure through effective cross-functional collaboration.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.