Our Tensix team is building custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI. Design Verification Engineers on this team validate compute IP and subsystems and build scalable DV infrastructure to keep verification fast, automated, and production-grade.

This role is hybrid, based out of Toronto, ON or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in modern verification methodologies with strong SystemVerilog skills and exposure to structured testbench development.
• Comfortable working from block-level to system-level verification and reasoning about microarchitecture behavior from specs and waveforms.
• Proficient in Linux environments with Python, or Bash scripting for automate builds, parse logs, manage CI pipelines.
• Skilled in coverage-driven verification and confident debugging across RTL, testbench, and workload scenarios.
• Motivated by AI hardware and eager to learn verification strategies for new architectures and domains.

What We Need

• Contribute to verification of Tensix IP and subsystems from early planning through tape-out, owning coverage goals and driving them to closure.
• Build and maintain reusable verification environments, agents, scoreboards, and supporting infrastructure in SystemVerilog and Python.
• Develop constrained-random and directed tests and close functional, code, and assertion coverage using data-driven approaches.
• Debug complex issues across RTL and testbench while collaborating with design, firmware, compiler, and architecture teams.
• Help evolve DV infrastructure including regression flows, CI/CD integration, EDA compute environments, and reproducible setups.

What You Will Learn

• How Tenstorrent verifies AI-native compute architectures including Tensix cores, RISC-V CPUs, matrix units, vector units, and datapath.
• How simulation, emulation, and software-driven workloads combine to validate both functional correctness and performance.
• How numerical precision formats such as BF16, FP4, and INT8 and on-chip dataflow impact verification complexity and coverage strategy.
• How to build scalable DV infrastructure across hybrid compute environments including containerized regression systems.
• How data analytics and modern AI tooling can enhance verification workflows and accelerate convergence.

Our Tensix Team is building the next generation of high-performance AI compute systems. We’re looking for a Power Architect to drive architectural strategy, modeling, and design decisions that shape how power is understood and optimized across our products. This is a hands-on role with massive influence over how we build power-aware systems from the ground up.

This role is hybrid, based out of Toronto, ON or Austin, TX.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• 10+ years experience with power estimation tools like PowerArtist, PtPX, RTL Architect, and PrimePower.
• Skilled in modeling and optimizing power at the architectural level, with deep knowledge of power-gating, voltage domains, and leakage control.
• Track record of influencing architectural and micro-architectural changes that meaningfully reduced design power.
• Proficient in Verilog HDL, Design Compiler, C/C++ and Python.
• Background in power-optimization of compute datapath  and/or interconnects.

What We Need

• Predict power consumption early in architecture and track it through RTL evolution.
• Propose architectural changes for power optimization across server and non-server markets.
• Build workloads that stress real-world use cases and guide thermal and power-delivery solutions.
• Correlate pre-silicon estimates to silicon measurements and drive power efficiency improvements.

What You Will Learn

• How AI workloads impact power at every layer of the stack — from circuit to software.
• Challenges in building accurate, CI-integrated power modeling infrastructure.
• Techniques for aligning design tradeoffs to the realities of AI model execution.
• How Tenstorrent approaches full-stack power optimization across chiplet-based systems.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors. As we push performance boundaries, we’re reimagining the frontend of our RISC-V cores to deliver major gains in programmability, efficiency, and developer experience. This is a rare opportunity to shape the CPU architecture at the heart of our AI platform and lead one of the most strategic technical efforts at Tenstorrent.

This role is hybrid, based out of Toronto, ON or Austin, TX.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced architect with over 10 years in CPU performance modeling and microarchitecture.
• Proficient in C++ and Python, with a strong understanding of RISC-V instruction-set.
• Well versed in compiler design and how software stacks impact CPU performance and programmability.
• Familiar with open-source RISC-V cores and LLVM toolchains, including adding custom optimization passes.

What We Need

• Analyze AI workloads to identify CPU performance requirements and bottlenecks.
• Architect custom RISC-V CPU cores optimized for performance, power, and area.
• Design custom instructions that improve performance without sacrificing programmability.
• Collaborate across compilers, software, and hardware teams to co-design Tenstorrent’s next-gen compute architecture.

What You Will Learn

• How modern AI models stress CPU architecture and influence design decisions.
• The interplay between compiler design, CPU microarchitecture, and real-world performance.
• How Tenstorrent’s unified hardware-software stack enables breakthrough performance for general-purpose AI compute.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The Tensix team is building the high-performance compute fabric that powers Tenstorrent’s AI and ML workloads. As an AI Performance Architect, you will model, analyze, and optimize how real AI workloads run on the Tensix architecture, shaping future hardware features and ensuring every design decision delivers measurable performance gains. This role connects architecture, software, and RTL to push the limits of efficiency and scalability across next-generation AI systems.

This role is hybrid, based out of Toronto, ON; Austin, TX; or remote.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deeply analytical engineer with strong intuition for AI workload behavior and system-level performance bottlenecks.
• Experienced in C++ and Python for simulation, modeling, and performance analysis across heterogeneous compute systems.
• Adept at bridging software and hardware teams—translating deep learning workloads into architectural insight and measurable design tradeoffs.
• Curious, data-driven, and comfortable pushing the limits of efficiency, scalability, and accuracy in high-performance AI systems.
  
  

What We Need

• Benchmark and analyze complex AI workloads across single and multi-node hardware configurations to guide next-gen architecture.
• Develop and maintain performance models, simulators, and micro-benchmark suites to drive feature evaluation and design optimization.
• Conduct detailed PPA (Performance, Power, Area) studies to assess design tradeoffs and inform hardware-software co-design decisions.
• Collaborate closely with RTL, Compiler, and Runtime teams to instrument and correlate performance models with silicon results.
  
  

What You’ll Learn

• Advanced modeling techniques for large-scale AI systems, including multi-chip and distributed performance analysis.
• How architectural choices propagate through the software stack—from compiler and runtime layers down to custom AI accelerators.
• Emerging deep learning trends and their impact on compute architecture design and performance tuning.
• How to define and validate performance features that directly translate to measurable gains across real-world AI workloads.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.