Principal Engineer, SOC Design

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Job ID:  42866

Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy

• Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
• Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
• Reviews 3^rd party IPs including ARM cores, DDR controller, and UCIe PHY 
• Responsible for integrating the third part IPs and sub system at top level
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

What You Bring

• Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
• Highly motivated with good verbal and written communication skills.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
• Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
• Good understanding of PPA (performance, power, and area) trade-offs.
• Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
• Experience in interfacing 3^rd party service companies for DFT/PI/PD.
• Good knowledge and experience in AMBA bus fabric, ARM cores.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Memory IO Lab is part of Samsung’s Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume. Memory IO’s vision is to provide memory interface technology solutions which can be adopted in DDR, LPDDR, GDDR, and more. We are an integral part of Samsung’s paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps.

Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy

What You'll Do

• Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES.
• Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary.
• Ownership of circuit and system specifications.
• Simulate designs with state-of-the-art CAD tools.
• Document designs and simulation results.

What You Bring

• BS 10+ years experience, MS 8+years of experience, PhD 5+ years experience in Electrical Engineering, Computer Science preferred. 
• 5+ years of experience working with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes.
• Prior experience in design of any one of the standard high speed interfaces like DDR, LPDDR, , GDDR, HBM I/O interface.
• Needs to be an expert in providing and understanding layout requirements of high speed circuits.
• Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design.
• Experience working closely with device/process team to define transistor specs
• The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
• Ability to troubleshoot and analyze complex problems.
• Excellent communication (written and verbal) and interpersonal skills
• Experience in high frequency clock distribution design, implementation, and analysis.
• Deep understanding of PPA (performance, power, and area) trade-offs.
• Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools
• Experience on silicon bring-up and automatic measurement using script
• Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SoC Architecture team is involved in  SoC‑level designs for emerging memory/storage solutions and validates each design’s feasibility with hands‑on RTL implementation. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

This role offers the opportunity to shape next-generation SoC and subsystem architectures while staying deeply hands-on in RTL design, integration, and validation. It is ideal for engineers who want to turn advanced memory and storage concepts into real hardware and drive them all the way to silicon

Job ID: 42896

Location: Daily onsite presence at our Folsom office in alignment with our Flexible Work policy

• Collaborate with architecture, design, verification, and system teams to define and implement SoC features and subsystems
• Translate architectural requirements into microarchitecture, RTL design, and verification plans
• Design and develop RTL for SoC blocks and integration logic using SystemVerilog/Verilog
• Drive block- and SoC-level integration activities, including clocking, reset, power intent, interfaces, and configuration infrastructure
• Analyze performance, power, area, and timing tradeoffs to deliver efficient and scalable designs
• Support design verification by debugging issues found in simulation, emulation, formal analysis, and silicon validation
• Participate in pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis and issue resolution
• Contribute to technical documentation, block specification, test plans, and design reviews

What You Bring

• Bachelors in Electrical, Computer Science or related with 15+ years of experience or Masters in Electrical, Computer Science or related Science with 13+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 10+ years of Industry experience preferred.
• Strong technical background in SSD architecture and storage technologies, including controller architecture, NAND/flash behavior, data path design, and system performance consideration. 
• Familiarity with DRAM architecture and memory subsystem design, including memory hierarchy, bandwidth/latency tradeoffs, buffering, and traffic behaviors. 
• Experience with data integrity and protection mechanisms, such as ECC, parity, CRC, RAID, and end-to-end data protection schemes. 
• Experience contributing to complex hardware products from architecture definition through RTL implementation, verification, and silicon bring-up. 
• Proven ability to collaborate effectively across architecture, design, verification, firmware, and validation teams. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1