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Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
What You’ll Do
The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SoC Architecture team is involved in SoC‑level designs for emerging memory/storage solutions and validates each design’s feasibility with hands‑on RTL implementation. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.
This role offers the opportunity to shape next-generation SoC and subsystem architectures while staying deeply hands-on in RTL design, integration, and validation. It is ideal for engineers who want to turn advanced memory and storage concepts into real hardware and drive them all the way to silicon
Job ID: 42896
Location: Daily onsite presence at our Folsom office in alignment with our Flexible Work policy
- Collaborate with architecture, design, verification, and system teams to define and implement SoC features and subsystems
- Translate architectural requirements into microarchitecture, RTL design, and verification plans
- Design and develop RTL for SoC blocks and integration logic using SystemVerilog/Verilog
- Drive block- and SoC-level integration activities, including clocking, reset, power intent, interfaces, and configuration infrastructure
- Analyze performance, power, area, and timing tradeoffs to deliver efficient and scalable designs
- Support design verification by debugging issues found in simulation, emulation, formal analysis, and silicon validation
- Participate in pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis and issue resolution
- Contribute to technical documentation, block specification, test plans, and design reviews
What You Bring
- Bachelors in Electrical, Computer Science or related with 15+ years of experience or Masters in Electrical, Computer Science or related Science with 13+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 10+ years of Industry experience preferred.
- Strong technical background in SSD architecture and storage technologies, including controller architecture, NAND/flash behavior, data path design, and system performance consideration.
- Familiarity with DRAM architecture and memory subsystem design, including memory hierarchy, bandwidth/latency tradeoffs, buffering, and traffic behaviors.
- Experience with data integrity and protection mechanisms, such as ECC, parity, CRC, RAID, and end-to-end data protection schemes.
- Experience contributing to complex hardware products from architecture definition through RTL implementation, verification, and silicon bring-up.
- Proven ability to collaborate effectively across architecture, design, verification, firmware, and validation teams.
- You’re inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.
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When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
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