What You’ll Do

As a seasoned Senior Technical Project Manager (ASIC) you will lead complex silicon development projects from specification definition through tape-out, fabrication, and post-silicon validation. You will be the primary face of Samsung’s (SLSI’s) ASIC design, verification, physical design, firmware, foundry and advanced packaging teams to the customer and ensure the timely delivery of all collateral. This role requires a strong technical background in semiconductors combined with exceptional program management skills to navigate risks and drive execution excellence.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Reports to: Team leader/Head of Custom SoC Solutions Team.

Job ID: 42809

Key Responsibilities

• End-to-End Program Ownership: Work with customers from initial concept and specification stage to silicon tape-out, bring-up, and production. This includes not only technical, but also spans commercial and legal domains.
• Project Planning & Scheduling: Develop and maintain detailed project plans, milestones, and resource allocation. Proactively identify and resolve bottlenecks and critical path issues.
• Cross-Functional Coordination: Collaborate with Architecture, RTL, Verification, Physical Design (PnR), DFT, Firmware, Emulation and Packaging teams to ensure aligned deliverables. Participate in cross functional meetings and identify and eliminate bottlenecks.
• Risk Management: Proactively identify risks and develop mitigation plans to avoid tape-out delays. Hold the development teams accountable for the scheduled quality deliverables.

 What you bring

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 15+ years or a Master’s degree with 13+ years.
• Experience: 10+ years in the semiconductor industry, with at least 5+ years in technical program/project management for ASIC/SoC products.
• Technical Knowledge: Deep understanding of the full ASIC design flow (RTL, Simulation, Synthesis, STA, PnR, DFT, Tape-out).
• Methodologies: Proven experience working with advanced process nodes and high-speed design.
• Tools: Proficiency in project management tools (Jira, Confluence, MS Project) and familiarity with EDA tools (Synopsys, Cadence).
• Experience with complex packaging (2.5D/3D IC, Si interposers, TSV).
• Knowledge of automotive functional safety and other automotive industry requirements
• Experience with hardware emulation platforms (Palladium, Veloce, ZeBu).
• Leadership: Strong ability to influence cross-functional teams without direct authority.
• Problem-Solving: Ability to analyze technical problems and drive solutions in a fast-paced environment.
• Communication: Excellent verbal and written communication skills, tailoring technical information for various stakeholders.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

We are seeking a Technical Marketing Senior Manager to join our System LSI - Custom SoC Sales and Business Development Team in San Jose, CA.  In this role, you will be responsible for identifying new opportunities for custom SoC (ASIC) business, conducting pre-shaping activities including technical requirements review and commercial discussions with potential customers, and building relationships with customers across the US market. This customer-facing role is highly cross-functional, where you will also manage day-to-day account management activities on both the technical and business sides with internal and external teams. We are seeking a high- energy professional with strong communication skills towards internal stakeholders and customers, as well as the ability to lead and develop new processes and ideas.  The successful candidate will thrive in a fast-paced, dynamic environment and be able to develop strategic relationships with customer teams. 

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy

Job ID: 42912

What You’ll Do

• Support the design-in activities and business operations by working with cross-functional teams across Engineering, Sales and Marketing teams to secure customer engagements.
• Act as local support interface for US customers for existing accounts and ongoing programs.
• Engage in engineering & commercial discussions with customers.
• Market survey and developing new customers and applications.
• Act as local POC for engineering/commercial VOC collecting and leading issue resolving by circling back internally with right internal POC.
• On-going and future projects reporting to both US and Korea Executives.
• Build relationships with internal stakeholder teams such as Marketing, Sales, Product Planning and development teams to know and understand S.LSI’s differentiated offerings and strategies.
• Work with customer teams to map their requirements to S.LSI offerings, identify potential gaps, and champion their cause by driving internal development teams to address their needs and deliver technical solutions.
• Develop and build relationships with customers’ teams to understand their technology needs, application requirements and jointly define the best silicon/platform solutions to enable customer’s products.

What You Bring

• Highly Technical Background with deep business acumen and the ability to synthesize technical and business information into clear, compelling executive-level presentations that influence internal and external stakeholders.
• Bachelor’s Degree in Engineering, Business, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• Technical sales and/or Marketing experience, management experience, technical/customer program management, or field applications engineering experience.
• Both Pre and Post Sales Customer Support.
• Good understanding of Semiconductor Industry, especially in SoC (System on Chip).
• Understanding or past experience with ASIC design and manufacturing flow, including advanced packaging is a Plus.
• Ability to analyze customer’s problem and needs from the component to system and application level based on customer’s requirements and purpose the solution that maps out to Samsung LSI’s offering.
• Frequent work and meetings are required with Korea.
• Korean language proficiency is a plus but not required.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

What You’ll Do

The Sr. Manager, Foundry Strategic Design Alliances & Ecosystem Sales will report to the Head of Foundry Strategic Design Alliances & Ecosystem Sales, and will focus on building a customer pipeline to scale the revenue associated with (i) Samsung Foundry’s Design Solution Partners (DSPs) and (ii) other strategic design houses, to further expand Samsung Foundry’s North America business. 

This position is based in San Jose, CA, USA but will require extensive collaboration across the organization, including with sales/account managers, business development, design ecosystem and counter-parts in Headquarters as well as external Design Solution Partners (DSPs). 

The candidate will be the primary link between Samsung Foundry and the US design community. Your mission is two-fold: (i) Scale the revenue and technical capability of our existing Design Solution Partners (DSPs) and (ii) identify strong non-DSP Strategic Design Houses to pull into high-value projects. You will own the commercial and operational success of multiple design projects from the initial pitch (Pre-D/A) to the final silicon delivery (Post-D/A).

The successful candidate should have the key skills required for the job, including strong business strategy formulation with customers and external partners, with solid understanding of the semiconductor foundry, ASIC and OSAT landscape.  Additionally, the candidate must be comfortable solving problems even when data is incomplete, as well as working in a fast-paced and dynamic environment. 

Location: Onsite at our San Jose headquarters 5 days a week with an average of 10 % travel per month

Reports to: Sr Dr, Foundry Business Strategy 

• Drive incremental revenue specifically through DSP/Strategic Partner engagements
• Lead the 3-way communications/negotiations between Samsung Foundry, design partner, and the end-customer to secure design awards.
• Lead monthly meetings and yearly business review meetings with DSP leadership to align on project status, sales targets and resource allocation for Samsung-bound projects
• Own the technical and commercial proposal, ensuring PPA targets and NRE costs are competitive and realistic
• Act as the executive account manager through the design flow, after securing the design-award
• Ensure the design house stays on track for tape-out and manage the hand-off to the fab. If a project hits a snag in physical design or sign-off, you are the first responder
• Drive strategy alignment with Headquarters counterparts plus execute and track overall progress
• Understand overall ASIC and Design House competitive landscape especially for advanced technology node (14nm and below)
• Qualify new business opportunities with the DSPs and formulate joint opportunity attack plan
• Support creation of CEO/EVP and board-level analysis for strategy meetings.
• Complete other responsibilities as assigned.

What You Bring

• Bachelors in Electrical Engineering, Physics, or related Physical Science with 10+ years of experience or Masters in Electrical Engineering, Physics or related Physical Science with 8+ years of Industry Experience in Electrical Engineering, Physics, or related Physical Science with 7+ years of Industry Experience Preferred.  Master in Business Discipline with Engineering-related degree is a PLUS!
• Semiconductor industry experience, with exposure to system designs, semiconductor foundry, design services, ASIC and EDA or IP business.
• Knowledge of Processors and ASICs used in hyperscale data centers, AI ASICs, Automotive and other emerging end markets
• Excellent communicator with good personality
• Solid PowerPoint and presentation skills
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding
• You’re excited about leading complex, multi-party negotiations and you know how to align incentives so that everyone (SF, DSP, customer) feels like they won
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-KS1

Principal Engineer, SOC Design

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Job ID:  42866

Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy

• Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
• Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
• Reviews 3^rd party IPs including ARM cores, DDR controller, and UCIe PHY 
• Responsible for integrating the third part IPs and sub system at top level
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

What You Bring

• Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
• Highly motivated with good verbal and written communication skills.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
• Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
• Good understanding of PPA (performance, power, and area) trade-offs.
• Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
• Experience in interfacing 3^rd party service companies for DFT/PI/PD.
• Good knowledge and experience in AMBA bus fabric, ARM cores.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Responsibilities and Description: 

The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. 

Required Qualifications: 

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Minimum 5 years of experience in digital physical design and verification.
• Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff.
• Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification.
• Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
• Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
• Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell.

Preferred Qualifications: 

• Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. 
• Experience in DFT (Design For Test) flows and ATPG.
• Experience in I/O design flow in multi-voltage power domain.
• Experience in building chip floor-plan including pin placement, partitions and power grid.
• Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints.
• Experience with build tools such as CMake and Bazel.
• Experience with code coverage and regression setup.

THE ROLE

Join the Systems Software team to architect and deliver the core software powering the industry's most innovative, high-availability storage platforms. You will lead the development of mission-critical system components, transforming complex hardware-software integration challenges into seamless, zero-downtime customer experiences. By collaborating with hardware and cross-functional software teams, you will define the future of enterprise data storage and ensure our platforms remain at the cutting edge of performance and reliability.

WHAT YOU'LL DO

• Architect High-Performance Networking: Drive the end-to-end design and debugging of C/C++ networking software to ensure next-generation switching and fabric platforms meet rigorous scalability and resiliency benchmarks.

• Own Core Protocol Development: Deliver critical Layer 2 and Layer 3 features—including forwarding behavior and control-plane protocols—that simplify operations for global enterprise customers.

• Lead Hardware-Software Integration: Partner with ASIC vendors and internal platform teams to implement switch SDK functionalities, ensuring robust hardware interfaces and successful in-service software upgrades (ISSU).

• Innovate with Open Networking: Design and customize SONiC-based solutions across the control and data planes to enhance our disaggregated network operating system capabilities.

• Drive Technical Excellence: Act as a technical mentor and lead for complex initiatives, setting the standard for code quality and architectural decisions across cross-functional networking efforts.

• We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.

WHAT YOU BRING

• Systems Programming Expertise: Advanced proficiency in C/C++ (C++11+) with a track record of building and debugging performance-sensitive systems software or networking applications.

• Deep Networking Domain Knowledge: Mastery of Layer 2 and Layer 3 protocols (Ethernet, VLANs, BGP, ECMP) and the ability to translate these complex behaviors into production-ready code.

• Hardware Interfacing Skills: Practical experience working with switch SDKs or Linux networking internals (kernel concepts, drivers, or packet processing) to interact directly with ASIC capabilities.

• Availability-Focused Engineering: Understanding of non-disruptive upgrade (NDU) technologies and the architectural discipline required to build systems that minimize customer impact during maintenance.

• Collaborative Technical Leadership: Ability to independently drive complex problem-solving and influence technical direction across multiple teams while mentoring junior engineers.

 #LI-ONSITE

ABOUT THE JOB

We are looking for a FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA. You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification. This will require expertise in SystemVerilog, object-oriented programming, and UVM. If you are someone who has supported rapid avionics development, then this role is for you.

WHAT YOU’LL DO

• Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs
• Develop verification plans with traceability to system and hardware requirements
• Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks
• Build functional coverage models and drive code coverage analysis to closure
• Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs
• Establish and maintain regression suites, tracking coverage metrics and verification progress
• Debug failures using waveform tools and simulation logs at the HDL and system level
• Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement
• Support hardware validation and board bring-up on target platforms
• Ensure verification meets DO-254 and relevant safety standards
• Author verification closure reports and coverage analysis summaries

REQUIRED QUALIFICATIONS

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
• 2+ years of experience in FPGA/ASIC verification
• Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches
• Object-oriented programming principles
• Industry simulators (Questa, VCS, Xcelium, or Vivado)
• Git-based collaborative workflows including code review
• Linux development environments
• Strong communication and teamwork skills
• Eligible to obtain and hold a U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• 5+ years of experience in FPGA/ASIC verification
• Master’s degree in Electrical Engineering, Computer Engineering, or related field
• DO-254, avionics verification standards for UAS, and safety-critical verification processes
• SVUnit or equivalent unit-testing frameworks
• Formal verification or CDC verification tools
• Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI
• Verification automation scripting (Python, Tcl, Makefile)
• SoC and ARM-based embedded platforms
• Verification automation, CI/CD integration, and Nix-based build environments

ABOUT THE TEAM

The Air Dominance and Strike (AD&S) Electrical Engineering Team is responsible for developing high-reliability avionics, embedded processing, and power systems for Group 5 air vehicles and missile platforms. Working across hardware, software, and mission autonomy, the team delivers flight-critical electronics, PCB assemblies, and FPGA-based processing architectures that enable Anduril's next-generation autonomous air platforms to operate in complex and contested environments. AD&S Electrical Engineers drive end-to-end development, from system architecture and circuit design to verification, integration, and flight test, ensuring scalable, mission-ready solutions that meet the performance, reliability, and survivability demands of the U.S. Military and modern air warfare.

ABOUT THE JOB 

We are looking for an Senior Electrical Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be responsible for end-to-end avionics systems and subsystems development. You will also be working on design, integration, testing, and validation processes. This will require knowledge and experience in PCB design, harnessing, process management, and cross-functional teamwork. If you are looking to join a team in rapid avionics development, then this role is for you.

WHAT YOU’LL DO

• Develop high performance, high efficiency, and highly robust avionics solutions for air vehicle platforms
• Develop reliable on-board communication systems to exchange high bandwidth data across various air and ground assets
• Architect, design, and build high-speed digital PCBAs (schematic capture, simulation, board layout)
• Help decide what to do in-house and what to outsource, communicate design requirements with external vendors and help drive the progress
• Develop relationships with external vendors and communicate design requirements to external vendors and suppliers.
• Work cross-functionally between software, firmware and hardware teams
• Develop hardware validation test plans for sub-system and full system products.

REQUIRED QUALIFICATIONS

• Bachelor’s degree in Electrical Engineering, or a closely related field.
• 8+ years relevant experience in electrical hardware design.
• Experience designing high density PCB layouts with an understanding of cutting-edge PCB manufacturing technology.
• Deep understanding of thermal, mechanical, power and performance tradeoffs.
• Experience with creating test plans, benchmarking and performing validation tests to determine performance of complex hardware systems.
• Understanding of high-speed interfaces (PCIe, DDR, USB, MIPI, etc.), power integrity, and signal integrity.
• Knowledgeable of EMI/EMC susceptibility and emissions along with mitigation experience.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

PREFERRED QUALIFICATIONS

• Experience with high performance SOMs (System On a Module).
• Experience in developing FPGA and ASIC architectures.
• Experience with rapid, hands-on prototyping.
• Skilled at soldering and reworking microelectronic components.
• Knowledgeable in RF investigation and analysis with the use of specialized equipment (Spectrum analyzer, Network Analyzer, etc) and RF simulation tool suites.
• Knowledge of state-of-the-art hardware systems, software tools and algorithms for interfaces required for sensors, actuators, firmware development, and inter-communication bus protocols (CAN-FD, Ethernet, SFP, 1553, etc).
• Experience using Linux command line interface (CLI).

Anduril’s Electrical Engineering Team is seeking a Wireless Systems Principal Engineer with a strong background in modulation/demodulation, forward error correction, multiple access, duplexing schemes used in wireless communications. In this role, you design, adapt, and optimize wireless communication waveforms for use by autonomous vehicles to communicate with each other and with human operators.  Familiarity with tradeoffs concerning performance, resiliency and range is necessary.  You will also work with embedded SW and FPGA engineers to optimize capability while maintaining the big picture mission and system view with an eye to both verification and validation of the end system. Additionally, you will guide the SW and FW engineers to develop SW/FW/HW to integrate wireless systems with autonomous vehicles and their controllers.  The preferred person for this role has a strong background in the effects of signal processing, communication systems architectures upon the users that rely upon them. Additionally, experience in providing technical approach to System Engineers, FPGA and SW engineers, and schedule status including work estimates and staff resource estimates to program management is preferred.  Substantial experience in the use of Matlab for waveform, network, and traffic design and simulation is highly preferred.

WHAT YOU’LL DO

• Guide embedded SW engineers and FPGA engineers in trade studies, implementation and optimization of waveforms to the autonomous applications.
• Collaborate with a multidisciplinary team of systems, software, firmware and hardware engineers to support integration activities.

REQUIRED QUALIFICATIONS

• Strong, demonstrated leadership of DSP engineers in the comms sector to include technical and programmatic leadership aspects - demonstrated ability to understand simple and innovative algorithms and work with program management, software and firmware groups to deliver compelling capabilities
• Familiarity with design of Modulation, Demodulation, Error Correction Schemes, Symmetric and Asymmetric Encryption and their affects on systems that use them.
• Familiarity with CSMA, CDMA, TDMA, FDMA, FDM, TDM, DAMA and similar communications protocols and their affect on throughput, system capacity, jitter, latency, and link integrity
• Familiarity with DSSS, FHSS, Chirp Spread Spectrum, OFDM, PSK, FSK, and similar modulation systems and their affects on links that use them.
• Experience with deceiver design parameters including: AGC, Frequency and Phase correction, DC and I/Q offset compensation, equalization, ACI and CCI mitigation
• Familiarity with MATLAB and/or Simulink.
• Experience with embedded devices for DSP, including FPGA, GPU, ASIC, and/or Software Defined Radios and the tradeoffs between which is best for what circumstances.
• Demonstrated algorithm design and implementation
• Ability to analyze and simulate algorithm performance and present findings to audience without deep technical knowledge of subject
• Familiar with commercial and/or military wireless and satellite communication standards
• Enthusiastic about both working with a team and executing DSP work individually
• Some travel required especially for review prep, reviews and integration activities, roughly 25% on average
• Must be able to obtain and hold a U.S. security clearance

PREFERRED QUALIFICATIONS

• BSEE or higher with an emphasis on Digital Signal Processing and/or information theory and practical experience
• MIMO, phased array, and beamforming experience
• Strong experience with DSP implementation for embedded devices and/or software defined radios
• Demonstrated technical task leadership of embedded SW and FPGA engineering and interfacing with program management
• Systems Engineering and mission analysis experience

At Tenstorrent, die-to-die (D2D) interfaces are how we stitch chiplets together into scalable AI and RISC‑V systems, delivering the bandwidth, latency, and power efficiency our architecture demands. As these links push signaling, process, and packaging limits, we rely on robust analog design automation to explore architectures quickly, verify complex corners, and deliver reliable Silicon at scale.

In this role, you will help build and refine automation that our analog designers use every day to design, simulate, and validate D2D PHYs. Your work on flows, scripts, and analysis frameworks will directly impact how fast we can iterate on D2D interfaces, how confidently we can sign them off, and ultimately how Tenstorrent connects and scales its next-generation AI hardware.

This role is hybrid based out of Toronto, Boston, Austin or Santa Clara (preferred). 

Who You Are

• A flexible thinker who is excited by the future of AI and eager to work at the boundary between analog circuits and advanced packaging.
• Strong proficiency in Python code conventions
• A curious and motivated student eager to connect the dots between Analog IC design, Data Analytics, and AI/ML tools.
• Interested in how architectural ideas become silicon products and how automation can accelerate the design cycle.

What We Need

• A co-op or PEY student pursuing a BS/MS/PhD in Electrical Engineering with academic exposure to Analog IC design.
• Interest in or academic exposure to Machine Learning concepts (e.g., data analysis, basic model training, optimization).
• Interest in applying Open Source packages and tools to analog design automation problems.
• Strong analytical thinking and communication skills.

What You’ll Learn

• Analog design challenges and solutions in modern FinFET processes.
• Deploy SW for HW Design Automation
• Collaborate with senior Analog and Design Automation engineers to gain insight into the full ASIC design methodology and how automation drives product success.

Compensation for all interns at Tenstorrent ranges from $35/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day remote. 

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Santa Clara, CA or Austin, TX

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM.
• You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
• You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams.

What We Need

• Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
• Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

What You Will Learn

• How to drive DFT for industry-leading AI/ML architectures, working on high-performance chips with aggressive performance and power targets.
• Practical strategies to reduce test cost while maintaining coverage, and to design DFT hooks that accelerate silicon bring-up and yield learning.
• How to minimize DFT intrusions while integrating cleanly with RTL, verification, physical design, and production test flows.
• How a senior, cross-functional ASIC team collaborates across design, PD, verification, and manufacturing to achieve first-pass silicon success on advanced nodes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will own end-to-end technical engagements, translating complex architectural advantages into customer wins while shaping our product roadmap through direct market feedback. If you combine deep technical expertise with exceptional customer engagement skills and want to drive the adoption of next-generation compute IP, join our team.

This role is hybrid, based out of the United States or Canada near one of our main office locations.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with proven success in CPU/GPU/NPU IP sales engagements.
• Technical expert who can articulate complex architectural benefits and conduct deep-dive analyses.
• Self-driven professional who independently manages multiple customer relationships from discovery to win.
• Strategic thinker who identifies customer pain points and positions solutions effectively.

What We Need

• 7+ years in the semiconductor industry with a degree in EE or related field including customer-facing roles in CPU IP.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Deep technical knowledge of CPU architectures, semiconductor technologies, and system-level design.
• Exceptional presentation and communication skills with ability to engage all organizational levels.
• Proven track record of technical wins and managing multiple simultaneous accounts.

What You Will Learn

• How to position cutting-edge RISC-V and AI accelerator IP against industry incumbents.
• Advanced customer engagement strategies for complex technical sales in the semiconductor industry.
• Direct influence on product development through customer feedback and market insights.
• The complete IP business cycle from evaluation through design win and production success.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with industry-standard tools (FusionCompiler, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
• Experience driving physical design requirements from early architecture through final signoff.

What You Will Learn

• How to implement cutting-edge AI accelerators, high-performance CPUs and the SOCs that host them on the most advanced process nodes.
• Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
• End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
• Direct impact on products that are redefining the landscape of AI and high-performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade-offs and verification. A background in electrical engineering, electronics or relevant fields is required. Must love all things high speed!

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above (e.g. 100GbE, GDDR6, PCIe Gen5+).
• You’re comfortable working with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT as well as knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards.
• You are proficient with PCB ECAD tools (ideally Cadence Allegro).
• You communicate clearly (written and verbal), think critically, and love solving complex signal integrity problems.
• You’re enthusiastic about all things high speed and enjoy collaborating across teams

What We Need

• Design, extract, and simulate complex breakout structures, including end-to-end simulations and validation against physical hardware. Perform simulation and extraction of board models for both SI and PI.
• Contribute to design and sign-off with internal and external ASIC packaging teams, ODMs, and internal layout teams. Create design specifications, work with external vendors, and drive adoption of new interconnect and packaging technologies.
• Actively participate in design reviews, providing insight from your SI/PI expertise and a broader system perspective.
• Support post-silicon bring-up and help troubleshoot production and field failures related to signal and power integrity. Document design processes and provide training/knowledge sharing to other team members.

What You Will Learn

• How to work at the cutting edge of high-speed interconnects, influencing the next generation of ASIC packaging and PCB architectures.
• Deep exposure to advanced ASIC packaging flows and collaboration models with internal and external packaging teams.
• Hands-on experience with emerging high-speed connector technologies and materials, including evaluating material trade-offs for performance and manufacturability.
• Best practices for end-to-end SI/PI validation, from simulation through to lab correlation, post-silicon bring-up, and field failure analysis.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Who we are

Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.

As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.

What you will be doing

We are seeking a highly skilled CODEC Video Compression Engineer/Developer to build low cost FPV digital video, similar to DJI 04.

They will design, optimize, and implement low-latency advanced video compression algorithms while maintaining high visual quality, for real time video streaming application. You will work closely with cross-functional teams to deliver high-quality, low-latency wireless video. This role blends deep knowledge of video processing, mathematics, and software/hardware optimization to enable video transmission with minimum latency and reduced bandwidth usage.

Responsibilities

• Design and implementation of dual CPU/GPU hybrid video compression encoder architecture that can seamlessly combine SW and HW encoding engines
• Design, develop, and optimize video compression algorithms in C/C++, Assembly, Rust or similar languages
• Implement and optimize encoder/decoder pipelines for real-time applications
• Analyze and improve codec performance for speed, quality, and efficiency across CPU, GPU
• Perform error handling
• Conduct performance benchmarking, debugging, and quality assurance testing: Develop and use objective and subjective metrics to evaluate codec performance
• Collaborate with hardware and software teams to integrate CODEC solutions into products, using high-level synthesis, or FPGA/ASIC design flows
• Stay updated on emerging video standards, compression techniques, and industry trends

You should have the following

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field
• Solid understanding of video compression theory, motion estimation, transform coding, MC DCT, VBSMC, entropy coding, and rate control
• Codec implementation experience in developing actual software and hardware that encodes and decodes video data according to a specific compression format
• System Verilog experience (HLS/C++)
• Solid understanding of video compression standards (H.264, H.265/HEVC, H.266, VP9, AV1) and rate control algorithms
• Experience with hardware implementations using dedicated chips (FPGAs, ASICs, DSPs), and hybrid implementations using software for control logic with hardware accelerators GPUs (NVENC, NVDEC). Experience with GPU acceleration (CUDA, Vulkan, OpenCL)
• Strong proficiency in C/C++ and experience with SIMD optimizations (SSE, AVX, NEON)
• Front-end development for ****control of performance-critical code
• Experience with multithreaded programming and performance profiling tools, debugging, and performance optimization
• Excellent problem-solving skills and ability to work in a collaborative environment

Nice to have

• Backend development (FFmpeg framework, GStreamer)
• Knowledge of container formats (MP4, MKV, MPEG-TS)
• Experience with ML–based video enhancement or compression

US Salary Range

$120,000 - $220,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.

We’re an equal opportunity employer. We welcome all applicants without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Who we are

Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.

As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.

What you will be doing

As a Principal Electrical Engineer at Neros, you are the chief technical authority and visionary for our electrical systems. Your primary focus will be on high-level architecture, advanced simulation, and strategic oversight. You will work closely with upper management to define the long-term technical roadmap and collaborate with senior engineers to solve our most complex cross-disciplinary challenges. This role requires a unique blend of deep academic knowledge and practical applied expertise to ensure our designs are innovative, robust, and aligned with company goals.

Responsibilities

• Define the overall electrical architecture for new systems, translating stakeholder needs into actionable hardware requirements
• Lead the technical direction of the company through high-level analysis, simulation, and block diagramming
• Serve as the final technical sign-off authority on all major design decisions, V&V plans, and product releases
• Mentor and guide Electrical Engineers, fostering technical excellence and professional growth within the team
• Work with stakeholders and management to sign off on system requirements and ensure technical feasibility
• Provide expert-level technical solutions to complex, multi-disciplinary problems across the organization
• Clearly communicate architectural vision and technical strategy through comprehensive documentation and presentations

You should have the following

• Master of Science or PhD in Electrical Engineering or a related field
• 10+ years of distinguished experience in electrical hardware design and architecture
• Recognized expert in a relevant technical domain (e.g., power electronics, RF design, system architecture, high-speed digital design)
• Proven experience in defining system architecture from the ground up and translating high-level requirements into detailed technical specifications
• Experience with Design for Manufacturing (DFM), Design for Test (DFT), and EMC/EMI
• Exceptional leadership and mentoring abilities, with experience guiding senior-level engineers
• Strategic thinker with outstanding communication skills, capable of influencing both technical teams and executive leadership

Nice to have

• Deep expertise using Ansys or other multi-physics simulation tools to model complex system interactions and drive fundamental architectural decisions
• A background in IC design, verification, or architecture, with experience in the ASIC or FPGA development lifecycle
• System-level expertise in RF and wireless technologies, including architecting products using LoRa or similar technologies, considering antenna design, and overall system signal integrity of RF systems
• Mastery of high-speed digital design principles, with a history of architecting systems involving high-speed interfaces for digital video or data
• Experience developing technology roadmaps and making trade-off decisions between different silicon vendors and platforms
• Knowledge of system modeling languages or environments like MATLAB/Simulink

US Salary Range

$180,000 - $250,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.

We’re an equal opportunity employer. We welcome all applicants without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Role Overview 

Astera Labs is seeking a Director, Global Talent Acquisition to lead and scale our worldwide recruiting function during a pivotal period of hypergrowth. This is a high-impact leadership role responsible for building and executing the talent acquisition strategy that will fuel our expansion across North America, APAC, EMEA, and India. 

As a key member of the People team, you will own the end-to-end recruiting lifecycle, from executing on the workforce plan and employer branding to team development and operational excellence. You'll partner closely with executive leadership to ensure we attract and hire the world-class engineering and business talent needed to maintain our position as the leader in AI infrastructure connectivity. This role requires a hands-on leader who thrives in fast-paced environments, has deep semiconductor industry expertise, and has a proven track record of building high-performing global recruiting teams from the ground up. 

Key Responsibilities 

Global Talent Acquisition Strategy & Execution 

• Develop and execute a comprehensive global talent acquisition strategy aligned with Astera Labs' aggressive growth objectives and workforce plans 
• Partner with executive leadership and hiring managers to forecast hiring needs, prioritize roles, and deliver against ambitious recruiting targets 
• Build scalable recruiting processes, systems, and metrics to support a rapidly growing organization 

Team Leadership & Development 

• Lead, mentor, and scale a global team of recruiters and recruiting coordinators across North America, APAC, EMEA, and India 
• Establish clear performance expectations, provide ongoing coaching, and foster a culture of excellence, accountability, and continuous improvement 
• Identify and develop future recruiting leaders within the organization 

Semiconductor & Technical Recruiting Excellence 

• Leverage deep semiconductor industry knowledge and networks to source and attract top-tier engineering talent in a highly competitive market 
• Drive innovative sourcing strategies to build robust pipelines for critical technical roles across hardware, firmware, and software disciplines 
• Serve as a trusted advisor to hiring managers on market trends, compensation benchmarking, and competitive intelligence 

Operational Excellence & Employer Branding 

• Implement and optimize recruiting tools, processes, and analytics to drive efficiency and improve candidate experience 
• Partner with Marketing and People teams to strengthen Astera Labs' employer brand and position the company as a destination for top talent 
• Ensure compliance with global hiring regulations and maintain consistency in recruiting practices across all regions 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, or related field 
• 10+ years of progressive talent acquisition experience, including 5+ years in a leadership role managing global recruiting teams 
• Proven experience in the semiconductor or adjacent hardware technology industry 
• Demonstrated success scaling recruiting functions and building teams from scratch in high-growth environments 
• Experience leading distributed teams across multiple geographies (North America, APAC, EMEA, India) 
• Strong understanding of technical roles and the ability to effectively partner with engineering leaders 

Preferred Qualifications 

• Experience at a pre-IPO or recently public technology company during periods of rapid scale 
• Track record of recruiting for highly specialized semiconductor roles (analog/mixed-signal, ASIC, firmware, etc.) 
• Experience implementing or optimizing applicant tracking systems and recruiting analytics platforms 
• Strong executive presence with the ability to influence and build relationships at all levels of the organization 
• Data-driven mindset with experience using metrics to drive recruiting performance and strategic decisions 

Salary range is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

Role Overview

Astera Labs is looking for a Senior Principal Engineering Program Manager to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale.

Key Responsibilities

• Program Ownership & Execution

  • Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM
  • Serve as the single point of ownership for assigned ASIC programs
  • Drive program planning, schedules, budgets, resources, and risk management

• Cross-Functional Leadership & Issue Resolution

  • Lead cross-functional teams across design, validation, product, test, firmware, software, and operations
  • Resolve complex pre-silicon and post-silicon issues through strong technical judgment

• Stakeholder Management & Alignment

  • Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders
  • Champion program execution while aligning engineering delivery with business and customer goals

Basic Qualifications

• BS or MS in Electrical, Electronics, or Computer Engineering
• 10+ years of ASIC product development experience in a semiconductor environment
• Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical Design
• Experience delivering ASICs in advanced nodes (<10nm)
• Proven ability to lead in a matrixed, high-pressure environment
• Strong program management skills; familiarity with MS Project, Jira, Atlassian tools, Scrum/WBS

Preferred Qualifications

• 5 or more years of experience as an ASIC Program Manager
• Experience with PCIe, memory, or high-speed data communication ASICs

Salary range is $205,000 to $250,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.

PsiQuantum’s mission is to build the first useful quantum computers—machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. 

Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportation, materials, and other foundational industries. 

Our architecture and approach is based on silicon photonics. By leveraging the advanced semiconductor manufacturing industry—including partners like GlobalFoundries—we use the same high-volume processes that already produce billions of chips for telecom and consumer electronics. Photonics offers natural advantages for scale: photons don’t feel heat, are immune to electromagnetic interference, and integrate with existing cryogenic cooling and standard fiber-optic infrastructure. 

In 2024, PsiQuantum announced government-funded projects to support the build-out of our first utility-scale quantum computers in Brisbane, Australia, and Chicago, Illinois. These initiatives reflect a growing recognition that quantum computing will be strategically and economically defining—and that now is the time to scale. 

PsiQuantum also develops the algorithms and software needed to make these systems commercially valuable. Our application, software, and industry teams work directly with leading Fortune 500 companies—including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical—to prepare quantum solutions for real-world impact. 

Quantum computing is not an extension of classical computing. It represents a fundamental shift—and a path to mastering challenges that cannot be solved any other way. The potential is enormous, and we have a clear path to make it real. 

Come join us. 

Job Summary:

Quantum computing promises to solve many important problems that could never be solved on any conventional computer. At PsiQuantum we’re building a general-purpose silicon photonic quantum computer to tackle these very problems.

PsiQuantum is looking for an experienced data platform engineer who can design, implement and maintain scalable data pipelines that extract, move and transform data across the Photonic Circuits organization. This role optimizes ETL workflows and integrates various data sources (APIs, DBs, streaming systems) and ensures data quality and observability. This role will work closely with the platforms team and the circuit designers, system engineers and validation engineers. The output will enable ease of producing analytics, scaling tape-out and providing well-structured data sets for reporting. Quantum computing requires breakthrough engineering innovations; we expect software solutions that are novel and custom while at the same time, leverage automation and other best practices from the semiconductor industry. Being a startup in an all-new engineering field, the role is expected to be highly collaborative and requires excellent technical skills to execute projects to meet milestones and technical scope.

An ideal Data Platform SW Engineer candidate combines strong SW engineering skills with deep appreciation for semiconductor and chip design EDA toolchains. They are experienced in building scalable data pipelines that ingest and transform data from simulation outputs, layout tools, verification systems, test benches, lab measurements, and manufacturing yield reports. Proficient in Python and SQL, they are comfortable working with large structured and unstructured datasets (netlists, GDS metadata, waveform data, logs) and integrating disparate systems across design, verification, and fabrication environments. They understand the importance of data integrity, traceability, and reproducibility in silicon development, and design pipelines with robust validation, versioning, and auditability. The ideal candidate collaborates effectively with circuit designers, CAD/EDA engineers, verification teams, and manufacturing operations, translating complex engineering workflows into reliable, automated data infrastructure that accelerates design iteration, improves yield analysis, and enables data-driven decision-making across the chip lifecycle.

Responsibilities:

• Key member of the software solutions team responsible for developing and deploying software for test systems, product platforms and manufacturing data management.
• Design, build, and maintain scalable data pipelines that ingest data from EDA tools, simulation frameworks, verification systems, lab equipment, and manufacturing test platforms.
• Develop robust ETL/ELT workflows to transform netlists, layout metadata, waveform data, logs, and yield data into structured, analysis-ready datasets.
• Integrate disparate engineering systems across design, verification, tapeout, and silicon validation environments.
• Ensure data integrity, traceability, and version control across the chip development lifecycle.
• Implement automated validation, monitoring, and observability for pipeline reliability and data quality.
• Optimize performance for large-scale simulation outputs and high-volume manufacturing datasets.
• Collaborate with photonic circuit designers, CAD/EDA/PDK engineers, verification teams, and silicon validation engineers to translate workflow requirements into scalable data solutions.
• Build data models and infrastructure that support yield analysis, failure analysis, PPA (power, performance, area) tracking, and design iteration metrics.
• Maintain secure and compliant data handling practices across on-prem and cloud environments.
• Contribute to internal tooling and automation frameworks to reduce manual data handling and accelerate design cycles.

Experience/Qualifications:

• Bachelors or other advanced degrees in Computer Science or related engineering fields.
• 3+ years of experience building and maintaining production-grade data pipelines or data platforms.
• Use programming languages (Python, SQL) and tools (DataBricks, Apache Kafka, Spark, Airflow) to ensure high-quality, scalable data flow.
• Understanding of software engineering best practices (version control, CI/CD, testing, code reviews).
• Experience working in semiconductor, ASIC/SoC, or photonics design environments.
• Knowledge of HPC environments or high-throughput compute clusters.
• Preference for experience in supporting ML or advanced analytic engineering workflows.
• Experience with complex software development projects for custom test solutions, hardware interfaces, and platform level firmware/software OR experience developing complex experimental systems in the case of recent college graduates.
• Proven team player with an ability to work effectively across departments, sites, time zones.
• Excellent verbal and written communication skills with an ability to communicate effectively to a variety of audiences.
• Strong critical thinking, creative, innovative, analytical, and detail-oriented problem-solving skills.
• Proven track record of impactful results.
• Ability to work independently with limited direction.
• Demonstrated ability to lead and juggle multiple priorities and deliver against a schedule.
• Demonstrated interest in quantum computing.
• Ability to contribute to a fast-paced start-up environment.

PsiQuantum provides equal employment opportunity for all applicants and employees. PsiQuantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.

Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to recruiting@psiquantum.com.

We are not accepting unsolicited resumes from employment agencies.

Snapshot

At Google DeepMind, we value a unique culture where long-term ambitious research flourishes. We are seeking a highly motivated ML Silicon Tech Lead Manager to join our HW-SW co-design team. This is a hands-on role for a deeply technical expert who will also lead a high-impact team to drive advances in machine learning acceleration.

About You

GenAI at Google DeepMind prioritizes deeply technical leadership. We are looking for an individual who:

• Contributes as a Senior IC: You are expected to be a direct technical contributor, particularly during onboarding and within key workstreams.
• Acts as a Technical Anchor: You excel at aligning senior engineers who may have diverging technical directions. You are the person who reduces the feeling of "too many moving parts" by providing a cohesive architectural north star.
• Thrives in Ambiguity: You are flexible enough to change course when ideas don't work out and willing to "plug in" wherever the project needs the most senior technical support.

The Role

As a TLM, you will spend a significant portion of your time on technical execution while managing a multi-disciplinary team to evolve our ML accelerator designs  in close collaboration with a paired ML software team.

Key Responsibilities:

• Direct Technical Contribution (IC): Directly contribute to the codebase and technical strategy. IC focus can be one specific silicon engineering discipline, or spanning the program needs more broadly.
• Technical Team Leadership: Lead a small team of ML silicon engineers across logic design, physical design, interconnect, and power.
• Architectural Alignment: Drive team cohesion by synthesizing fragmented technical opinions into a single, high-quality execution plan.
• HW-SW Strategy: Partner closely with the ML software team to define requirements for next-generation ML accelerators.
• Execution Management: Oversee technical execution across a virtual team including Google-internal and external partners.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10+ years of experience in silicon architecture, design, validation, or product development.
• Proven track record of technical leadership and successfully delivering complex silicon projects (tape-outs) to production.
• Deep expertise in at least one core silicon discipline (e.g., RTL, PD, DV) and strong familiarity with the entire ASIC flow.
• Experience with managing cross-functional silicon projects, including schedule, scope, and execution, and also managing silicon vendors and other external partners.

Preferred Qualifications:

• Master's or Ph.D. in a related field.
• Experience leading and managing teams across the full silicon development cycle, from RTL to bringup.
• Experience with high-performance compute IPs (e.g., GPUs, ML accelerators).
• Knowledge of high-performance and low-power architectures for ML acceleration.
• Excellent communication, and leadership skills.

At Google DeepMind, we value diversity of experience, knowledge, backgrounds and perspectives and harness these qualities to create extraordinary impact. We are committed to equal employment opportunity regardless of sex, race, religion or belief, ethnic or national origin, disability, age, citizenship, marital, domestic or civil partnership status, sexual orientation, gender identity, pregnancy, or related condition (including breastfeeding) or any other basis as protected by applicable law. If you have a disability or additional need that requires accommodation, please do not hesitate to let us know.

Snapshot

At Google DeepMind, we value a unique culture where long-term ambitious research flourishes. We are seeking a highly motivated ML Software Tech Lead Manager to join our HW-SW Co-design team. This is a hands-on IC role for a deeply technical expert who will also lead a small, high-impact team to drive advances in machine learning acceleration.

About You

GenAI at Google DeepMind prioritizes deeply technical leadership. We are looking for an individual who:

• Contributes as a Senior IC: You are expected to be a direct technical contributor, particularly during onboarding and within key workstreams.
• Acts as a Technical Anchor: You excel at aligning senior engineers who may have diverging technical directions. You are the person who reduces the feeling of "too many moving parts" by providing a cohesive architectural north star.
• Thrives in Ambiguity: You are flexible enough to change course when ideas don't work out and willing to "plug in" wherever the project needs the most senior technical support.

The Role

As a TLM, you will spend a significant portion of your time on technical execution while managing a multi-disciplinary team to evolve our software stack.

Key Responsibilities:

• Direct Technical Contribution (IC): Directly contribute to the codebase and technical strategy. Focus ideall includes acting as a Mountain View-based bridge between our co-design time and the Gemini core team.
• Technical Team Leadership: Lead a small team of ML software engineers across numerics, performance optimization, novel training techniques, and novel model exploration.
• Architectural Alignment: Drive team cohesion by synthesizing fragmented technical opinions into a single, high-quality execution plan.
• HW-SW Strategy: Partner closely with the hardware team to define requirements for next-generation ML accelerators.
• Execution Management: Oversee technical execution across a virtual team including Google-internal and external partners.

Minimum Qualifications:

• Bachelor’s degree in Computer Science, or equivalent practical experience.
• 10+ years of experience in high-performance software, including AI/ML.
• Proven track record of direct technical contribution and leadership in delivering complex silicon or software projects to production.

Preferred Qualifications:

• Master’s or Ph.D. in a related field.
• Hands-on experience with high-performance compute IPs (GPUs, ML accelerators).
• Experience contributing to silicon development.
• Expertise in at least one core silicon engineering discipline (e.g., RTL, PD, DV) and familiarity with the full ASIC flow.

Position Overview:

The Transaction Review Specialist (TRS) will be a member of the Transaction Services team. The TR Specialist will be primarily responsible for ensuring every approved consumer transaction is correctly documented in the ecoATM database and meets the required criteria for an approved transaction. The position requires the ability to remain focused while quickly and thoroughly reviewing ecoATM transactions. Accordingly, attention to detail is a must. 

Please note: This position is full time with a 40 hour work week. The role will require a flexible shift schedule with the ability to work nights/weekends. 

Hourly Pay Rate: $18.00 - $20.00/hr

Key Responsibilities: 

• Data entry and editing  
• Review daily customer transaction data to ensure accuracy of information, including but not limited to, state identification fields populated, authorized identification used by customer, IDV agent decision-making regarding customer approval  
• Generate reports for various law enforcement jurisdictions using local database, pdf process, or online forms 
• Review online documentation for potential fraudulent, utilizing provided tools to determine verification of information 
• Running weekly reports for law enforcement dissemination 
• Online article tracking for identified state jurisdictions 
• Review reports and flag suspicious activity; provide verification and communication of identified activity 
• Provide data review and product knowledge support to other departments to ensure optimal kiosk and online customer experience 

Additional Duties: 

• Approve or deny transactions with consumers based off of the requirements for conducting business with ecoATM (ID Verification) 
• Perform timely and accurate verifications, as requested 
• Review real-time devices and accurately detect device condition (PGV) 

Education & Experience 

• High School Diploma/GED or 1+ year experience in retail or fast-paced environment, to include 6+ months of data entry/verification experience required 
• Experience in a call center-type environment a plus 

Knowledge, Skills & Abilities 

• Strong attention to detail and efficiency 
• Ability to handle multiple tasks, ensuring timely completion 
• Must be self-motivated, resourceful  
• Proven ability to work autonomously 
• Proficient in data entry  
• Able to navigate through databases  
• Basic knowledge of MS Office (Word, Excel, Access, Outlook) 
• Effective oral and written communication skills  
• Proven ability to work both independently and as part of a team  
• Timely attendance 
• Able to work a flexible schedule, including evenings and weekends 

This job description is not intended to be all-inclusive. Employee may perform other related duties as assigned to meet the ongoing needs of the organization. 

About the Role

We are looking for a highly experienced Photonics Chip Lead to take ownership of the design and delivery of advanced Photonic Integrated Circuits (PICs) for next-generation optical networking solutions. This role requires deep technical expertise in Silicon Photonics systems, block and device design, as well as proficiency with IC design tools and PIC/ASIC co-design methodologies. You will lead the full lifecycle of photonic chip development—from architecture through physical design and integration—collaborating with multidisciplinary engineering teams.

Key Responsibilities

• Lead the design and delivery of Photonic Integrated Circuits (PICs) for core product lines.

• Drive all key phases of PIC development, including architecture, photonic routing, schematic capture, modeling, and physical layout.

• Collaborate closely with analog, digital, and packaging teams to ensure all product and integration requirements are met.

• Contribute to the design and optimization of Silicon Photonics devices and subsystems, enhancing the internal photonics design kit (PDK) and design libraries.

Qualifications

Specialized Skills

• Proven experience in end-to-end Silicon Photonics PIC design, including architecture, link budget analysis, and system integration.

• Expertise in photonic circuit modeling and simulation using industry-standard tools such as Lumerical, Photon Design, RSoft, or VPI.

• Strong background with physical design and layout tools (e.g., Cadence, Mentor Graphics, or equivalent).

• Experience in co-designing PICs with ASICs and digital control systems.

• Familiarity with data analysis platforms like JMP or DataConductor.

Education

• Master’s degree in Electrical Engineering, Physics, or a related field (Ph.D. preferred).

Experience

• 10+ years of hands-on experience in Silicon Photonics design and product development.

Attributes

• Highly self-driven with a proactive and solution-oriented mindset.

• Excels in collaborative, fast-paced environments.

• Excellent verbal and written communication skills.

• Demonstrates strong attention to detail and creative problem-solving ability.