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What You Can Expect
We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role focuses on end-to-end scan execution, from insertion and verification through DRC closure, coverage improvement, and final DFT signoff. The ideal candidate will own scan quality, coverage closure, and DFT signoff for complex SoC designs.
ESSENTIAL DUTIES AND RESPONSIBILITIES
Lead hands-on scan DFT implementation, including:Scan insertion and stitching
Scan Streaming Network (SSN) implementation
IJTAG (IEEE 1687) insertion and connectivity
Perform scan DFT verification, debug, and DFT DRC closure
Debug and resolve scan-related DRCs, connectivity issues, and control signal problems
Run, analyze, and debug SpyGlass DFT/RTL checks, partnering with design teams to resolve violations
Generate, simulate, and debug ATPG scan patterns
Analyze ATPG results and drive scan coverage improvement and closure
Develop and validate DFT-related timing constraints (scan, shift, capture, and test modes)
Create and maintain TCL scripts for scan insertion, ATPG setup, and coverage analysis
Optimize scan implementations for pattern efficiency and test quality
Support hierarchical scan integration at both block and SoC levels
Collaborate closely with RTL and Physical Design teams to resolve scan-related issues
Support pre-silicon DFT signoff and post-silicon pattern bring-up and debug
Assist with ATE pattern conversion and scan debug activities
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or
related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or
related fields with 3-5 years of experience.
8+ years of hands-on experience in DFT scan implementation
Strong expertise with Siemens Tessent, including:Scan insertion and verification
ATPG pattern generation and coverage analysis
IJTAG (IEEE 1687) and SSN implementation
Strong understanding of:Scan Streaming Network (SSN)
IEEE 1149.x, IEEE 1500, and IEEE 1687 standards
Proven ability to resolve scan DFT DRCs and drive coverage closure
Strong TCL scripting skills for automation and flow customization
Experience developing and validating scan and test-mode timing constraints
Full DFT lifecycle experience, from RTL/netlist through silicon debug
Strong debugging, ownership, and problem-solving skills
Excellent verbal and written communication skills
PREFERRED QUALIFICATIONS
Experience with scan compression and advanced scan architectures
Post-silicon experience, including:Pattern bring-up and debug
Silicon characterization and yield learning
Experience mentoring junior engineers or owning DFT scan signoff
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Apply to PhizenixPHIZENIX INC
Business Development Manager — IT Staffing
Bay Area, CA | Full-time | $80,000 – $120,000 base + commission | IT Staffing / MSP
ABOUT PHIZENIX INC
Phizenix Inc is a Tech Talent Solutions, IT Services and IT Consulting organization based out of Livermore, CA. We partner with leading enterprises and high-growth tech organizations to deliver top IT talent through direct, contract, and MSP-managed staffing solutions. As we scale our Bay Area presence, we are looking for a driven Business Development Manager to expand our client base and revenue.
ABOUT THE ROLE
You will own new business development for Phizenix Inc — opening doors, building relationships, and closing deals with clients preferably from Bay Area, CA. This is a hunter role focused on acquiring net-new logos and growing accounts to $2M–$5M+ in revenue, with deep engagement in MSP/VMS-managed programs.
WHAT YOU'LL DO
WHAT YOU'LL BRING
NICE TO HAVE
COMPENSATION & PERKS
Commission: Uncapped, on new and expanded accounts
Benefits: Full medical, dental, vision, flexible PTO, and remote flexibility after ramp
WHY PHIZENIX INC
At Phizenix Inc, you'll have the backing of an established staffing brand with the agility of a growth-stage firm. You'll have direct access to leadership, a competitive commission structure, and a clear path to senior sales or management roles as we expand our Silicon Valley footprint.
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Location Bengaluru |
Reports To Head of Supply Chain |
Level Supply Chain Manager |
Type Full-Time (Hybrid/Onsite) |
We are hiring a Supply Chain Manager to own the Asia-side supply chain operations for our AI hardware products. Based in India, you will be the operational owner of PCBA build execution with our CM partners, component-level supply planning, procurement management, and Asia logistics. This role is critical to ensuring our production pipeline runs smoothly from component procurement through board assembly to finished goods fulfillment. You will work extensively in NetSuite ERP for procurement, MRP, inventory management, and invoice reconciliation. You will also own the tactical procurement work including PO/invoice reconciliation and drive monthly variance analysis (PCBA costs, material variances, and PPVs) in partnership with finance.
PCBA Build Planning & Execution
Procurement Management & Variance Analysis
Asia Logistics & 3PL Fulfillment
Component Supply Planning & Inventory Management
AI-Augmented Operations & Systems
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Apply to PhizenixClient is seeking a highly motivated and experienced Senior Account Executive with a proven track record of opening new accounts and selling professional consulting services in enterprise IT domains. This is an individual contributor role focused exclusively on hunting new business opportunities and closing complex deals.
Key Responsibilities:
Skills and Qualifications:
Nice to have
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Get ready to dive into an exhilarating journey as you work on the bring-up, validation, and debugging of a groundbreaking interference accelerator chip/chiplets! Here’s what you can look forward to:
What you will bring:
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Job Overview
As a Shopify Developer, you will be responsible for designing, building, and maintaining our Shopify storefront — ensuring it delivers a luxury, performant, and conversion-optimized experience. You'll collaborate cross-functionally with design, marketing, and product teams to bring our brand story to life digitally.
Key Responsibilities
Required Skills & Experience
Nice to Have
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Role Overview
We are seeking a Senior Staff DFT Engineer to join a rapidly growing DFT design team focused on next-generation AI accelerator SoCs. In this role, you will define, architect, and implement current and future DFT/DFX solutions, supporting advanced SoC designs that leverage innovative memory-centric compute and heterogeneous chiplet architectures.
This is a highly hands-on role requiring both deep technical execution and high-level planning, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.
Location:
Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.
Drive DFT partitioning strategies for ATPG, including hierarchical and scalable approaches.
Implement ATPG compression and serialization, and perform RTL scan insertion with associated design rule fixes.
Own Memory BIST (MBIST) solutions, including memory repair and in-system test (IST), from implementation through verification and silicon debug.
Support boundary scan and define DFT mode constraints for IPs, providing timing feedback to STA teams.
Generate and integrate DFT RTL, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).
Apply and support IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.
Execute and verify ATPG (SAF, TDF) and MBIST using unit-delay and min/max timing simulations.
Perform detailed ATPG coverage analysis and drive coverage closure.
Collaborate with product and test engineering teams to deliver manufacturing test patterns for ATE.
Develop diagnostic tools and flows for ATPG, MBIST, and silicon bring-up on ATE.
Work hands-on with industry-standard DFT tools, contributing from low-level implementation through architectural planning.
BE/ME (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7+ years of experience in DFT, including scan test and MBIST.
Proficiency with HDLs such as Verilog, SystemVerilog, or VHDL.
Experience with scripting or programming languages (e.g., Python, Perl, TCL, C).
Strong ability to collaborate effectively in cross-functional and diverse teams.
Experience producing clear, detailed technical documentation.
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What you will do:
The role requires you to be part of the team that helps productize the SW stack for our AI compute engine. As part of the software team, you will be responsible for the development, enhancement, and maintenance of software kernels for next-generation AI hardware. You possess experience building software kernels for HW architectures. You possess a very strong understanding of various hardware architectures and how to map algorithms to the architecture. You understand how to map computational graphs generated by AI frameworks to the underlying architecture. You have had past experience working across all aspects of the full stack toolchain and understand the nuances of what it takes to optimize and trade off various aspects of hardware-software co-design. You are able to build and scale software deliverables in a tight development window. You will work with a team of compiler experts to build out the compiler infrastructure, working closely with other software (ML, systems) and hardware (mixed signal, DSP, CPU) experts in the company.
What you will bring:
Minimum:
MS or PhD in Computer Engineering, Math, Physics, or related degree with 10+ years of industry experience Strong grasp of computer architecture, data structures, system software, and machine learning fundamentals Proficient in C/C++ and Python development in Linux environment and using standard development tools Experience implementing algorithms in high-level languages such as C/C++ and Python Experience implementing algorithms for specialized hardware such as FPGAs, DSPs, GPUs, AI accelerators using libraries such as CuDA etc. Experience in implementing operators commonly used in ML workloads—GEMMs, Convolutions, BLAS, SIMD operators for operations like softmax, layer normalization, pooling, etc. Experience with development for embedded SIMD vector processors such as Tensilica. Self-motivated team player with a strong sense of ownership and leadership
Preferred:
Prior startup, small team, or incubation experience.
Experience with ML frameworks such as TensorFlow and/or PyTorch.
Experience working with ML compilers and algorithms, such as MLIR, LLVM, TVM, Glow, etc.
Experience with a deep learning framework (such as PyTorch or TensorFlow) and ML models for CV, NLP, or recommendation.
Work experience at a cloud provider or AI comp.
Ready to apply?
Apply to PhizenixLocation: Hybrid, working onsite at our Bengaluru, India offices 3-5 days per week.
What you will do:
The role requires you to be part of the team that helps productize the SW stack for our AI compute engine. As part of the software team, you will be responsible for the development,
enhancement, and maintenance of software kernels for next-generation AI hardware. You possess experience building software kernels for HW architectures. You possess a very strong
understanding of various hardware architectures and how to map algorithms to the architecture. You understand how to map computational graphs generated by AI frameworks to the
underlying architecture. You have had past experience working across all aspects of the full stack toolchain and understand the nuances of what it takes to optimize and trade off various
aspects of hardware-software co-design. You can build and scale software deliverables in a tight development window. You will work with a team of compiler experts to build out the
compiler infrastructure, working closely with other software (ML, systems) and hardware (mixed signal, DSP, CPU) experts in the company.
What you will bring:
Minimum:
MS in computer engineering, math, physics, or a related degree with 5+ years of industry experience or PhD in computer engineering, math, physics, or a related degree with 1+ years of industry experience
Strong grasp of computer architecture, data structures, system software, and machine learning fundamentals.
Proficient in C/C++ and Python development in Linux environments and using standard development tools.
Experience implementing algorithms in high-level languages such as C/C++ and Python.
Experience implementing algorithms for specialized hardware such as FPGAs, DSPs, GPUs, and AI accelerators using libraries such as CUDA, etc.
Experience in implementing operators commonly used in ML workloads—GEMMs, Convolutions, BLAS, SIMD operators for operations like softmax, layer normalization, pooling, etc.
Experience with development for embedded SIMD vector processors such as Tensilica.
Self-motivated team player with a strong sense of ownership and leadership.
Preferred:
Prior startup, small team, or incubation experience.
Experience with ML frameworks such as TensorFlow and/orPyTorch.
Experience working with ML compilers and algorithms, such as MLIR, LLVM, TVM, Glow, etc.
Experience with a deep learning framework (such as PyTorch or TensorFlow) and ML models for CV, NLP, or recommendation
Work experience at a cloud provider or AI compute/subsystem company.
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Location:
Hybrid, working onsite at our Bangalore offices 3 days per week.
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Apply to PhizenixLocation:
Hybrid, working onsite at our Bangalore offices 3 days per week.
Minimum:
BS in Electrical Engineering, Computer Science, or a related field with 8+ years of industry experience, or an MS in Electrical Engineering, Computer Science, or a related field with 7 years of industry experience is preferred.
Experience in IP/SoC verification cycle preferably from concept to tape-out to bring-up.
Good knowledge of verification methodologies such as UVM/OVM, etc.
Hands-on ASIC-SoC design verification tests and debug experience.
Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.
Good problem-solving skills and the passion to take on challenges (particularly in AI domain).
Passionate about AI and thriving in a fast-paced and dynamic startup culture.
Preferred:
Part of Successful implementation of multiple verification environments and tape-out efforts.
Experience with C/C++ is good
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Base + Commission. Targets and payout will match what we need this role to drive.
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This role is part of the Software Infrastructure team, responsible for building and scaling the core development infrastructure that supports the entire software engineering organization. You will work on designing, improving, and maintaining tools and platforms that enable development of ML accelerator systems across both hardware and software environments.
In this role, you’ll own and enhance infrastructure around GitLab, CI/CD pipelines, containerized workflows (Docker/Podman), and developer productivity tools. You’ll collaborate closely with software and hardware teams to ensure reliable, scalable, and efficient development and deployment pipelines.
The team is looking for someone with strong hands-on experience in C/C++, Python, Linux-based systems, REST APIs, containers, and modern DevOps practices, with the ability to debug and improve complex CI and build environments.
Bachelor’s degree in Computer Science, Engineering, Math, Physics, or a related field
7+ years of industry experience in software infrastructure, DevOps, or platform engineering
Strong proficiency in C/C++ and Python
Deep experience with GitLab workflows, including merge requests, merge trains, and CI/CD pipelines
Hands-on experience with Docker and Podman containers
Experience using Kubernetes (K8s) or similar orchestration tools for deploying ML or large-scale workloads
Familiarity with Bazel, code coverage tooling, data source integration, and DevOps metrics
Proven ability to debug CI failures, perform root cause analysis, manage linting, bisect issues, handle remote code coverage, and implement security and vulnerability testing
Experience working in startups or small, fast-moving teams
Background in AI compute, ML accelerators, or subsystem development
Prior experience in a DevOps-focused role
Exposure to MLOps, including ML model deployment pipelines and development workflows
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Apply to PhizenixClient is seeking machine learning researchers to join our Algo Team. We’re looking for someone to invent, design, and implement efficient algorithms that will be used to optimize Large Language Model inference on DNN Accelerators we develop. You would be part of a close-knit team of mathematicians, ML researchers, and ML engineers who create and apply advanced algorithmic and numerical techniques to the most cutting-edge and high-impact research in the overlap of mathematics, ML, and modern LLM applications.
Location:
Hybrid, working on-site at our Bangalore, India, offices 3 days per week
Qualifications:
Strong mathematical skills—MSc or PhD in math, CS, statistics, physics, or a related STEM field
Experience in Python and OOP code design
Experience with transformer architecture is advantageous but not mandatory
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You will be part of a team responsible for bringing a software stack to production for next-generation AI compute platforms. As a member of the Software QA team, you will design and build automated test frameworks for AI hardware and software components, and continuously enhance the test and qualification infrastructure to support evolving products.
This role involves leveraging CI/CD pipelines and Python-based test frameworks to drive both component-level and end-to-end validation. You will develop automation to support large language model accuracy, benchmarking, and robustness testing, ensuring software and hardware stacks meet high quality and performance standards.
You will collaborate closely with machine learning kernel teams, compiler and runtime engineers, hardware architects, and ML researchers across global teams throughout the qualification lifecycle. There will also be opportunities to contribute to emerging ML and AI technologies as part of the broader engineering effort.
Qualifications
Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field, with 7+ years of industry experience.
Solid understanding of machine learning fundamentals and large language models.
Strong proficiency in Python, including data structures, and experience working in a Linux environment.
Self-driven team player with strong collaboration skills.
Preferred Experience
Experience working in startups or small, fast-paced teams.
Hands-on exposure to machine learning models and neural network layers.
Experience testing deep learning frameworks such as TensorFlow, PyTorch, and transformer-based models.
Familiarity with CI/CD systems, particularly GitLab-based pipelines.
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Lead silicon bring-up, post-silicon validation, and deep debug of next-generation AI accelerator chiplets, including validation of high-speed interfaces such as PCIe Gen5, LPDDR5, and die-to-die interconnects.
Define and execute comprehensive validation and bring-up strategies, building automated, self-checking test frameworks with firmware- and kernel-level instrumentation and logging.
Develop embedded firmware and host-side test software to stress, validate, and characterize high-speed interfaces across multiple system configurations.
Work hands-on in the lab, partnering with the team to set up and utilize advanced debug and test equipment to support efficient validation and issue resolution.
Collaborate closely with hardware, software, validation, test, and operations teams, including support for ATE and complex HW/SW debug efforts.
Qualifications
BS/MS in Electrical or Computer Engineering with 15+ years of experience working on high-performance SoCs.
Proven experience in system and AI accelerator bring-up and post-silicon debug.
5+ years of embedded software, firmware, or RTOS development experience.
Strong familiarity with high-speed serial protocols (PCIe Gen3/4/5) and/or high-speed memory technologies (LPDDR3/4/5 or similar I/O standards).
Excellent debugging, communication, and cross-functional collaboration skills, with the ability to work effectively across diverse engineering teams.
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Apply to PhizenixWe are seeking an experienced Package Reliability Engineer with expertise in 2.5D/3D advanced packaging. The ideal candidate will have a strong background in physics of failure, materials science, and experience working closely with OSATs to drive package reliability improvements. This role requires collaboration with external assembly and test partners, internal design, process, and failure analysis teams, and suppliers to ensure the reliability and manufacturability of cutting-edge semiconductor packages.
ESSENTIAL DUTIES AND RESPONSIBILITIES
QUALIFICATIONS
PREFERRED QUALIFICATIONS
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Apply to PhizenixWe are seeking a modeling Engineer to develop high-level models of complex SoC hardware. The virtual platforms combine models of custom hardware accelerators for vision, 2D and 3D graphics, machine learning and more, within a multi-core, multi-level memory hierarchy SoC architecture, and serve as the primary simulation vehicle for system software and firmware. The ideal candidate will be proficient in hardware simulation using C++, and understand the firmware development processes.
Responsibilities
- Design and develop SystemC TLM models to accurately represent the SoC architecture integrating emulated processors, DSPs, Network-on-Chip, DMA and memory controllers, etc…
- Integrate first-party and vendor models into the Virtual Platform, develop automated workflows to ensure register-level accuracy and complete connectivity at the SoC level, minimizing manual intervention and enabling continuous integration.
- Collaborate with silicon architects, digital designers and verification engineers to design and develop high-fidelity, fast C++ models for first-party IP.
- Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering, enabling end-to-end silicon validation test frameworks.
- Enhance the virtual platforms to enable SoC and system architecture exploration by instrumenting models for power and performance metrics, allowing for data-driven design decisions and trade-off analysis to optimize system performance and power consumption.
Minimum qualifications
- B.S. degree in Computer Science or Electrical Engineering or equivalent experience.
- 2+ years experience in hardware model simulation, virtual platform, performance modeling of complex SoCs or high-fidelity hardware accelerators.
- High proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation.
- General familiarity with SoC components: embedded processors such as ARM A/M series, Risc-V, DSP, DMA, Cache Hierarchy, DRAM, Network-on-chip, AMBA protocols. Extensive experience in at least one of these areas.
- Experience with modern buildframeworks and continuous integration systems, such as CMake, Bazel and CI frameworks such as Jenkins, GitLab CI/CD.
- Experience with debugging and profiling tools, such as GDB or other debuggers
Preferred qualifications
- Experience with the SystemC/TLM library
- Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models
- Familiarity with processor/DSP architectures, such as ARM, RISC-V, and XTensa
- Familiarity with NoC, MMU, address translations, and cache modeling
- Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc…
- Proficiency in Python to automate design flows, creation of collateral data
- Experience with high level C/C++ synthesis (HLS)
- Working knowledge of Verilog
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We are seeking a highly skilled Silicon Photonic IC Design Engineer to play a key role in the design and physical layout of advanced Silicon Photonic Integrated Circuits (PICs) that interface directly with custom ASICs built on leading-edge semiconductor process nodes. This position offers the opportunity to work at the intersection of photonics, analog, and digital design — helping to define and deliver next-generation optical and electronic systems.
Contribute to the design and physical layout of complex Silicon Photonic ICs (PICs) that connect directly with advanced ASICs.
Participate in all stages of PIC delivery — from floor planning and block placement to micro-architecture, optical/electrical routing, and back-end verification (DRC/LVS).
Collaborate with analog, digital, and packaging teams to ensure optimal design outcomes that meet requirements for opto-electronic performance, signal integrity (SI), and power integrity (PI).
Work closely with other photonics engineers to refine layout methodologies, improve design automation, and enhance existing software-based verification and layout flows.
Specialized Skills
Strong understanding of photonics fundamentals and core engineering design principles.
Hands-on experience with Silicon Photonics Process Design Kits (PDKs) and best practices for designing and laying out photonic components, subsystems, and complete PICs.
Proficiency with physical design tools such as Cadence, Siemens Mentor, or Klayout, including scripting and automation using SKILL or Python.
Familiarity with layout verification tools (e.g., Calibre, Pegasus) for DRC, ERC, and LVS checks.
Experience with SI and PI-aware electrical routing for mixed-signal and digital designs is a strong advantage.
Education
Ph.D. in Electrical Engineering, Physics, or a related field with a focus on integrated photonics or optical device design.
Preferred Attributes
Highly self-motivated with a proactive approach to problem-solving.
Creative thinker with strong attention to detail.
Thrives in a collaborative and fast-paced environment.
Excellent written and verbal communication skills.
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Future Opportunities at Phizenix – Stay Connected With Us
US Location: Remote / Hybrid / Onsite (depending on the role)
Employment Type: Full-time / Contract
Departments: Talent Acquisition, Tech & Engineering, Product & Delivery, Marketing, Operations & Strategy, Leadership & More
At Phizenix, we’re always on the lookout for passionate, innovative individuals ready to make an impact. While we might not have the perfect role for you today, that doesn’t mean the right opportunity isn’t just around the corner.
If you're interested in joining a fast-growing, people-first organization, we’d love to hear from you.
We regularly hire across a wide variety of roles and specialties, including:
Tech & Engineering
AI / ML Specialists
Frontend, Backend & Full-Stack Engineers
DevOps & Infrastructure Experts
QA Engineers & Automation Specialists
Data Engineers & Analysts
Mobile Developers (iOS / Android)
Product & Delivery
Product Managers & Product Owners
Scrum Masters & Agile Coaches
Delivery Managers
Business Analysts
UX Researchers
Design & Experience
UI/UX & Product Designers
Design Systems Specialists
Interaction & Motion Designers
Creative Directors
Marketing & Brand
Growth Marketers
Content Strategists & Copywriters
Performance Marketing Experts
SEO / SEM Specialists
Social Media & Community Managers
Brand Designers
Strategy & Operations
Business Strategy Analysts
Program & Project Managers
Operations Managers
Process Improvement / Lean Experts
Chiefs of Staff / BizOps Roles
Ready to stay on our radar?
Upload your resume and we’ll be in touch when something aligns with your skills and aspirations.
Let’s start the conversation before opportunity knocks—we’ll be ready.
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12 Months Contract with Possible extensions
We are looking for experienced AI Corporate Trainers to educate business professionals and organizations on AI technologies, their practical applications, and how to integrate AI into existing workflows. In this role, you will develop and deliver corporate training programs on AI concepts, implementation strategies, and best practices. The ideal candidate has a strong background in AI technologies, excellent presentation skills, and the ability to teach AI in a way that is engaging and easy to understand for diverse audiences.
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ABOUT THE ROLE
As Senior Firmware Engineer, you will be a key player in the architecture and the full lifecycle development of an AI platform system, including requirements, design, code, and test. In this role, you will be part of a team developing next generation AI/ML solutions using Client's AI Photonic Fabric Architecture. You will be responsible for developing production-grade firmware for Client's photonic fabric product lineup and developing firmware APIs for resource management and optimization. You will collaborate closely with hardware and software teams to implement the communication management software for different Photonic Fabric use cases.
ESSENTIAL DUTIES AND RESPONSIBILITIES
QUALIFICATIONS
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We’re seeking multiple Solutions Engineers to join our team of innovators and thought leaders. In this role, you’ll combine hands-on technical expertise with architectural vision to design and implement cutting-edge customer experience solutions using AWS services, with a particular focus on Amazon Connect and generative AI technologies.
Key Responsibilities
Required Skills & Experience
Preferred Qualifications
What Sets You Apart
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We are looking for a highly experienced Photonics Chip Lead to take ownership of the design and delivery of advanced Photonic Integrated Circuits (PICs) for next-generation optical networking solutions. This role requires deep technical expertise in Silicon Photonics systems, block and device design, as well as proficiency with IC design tools and PIC/ASIC co-design methodologies. You will lead the full lifecycle of photonic chip development—from architecture through physical design and integration—collaborating with multidisciplinary engineering teams.
Lead the design and delivery of Photonic Integrated Circuits (PICs) for core product lines.
Drive all key phases of PIC development, including architecture, photonic routing, schematic capture, modeling, and physical layout.
Collaborate closely with analog, digital, and packaging teams to ensure all product and integration requirements are met.
Contribute to the design and optimization of Silicon Photonics devices and subsystems, enhancing the internal photonics design kit (PDK) and design libraries.
Specialized Skills
Proven experience in end-to-end Silicon Photonics PIC design, including architecture, link budget analysis, and system integration.
Expertise in photonic circuit modeling and simulation using industry-standard tools such as Lumerical, Photon Design, RSoft, or VPI.
Strong background with physical design and layout tools (e.g., Cadence, Mentor Graphics, or equivalent).
Experience in co-designing PICs with ASICs and digital control systems.
Familiarity with data analysis platforms like JMP or DataConductor.
Education
Master’s degree in Electrical Engineering, Physics, or a related field (Ph.D. preferred).
Experience
10+ years of hands-on experience in Silicon Photonics design and product development.
Attributes
Highly self-driven with a proactive and solution-oriented mindset.
Excels in collaborative, fast-paced environments.
Excellent verbal and written communication skills.
Demonstrates strong attention to detail and creative problem-solving ability.
Ready to apply?
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