Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

ABOUT THE TEAM 

Anduril AIRS provides high-performance cooled infrared imaging solutions, encompassing IDCAs, modules, and cameras. We achieve this through state-of-the-art technologies, advanced designs, and vertically integrated manufacturing processes. Our core strength lies in delivering customized, mission-critical imaging capabilities to system integrators and instrumentation manufacturers facing unique, challenging, and complex thermal imaging needs.

ABOUT THE JOB

The AIRS team is seeking a Senior Firmware Engineer to design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.

WHAT YOU’LL DO

• Lead FPGA architecture, standards, development and review processes
• FPGA Development: Designing, architecting, simulating, and integrating VHDL designs into FPGAs or Systems on Chip (SoC) for optimized performance, resource utilization, and power efficiency.
• Hardware/Software Integration: Collaborating with multidisciplinary teams (electrical engineers, software engineers, systems engineers) to ensure seamless integration of the firmware with the overall system, including processor bring-up and board support packages.
• Testing and Validation: Developing robust test benches in VHDL/Verilog and utilizing lab tools such as oscilloscopes and logic analyzers for rigorous testing and validation of designs against functional specifications and performance requirements.
• Optimization: Optimizing the algorithms for hardware acceleration, including MIPS optimization and efficient use of on-chip bus protocols like AXI or AXI-Stream. 

REQUIRED QUALIFICATIONS

• Education: A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
• Experience: 10+ years of experience developing HDL firmware for FPGA devices 
• Hardware Description Languages: Expertise in VHDL and/or Verilog/SystemVerilog is essential for RTL (Register Transfer Level) design.
• FPGA Tools: Experience with industry-standard FPGA design tools such as Xilinx Vivado or Intel Quartus.
• Debugging Skills: Strong hardware/software debugging skills using standard lab equipment.
• Version Control: Proficiency with version control systems (e.g., Git) for collaborative development.
• Eligible to obtain and maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS 

• Demonstrated experience designing with multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, and common communication busses like SPI and I2C
• Embedded software development experience with the use of timers, interrupts, hardware peripherals such as SPI controllers and ADCs
• Knowledge of embedded Linux development, including device trees, hardware drivers, bootloaders, and basic Unix/Linux tools
• Familiar with common programming languages like Python and MATLAB
• Familiarity with infrared image sensor technology

About Epirus

Epirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques that allow power-hungry systems to do more with less.  

Job Summary: This is an exciting role in an innovative company. The ideal candidate for the position is someone who has experience developing high-performance real-time, autonomous software systems to rapidly develop next-generation products.  Employ your expertise by developing software systems that support functions such as autonomous target tracking, agile electronic beam-forming, and real-time hardware control.

Responsibilities: 

• Design and implement software of embedded devices and systems from requirements to production and deployment 
• Design, develop, code, test, and debug system software 
• Build real-time control software for a variety of projects 
• Analyze and enhance the efficiency, stability and scalability of system resources 
• Direct software QA and optimize I/O performance 
• Interface with hardware design and development 
• Assess third-party and open-source software 
• Lead teams to create minimum viable products from an idea 
• Derive software frameworks and architectures to accelerate development 
• Mentor peers to advance team velocity

Basic Qualifications:

• 5+ years of development in C and C++ 
• 3+ years working with embedded systems 
• Additional experience with one or more modern systems language(s): Python, Java, VHDL, Verilog, Go, Rust, etc. 
• Versed in multithreaded design (concurrency primitives, resource management, etc.) 
• Competent in computer science concepts (algorithms, data structures, object-oriented programming, etc.) 
• Strong foundations in mathematics and linear algebra 
• Adequate knowledge of reading schematics and data sheets for components 
• Bachelor’s degree in computer science or a similar discipline, Master’s degree preferred
• This is an on-site position; availability to work in our HQ in Torrance is required

Preferred Skills and Experience:

• 2+ years of experience with Xilinx FPGA and Embedded Cortex CPU architectures 
• Experience building software for real-time operating environments with specific latency requirements 
• Experience with Embedded Linux and/or software integration with FPGA firmware 
• Knowledge or experience with digital signal processing (DSP) or radio frequency (RF) technologies 
• User experience with DevOps Pipeline tools 
• Experience with Docker or Helm  
• Scrum Master Certification 
• Desire to mentor new hires 
• Exposure or interest in sensor fusion, machine learning, or AI

ITAR REQUIREMENTS: 

• To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

At Epirus, you’ll work with technical peers and great people—and get first crack at some of the defining technology challenges of our time. Here, “impossible” is just a challenge. We're a diverse, fast-growing team of change-makers fueling the future of energy with revolutionary solutions. Join us and rewrite the rules. 

ABOUT THE TEAM

Anduril's Space team is dedicated to expanding our AI-powered capabilities into the final frontier, enhancing Space Domain Awareness, Space Control, and Command and Control for U.S. military and allied partners. We're developing fully integrated hardware and software systems, including Lattice for Space Missions and modular payloads, to address growing threats in space and ensure our Guardians maintain a decisive advantage in this contested warfighting domain.

ABOUT THE JOB

We are looking for a Sr. FPGA/SoC Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be responsible for developing FPGA/SoC firmware and overseeing 3rd party development. You will work with internal and external design teams to develop products for use in orbit. This will require architecture, RTL generation and debug.

WHAT YOU’LL DO

• Rapidly develop, test, and implement FPGA designs using Xilinx SoC/FPGA.
• Integrate third-party vendors IP, as necessary.
• Work with third-party developers to ensure timely product success
• Perform digital circuit design, VHDL/Verilog coding, synthesis, place and route, timing closure, simulation, and verification. 
• Participate in entire design life cycle: from requirements and concept, through design and hand on testing/board bring up.
• Implement a variety of signal types such as high speed comms (ethernet, serial), signal processing (analog, digital).
• Ensure designs meet all relevant safety and performance standards, with traceability back to top-level system requirements, as necessary.
• Investigate and resolve bugs found during hand on testing (at HDL level and system level).

REQUIRED QUALIFICATIONS

• 5 years of experience preferred in FPGA/HDL hardware design. Experience with Xilinx SoC (Versal) is highly preferred.
• Familiarity with design software like Vivado (preferred), ModelSim, or Quartus.
• Proficient in VHDL and/or Verilog.
• Ability to work in a fast-paced, challenging environment.
• Excellent problem-solving and organizational skills.
• Strong communication and teamwork skills.
• Experience in SoC hardware bring-up, preferably on ARM-based systems.
• Eligible to obtain and maintain an active U.S. Secret security clearance. 

PREFERRED QUALIFICATIONS

• Working knowledge of designing for safety-critical functions.
• FPGA interfaces and high speed busses.
• Experience with systems on a Chip (SoC).
• Low-level firmware (C/C++) development for bring-up and test.
• Experience writing HDL for Space applications.

WHAT IS AIS?

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for a Staff FPGA Engineer to join our rapidly growing team in Reston, Virginia. You will be responsible for rapidly developing, testing, and implementing FPGA designs on Xilinx SoC/FPGA platforms. This requires strong skills in digital circuit design, VHDL/Verilog coding, and simulation. 

WHAT YOU’LL DO

• Integrate third-party vendors IP, as necessary.
• Participate in entire design life cycle: from requirements and concept, through design and hand on testing/board bring up.
• Implement a variety of signal types such as high speed comms (ethernet, serial), signal processing (analog, digital).
• Ensure designs meet all relevant safety and performance standards, with traceability back to top-level system requirements, as necessary.
• Investigate and resolve bugs found during hand on testing (at HDL level and system level).

REQUIRED QUALIFICATIONS

• Bachelors degree in electrical engineering, electronics engineering, computer engineering or related field
• 8+ years of professional experience in FPGA design and development. Experience with Xilinx SoC is highly preferred
• Familiarity with design software like Vivado (preferred), ModelSim, or Quartus
• Proficient in VHDL and/or Verilog
• Ability to work in a fast-paced, challenging environment
• Excellent problem-solving and organizational skills
• Strong communication and teamwork skills
• Experience in SoC hardware bring-up, preferably on ARM-based systems
• Currently possesses and is able to maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Working knowledge of designing for safety-critical functions.
• FPGA interfaces and high speed busses.
• Experience with systems on a Chip (SoC).
• Low-level firmware (C/C++) development for bring-up and test.

WHAT IS AIS?

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for a Staff FPGA Engineer to join our rapidly growing team in Reston, Virginia. You will be responsible for rapidly developing, testing, and implementing FPGA designs on Xilinx SoC/FPGA platforms. This requires strong skills in digital circuit design, VHDL/Verilog coding, and simulation. 

WHAT YOU’LL DO

• Integrate third-party vendors IP, as necessary.
• Participate in entire design life cycle: from requirements and concept, through design and hand on testing/board bring up.
• Implement a variety of signal types such as high speed comms (ethernet, serial), signal processing (analog, digital).
• Ensure designs meet all relevant safety and performance standards, with traceability back to top-level system requirements, as necessary.
• Investigate and resolve bugs found during hand on testing (at HDL level and system level).

REQUIRED QUALIFICATIONS

• Bachelors degree in Electrical Engineering, Electronics Engineering, Computer Engineering or related field
• 12+ years of professional experience in FPGA design and development. Experience with Xilinx SoC is highly preferred
• Familiarity with design software like Vivado (preferred), ModelSim, or Quartus
• Proficient in VHDL and/or Verilog
• Experience in SoC hardware bring-up, preferably on ARM-based systems
• Ability to work in a fast-paced, challenging environment
• Excellent problem-solving and organizational skills
• Strong communication and teamwork skills
• Currently possesses and is able to maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Working knowledge of designing for safety-critical functions
• FPGA interfaces and high speed busses
• Experience with systems on a Chip (SoC)
• Low-level firmware (C/C++) development for bring-up and test

PsiQuantum’s mission is to build the first useful quantum computers—machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. 

Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportation, materials, and other foundational industries. 

Our architecture and approach is based on silicon photonics. By leveraging the advanced semiconductor manufacturing industry—including partners like GlobalFoundries—we use the same high-volume processes that already produce billions of chips for telecom and consumer electronics. Photonics offers natural advantages for scale: photons don’t feel heat, are immune to electromagnetic interference, and integrate with existing cryogenic cooling and standard fiber-optic infrastructure. 

In 2024, PsiQuantum announced government-funded projects to support the build-out of our first utility-scale quantum computers in Brisbane, Australia, and Chicago, Illinois. These initiatives reflect a growing recognition that quantum computing will be strategically and economically defining—and that now is the time to scale. 

PsiQuantum also develops the algorithms and software needed to make these systems commercially valuable. Our application, software, and industry teams work directly with leading Fortune 500 companies—including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical—to prepare quantum solutions for real-world impact. 

Quantum computing is not an extension of classical computing. It represents a fundamental shift—and a path to mastering challenges that cannot be solved any other way. The potential is enormous, and we have a clear path to make it real. 

Come join us. 

Job Summary:

The mission of PsiQuantum's Principal Hardware Design Engineer role is to support the Electronics team by owning hardware designs integral to the underlying system of the quantum computer. This engineer will collaborate in cross-functional teams of thermal, mechanical, firmware, optical engineers. The designs will meet the requirements of the overall system architecture and physical framework of the quantum computer.

Responsibilities:

• Define, Design and deliver production ready high-speed embedded hardware systems.
• Design, create schematics, and oversee PCB layout of analog and digital circuitry consisting of but not limited to high-speed transceivers, 10+ Gbps electrical and optical data links, FPGA's, microcontrollers, clock distribution, and power distribution.
• Ensure signal integrity and EMI suppression is accounted for in all designs.
• Design and create test set-ups for testing of electro-optic modules.
• Characterize, optimize, and debug analog, digital, and electro-optic circuitry using equipment such as mixed signal & sampling oscilloscopes, vector network analyzers, signal generators, multimeters, DC power supplies.
• Develop software to drive measurements.
• Analyze data and extract key performance parameters.
• Maintain detailed documentation of hardware designs, test results, and design changes.
• Software tools:
  • Orcad Schematic Capture and Allegro PCB Layout
  • C++, Python, RTL (VHDL or Verilog)
  • Keysight PathWave ADS
  • Microsoft Office

Experience/Qualifications:

• 7 years of experience with a Master Degree.
• 9-12 years of experience with a B.S. Degree.
• Results oriented.
• Delivers on commitments.
• Attention to detail.
• Data-driven in decision-making.
• Strong problem-solving skills.
• Proven team player with an ability to work effectively across departments, sites, time zones in direct and matrix team environments.
• Excellent verbal and written communication skills with an ability to communicate effectively to a variety of audiences ranging from senior leadership and technical experts to entry-level staff.

PsiQuantum provides equal employment opportunity for all applicants and employees. PsiQuantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.

Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to recruiting@psiquantum.com.

We are not accepting unsolicited resumes from employment agencies.

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

We are looking for a Senior Engineer, RTL Memory Centric Computing.  This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop IP for memory centric computing systems using Verilog, System Verilog and HLS
• Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.
• Collaborate with Verification engineers to design and develop test plans
• Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in microarchitecture and computer architecture
• 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs
• Experience in designing Memory Controller, NOC, Interconnect IP
• Experience in Memory Centric computing IP and  SOC integration
• Experience in AI/ML workloads.
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SoC Architecture team is involved in  SoC‑level designs for emerging memory/storage solutions and validates each design’s feasibility with hands‑on RTL implementation. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

This role offers the opportunity to shape next-generation SoC and subsystem architectures while staying deeply hands-on in RTL design, integration, and validation. It is ideal for engineers who want to turn advanced memory and storage concepts into real hardware and drive them all the way to silicon

Job ID: 42896

Location: Daily onsite presence at our Folsom office in alignment with our Flexible Work policy

• Collaborate with architecture, design, verification, and system teams to define and implement SoC features and subsystems
• Translate architectural requirements into microarchitecture, RTL design, and verification plans
• Design and develop RTL for SoC blocks and integration logic using SystemVerilog/Verilog
• Drive block- and SoC-level integration activities, including clocking, reset, power intent, interfaces, and configuration infrastructure
• Analyze performance, power, area, and timing tradeoffs to deliver efficient and scalable designs
• Support design verification by debugging issues found in simulation, emulation, formal analysis, and silicon validation
• Participate in pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis and issue resolution
• Contribute to technical documentation, block specification, test plans, and design reviews

What You Bring

• Bachelors in Electrical, Computer Science or related with 15+ years of experience or Masters in Electrical, Computer Science or related Science with 13+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 10+ years of Industry experience preferred.
• Strong technical background in SSD architecture and storage technologies, including controller architecture, NAND/flash behavior, data path design, and system performance consideration. 
• Familiarity with DRAM architecture and memory subsystem design, including memory hierarchy, bandwidth/latency tradeoffs, buffering, and traffic behaviors. 
• Experience with data integrity and protection mechanisms, such as ECC, parity, CRC, RAID, and end-to-end data protection schemes. 
• Experience contributing to complex hardware products from architecture definition through RTL implementation, verification, and silicon bring-up. 
• Proven ability to collaborate effectively across architecture, design, verification, firmware, and validation teams. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

We are looking for a Senior Engineer, RTL Memory Centric Computing.  This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop IP for memory centric computing systems using Verilog, System Verilog and HLS
• Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.
• Collaborate with Verification engineers to design and develop test plans
• Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in microarchitecture and computer architecture
• 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs
• Experience in designing Memory Controller, NOC, Interconnect IP
• Experience in Memory Centric computing IP and  SOC integration
• Experience in AI/ML workloads.
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-VL1

What You’ll Do

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Support trace-driven power modeling, aligned with C/SystemC workload traces.
• Perform synthesis-assisted calibration using average and worst-case power anchors when available.
• Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
• Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
• Contribute to scalable IP-wise composition for full-system power simulation.

What You Bring

• Bachelors degree 20+ years of experience or Masters degree 18+ years of experience.
• Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
• Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
• Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
• Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
• Familiarity with SystemC or transaction-level modeling.
• Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
• Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Preferred Qualifications

• Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
• Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
• Exposure to low-power design and thermal management.
• Exposure to power macromodeling, power estimation flows, or architectural power analysis.

What You’ll Do

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Support trace-driven power modeling, aligned with C/SystemC workload traces.
• Perform synthesis-assisted calibration using average and worst-case power anchors when available.
• Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
• Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
• Contribute to scalable IP-wise composition for full-system power simulation.

What You Bring

• Bachelors degree 5+ years of experience or Masters degree 3+ years of experience.
• Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
• Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
• Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
• Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
• Familiarity with SystemC or transaction-level modeling.
• Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
• Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Preferred Qualifications

• Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
• Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
• Exposure to low-power design and thermal management.
• Exposure to power macromodeling, power estimation flows, or architectural power analysis.

Team Description:

The Brain Interfaces SoC Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

The engineer will be responsible for analog and mixed-signal chip design, from circuit design to layout and verification. Other responsibilities include:

• Design analog circuit building blocks and subsystems in transistor-level to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements while satisfying top-level specifications
• Works with layout teams to oversee block-level layout of multiple blocks
• Planning and execution of analog verification plan for portion of IP or chip and runs complex simulations and analyses (e.g., power, performance, linearity, yield) on designs
• Designs, programs, and runs complex tests and reviews tests of junior team members; ensures bugs and other issues are identified and appropriately analyzed
• Consults with internal or external users and third-party vendors to guide implementation and ensure alignment with their needs and goals

Required Qualifications:

• Bachelor of Science degree and additional experience in a related technical field for at least 5 years after receiving the BS degree
• Minimum 5 years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC and Class D audio amplifier, high speed PHY & SERDES) with a successful track record of silicon validation
• The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly

Preferred Qualifications:

• Masters or PhD in electrical engineering, physics, or other related fields
• Experience with design for high-volume production
• Experience in lab testing of high-precision analog and mixed-signal ICs
• Functional modeling experience and logic verification with Verilog AMS and SystemVerilog
• Experience in design and layout with advanced CMOS FinFET technologies
• Skills in scripting and automation for complex simulation scenarios

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity to partner with our electrical, microfabrication, chip designers, neuro and mechanical engineers.

Job Responsibilities:

We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in architecting and implementing innovative solutions with high energy-efficiency and compact silicon footprint and who thrive with the autonomy to propose creative approaches to problems. 

Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals with different skill sets and perspectives, and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

The Analog and Mixed-Signal IC Design Engineer Intern will be responsible for analog and mixed-signal chip design, from circuit design to layout and verification. 

• Define and implement innovative and optimal analog and mixed signal circuit architectures and transistor-level circuit solutions to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements
• Defines verification plan for a portion of IP or chip and runs complex simulations and analyses (e.g., power, performance, linearity, yield) on designs
• Designs, programs, and runs complex tests and reviews tests of other team members; ensures bugs and other issues are identified and appropriately analyzed

Key Qualifications:

• Minimum 1 years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC and Class D audio amplifier, high speed PHY & SERDES) with a successful track record of silicon validation
• Minimum 3 months experience of application of technical skills outside of the classroom (examples: laboratory, research, extracurricular project teams, open source contributions, volunteering, personal projects or prior internship/work experience)
• The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly

Preferred Qualifications:

• Skills in scripting and automation for complex simulation scenarios
• Experience in lab testing of high-precision analog and mixed-signal ICs
• Functional modeling experience and logic verification with Verilog AMS and SystemVerilog
• Experience in design and layout with advanced CMOS FinFET technologies
• Experience with design for high-volume production

Job Summary

We are seeking a talented Signal Processing Engineer to design, develop, and optimize advanced digital signal processing (DSP) algorithms for on-chip and embedded implementation. In this role, you will create efficient, hardware-friendly algorithms that run directly on custom SoCs, enabling real-time processing with constraints on power, latency, area, and throughput. You will collaborate closely with the SoC, Firmware, and Machine Learning teams to translate high-level signal processing needs into production-ready solutions.

Key Responsibilities

• Design and develop signal processing algorithms for sensing neural activity in the cortex (e.g. spike detection), monitoring cortical electrode health, and more.
• Design and develop numerical algorithms, such as custom data compression to increase radio throughput.
• Develop fixed-point or quantized versions of algorithms optimized for constrained hardware.
• Implement and verify algorithms in high-level languages and transition them to hardware-friendly representations.
• Perform algorithm-to-architecture mapping: analyze trade-offs between accuracy, latency, power, and resource utilization on the SoCs.
• Collaborate with the digital design team to define micro-architectures for custom on-chip processing pipelines, including dataflow, pipelining, and parallelization.

Required Qualifications

• Education: BS, MS or PhD in Electrical Engineering, Computer Engineering, Signal Processing, or a related field.
• Experience: 3+ years in digital signal processing algorithm development or real-world products, with a focus on embedded or hardware-constrained implementations.
• Fluent in signal processing fundamentals (both analog and digital) and strong numerical capabilities.
• Familiarity with fixed-point arithmetic, quantization effects, and numerical precision trade-offs.
• Proficiency in Python and C for algorithm prototyping and simulation.

Preferred Qualifications

• Hands-on experience with Verilog/VHDL, or transitioning algorithms to RTL.
• Experience with dedicated DSP cores or accelerators.
• Track record of optimizing for power/area/latency in resource-constrained environments.

Base Salary Range:

 $121,000 - $230,500

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

The Role 

We are seeking a Mixed-Signal Behavioral Modeling Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams.  

Responsibilities 

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.). 
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog. 
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog). 
• Integrate AMS models into digital verification environments (UVM-based). 
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification. 
• Support architectural exploration through early-phase modeling and system-level simulations.  
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions. 
• Work with digital and verification teams to ensure seamless integration of AMS models. 
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up. 
• Act as technical leader and subject-matter expert.  

Required Qualifications  

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field. 
• 2+ years of experience in analog/mixed-signal modeling and/or AMS verification. 
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages. 
• Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers). 
• Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar). 

Preferred Qualifications  

• Experience building AMS verification methodologies from scratch. 
• Familiarity with UVM-based verification and digital design flows. 
• Knowledge of signal processing theory, RF system modeling, or communication systems. 
• Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling. 
• Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

• Base salary range for this role is $130,000 – $180,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

The Role 

We are seeking a Senior Mixed-Signal Behavioral Modeling Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams.   

Responsibilities 

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.). 
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog. 
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog). 
• Integrate AMS models into digital verification environments (UVM-based). 
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification. 
• Support architectural exploration through early-phase modeling and system-level simulations.  
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions. 
• Work with digital and verification teams to ensure seamless integration of AMS models. 
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up. 
• Act as technical leader and subject-matter expert.  

Required Qualifications  

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field. 
• 5+ years of experience in analog/mixed-signal modeling and/or AMS verification. 
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages. 
• Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers). 
• Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar). 

Preferred Qualifications  

• Experience building AMS verification methodologies from scratch. 
• Familiarity with UVM-based verification and digital design flows. 
• Knowledge of signal processing theory, RF system modeling, or communication systems. 
• Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling. 
• Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

• Base salary range for this role is $160,000 – $230,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

ABOUT THE TEAM

The Electronic Warfare (EW) team is responsible for developing high-reliability radios, embedded processing, and power systems for software defined radio platforms. Working across hardware, software, and mission autonomy, the team delivers EW-critical electronics, PCB assemblies, and FPGA-based processing architectures that enable Anduril's next-generation autonomous electronic warfare platforms to operate in complex and contested environments. EW Electrical Engineers drive end-to-end development, from system architecture and circuit design to verification, integration, and test, ensuring scalable, mission-ready solutions that meet the performance, reliability, and survivability demands of the U.S. Military and modern EW warfare.

ABOUT THE JOB

We are looking for a Senior FPGA Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be responsible for the end-to-end design and verification of projects on the Xilinx SOC/FPGA platforms and helping to establish robust design processes. This will require expertise in SystemVerilog, FPGA, and Xilinx. If you are someone who has supported rapid software defined radio development, then this role is for you.

WHAT YOU'LL DO

• Work with software, and electrical, engineers to bring up state of the art boards for software defined radios.
• Integrate, and test, VHDL DSP Modules into larger system.
• Design custom, and optimized, HDL for software defined radios.
• Develop drivers for custom RF component boards (PLLs, mixed signal front ends, etc)

REQUIRED QUALIFICATIONS

• Strong experience with DSP implementation for embedded devices and/or software defined radios.
• Experience leading a team of FPGA engineers in the development of new custom PCB's and custom FPGA modules
• Experience with bring-up of high speed digital interfaces (PCIE,JESD,etc).
• HDL design experience using VHDL or Verilog.
• Experience with Linux development environment and tools (e.g. Git, gcc, etc)
• Eligible to obtain and maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Experience with embedded Linux driver development.
• Experience with Linux development environment and tools (e.g. Git, gcc, etc)
• Exposure to Wireless comms or Radar systems
• Experience with RF test equipment (Spec An, Sig Gens, Oscilloscope, etc)
• Experience with Xilinx AI Engines or NVDIA CUDA

ABOUT THE TEAM 

The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies.  The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.   

ABOUT THE JOB 

The Imaging team is seeking a Firmware Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. 

WHAT YOU’LL DO 

• FPGA architecture, standards, development and review processes 
• FPGA Development: Designing, architecting, simulating, and integrating VHDL designs into FPGAs or Systems on Chip (SoC) for optimized performance, resource utilization, and power efficiency. 
• Hardware/Software Integration: Collaborating with multidisciplinary teams (electrical engineers, software engineers, systems engineers) to ensure seamless integration of the firmware with the overall system, including processor bring-up and board support packages. 
• Testing and Validation: Developing robust test benches in VHDL/Verilog and utilizing lab tools such as oscilloscopes and logic analyzers for rigorous testing and validation of designs against functional specifications and performance requirements. 
• Optimization: Optimizing the algorithms for hardware acceleration, including MIPS optimization and efficient use of on-chip bus protocols like AXI or AXI-Stream.  

REQUIRED QUALIFICATIONS 

• Education: A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required. 
• Experience: 2+ years of experience developing HDL firmware for FPGA devices  
• Hardware Description Languages: Expertise in VHDL and/or Verilog/SystemVerilog is essential for RTL (Register Transfer Level) design. 
• FPGA Tools: Experience with industry-standard FPGA design tools such as Xilinx Vivado or Intel Quartus. 
• Debugging Skills: Strong hardware/software debugging skills using standard lab equipment. 
• Version Control: Proficiency with version control systems (e.g., Git) for collaborative development. 
• Eligible to obtain and maintain an active U.S. Secret security clearance 

PREFERRED QUALIFICATIONS  

• Demonstrated experience designing with multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, and common communication busses like SPI and I2C 
• Embedded software development experience with the use of timers, interrupts, hardware peripherals such as SPI controllers and ADCs 
• Knowledge of embedded Linux development, including device trees, hardware drivers, bootloaders, and basic Unix/Linux tools 
• Familiar with common programming languages like Python and MATLAB 
• Familiarity with infrared image sensor technology 

ABOUT THE TEAM

Anduril’s Electronic Warfare (EW) team is seeking experienced generalist embedded software engineers to build out the software ecosystem supporting a next-generation electronic warfare platform. As an Embedded software engineer, you’ll develop high-performance implementations of numerical algorithms, collaborate with digital systems engineers to enable maximum-performance interfaces between next-gen RF hardware and software, work with DSP and RFML engineers to rapidly deploy bleeding-edge capabilities to our customers, and collaborate with the wider software organization to deliver seamless integration of electronic warfare products with the Anduril Lattice system-of-systems suite. You will apply state-of-the-art software construction techniques to ensure the timely delivery of correct mission-critical code.

WHAT YOU'LL DO

• Work with digital systems engineers and systems programmers to develop high-performance hardware/software interfaces.
• Develop and maintain infrastructure and tools that enable DSP and RFML engineers to rapidly deploy algorithms and models to our assets.
• Develop high-performance implementations of numerical algorithms for generating, manipulating, and visualizing RF data.
• Develop correct, high-reliability software for controlling our electronic warfare assets, seamlessly integrated with the Anduril Lattice ecosystem.
• Utilize infrastructure providing deterministic builds and configuration management for deployment, guaranteeing software traceability and minimizing the maintenance burden of our products.

REQUIRED QUALIFICATIONS

• 2+ years professional experience in software engineering
• Experience with software-defined digital radio systems
• Eligible to obtain and maintain an active U.S. Top Secret SCI security clearance

PREFERRED QUALIFICATIONS

• Experience (professional or in the setting of an open source community) working with typed functional programming languages (Haskell, Scala, F#, OCaml, Rust, etc.)
• Experience with MATLAB, especially C code generation.
• Experience with Linux kernel module development
• Experience with FPGA development (Verilog, VHDL, etc.), especially Xilinx devices and tools.
• Experience with graphics programming (OpenGL, DirectX, Vulkan, etc.)
• Experience with Nix/NixOS

WHAT YOU’LL DO

• Lead an electrical engineering team in creating embedded compute solutions for vehicle management, DSP, and networking
• Own the full PCB development cycle of host boards for FPGAs / SoCs / SoMs (Developing requirements, schematic capture, board layout, bring-up, test, and integration)
• Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization)
• Collaborate with internal stakeholders to develop a strategy for developing and rolling out your compute solutions across Anduril in a scalable manner
• Create, maintain and communicate product development schedules with sufficient detail to ensure that all assigned personnel are aware of their tasks and deadlines.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree in Electrical Engineering or equivalent
• 7+ years of experience designing, testing and troubleshooting complex board designs in military, automotive or similar hardware.
• Experience with leading an Electrical Engineering team focused on Digital Design
• Proficiency in an HDL language (VHDL, Verilog)
• Familiarity with common MCU, CPU, FPGA devices and technologies.
• Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.
• Experience in design for signal integrity / power integrity.
• Knowledge of modern analog and digital electronics and electronic circuits.
• Competence with test equipment such as oscilloscopes, logic analyzers, thermal chambers, current-probes, and automation of tests.
• Proficient with Altium Designer or equivalent electronic design automation design tool
• Eligible to obtain and maintain an active U.S. Top Secret security clearance

PREFERRED QUALIFICATIONS

• Understanding and familiarity with DO-254, DO-178C, DO-160, DO-311A
• Understanding and familiarity with MIL-STD-810, MIL-STD-704, MIL-STD-461
• Expertise in computer networking
• Experience with implementing enhanced security measures

WHAT YOU’LL DO

• Lead an electrical engineering team in creating embedded compute solutions for vehicle management, DSP, and networking
• Own the full PCB development cycle of host boards for FPGAs / SoCs / SoMs (Developing requirements, schematic capture, board layout, bring-up, test, and integration)
• Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization)
• Collaborate with internal stakeholders to develop a strategy for developing and rolling out your compute solutions across Anduril in a scalable manner
• Create, maintain and communicate product development schedules with sufficient detail to ensure that all assigned personnel are aware of their tasks and deadlines.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree in Electrical Engineering or equivalent
• 7+ years of experience designing, testing and troubleshooting complex board designs in military, automotive or similar hardware.
• Experience with leading an Electrical Engineering team focused on Digital Design
• Proficiency in an HDL language (VHDL, Verilog)
• Familiarity with common MCU, CPU, FPGA devices and technologies.
• Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.
• Experience in design for signal integrity / power integrity.
• Knowledge of modern analog and digital electronics and electronic circuits.
• Competence with test equipment such as oscilloscopes, logic analyzers, thermal chambers, current-probes, and automation of tests.
• Proficient with Altium Designer or equivalent electronic design automation design tool
• Eligible to obtain and maintain an active U.S. Top Secret security clearance

PREFERRED QUALIFICATIONS

• Understanding and familiarity with DO-254, DO-178C, DO-160, DO-311A
• Understanding and familiarity with MIL-STD-810, MIL-STD-704, MIL-STD-461
• Expertise in computer networking
• Experience with implementing enhanced security measures

ABOUT THE TEAM

Anduril’s Electronic Warfare (EW) team is seeking experienced generalist embedded software engineers to build out the software ecosystem supporting a next-generation electronic warfare platform. As an Embedded software engineer, you’ll develop high-performance implementations of numerical algorithms, collaborate with digital systems engineers to enable maximum-performance interfaces between next-gen RF hardware and software, work with DSP and RFML engineers to rapidly deploy bleeding-edge capabilities to our customers, and collaborate with the wider software organization to deliver seamless integration of electronic warfare products with the Anduril Lattice system-of-systems suite. You will apply state-of-the-art software construction techniques to ensure the timely delivery of correct mission-critical code.

WHAT YOU'LL DO

• Work with digital systems engineers and systems programmers to develop high-performance hardware/software interfaces.
• Develop and maintain infrastructure and tools that enable DSP and RFML engineers to rapidly deploy algorithms and models to our assets.
• Develop high-performance implementations of numerical algorithms for generating, manipulating, and visualizing RF data.
• Develop correct, high-reliability software for controlling our electronic warfare assets, seamlessly integrated with the Anduril Lattice ecosystem.
• Utilize infrastructure providing deterministic builds and configuration management for deployment, guaranteeing software traceability and minimizing the maintenance burden of our products.

REQUIRED QUALIFICATIONS

• 7+ years professional experience in software engineering
• Experience (professional or in the setting of an open source community) working with typed functional programming languages (Haskell or Rust)
• Experience with software-defined digital radio systems
• Willingness to travel up 30%
• Eligible to obtain and maintain an active U.S. Top Secret SCI security clearance

PREFERRED QUALIFICATIONS

• Experience with MATLAB, especially C code generation.
• Experience with Linux kernel module development
• Experience with FPGA development (Verilog, VHDL, etc.), especially Xilinx devices and tools.
• Experience with graphics programming (OpenGL, DirectX, Vulkan, etc.)
• Experience with Nix/NixOS

WHAT YOU’LL DO

• Technical lead for electrical engineering team, creating embedded compute solutions for vehicle management, DSP, and networking.
• Own the full PCB development cycle of host boards for FPGAs / SoCs / SoMs (Developing requirements, schematic capture, board layout, bring-up, test, and integration).
• Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization).
• Collaborate with internal stakeholders to develop a strategy for developing and rolling out your compute solutions across Anduril in a scalable manner.
• Create, maintain and communicate product development schedules with sufficient detail to ensure that all assigned personnel are aware of their tasks and deadlines.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree in Electrical Engineering or equivalent
• 15+ years of experience designing, testing and troubleshooting complex board designs in military, automotive or similar hardware.
• Experience with leading an Electrical Engineering team focused on Digital Design
• Proficiency in an HDL language (VHDL, Verilog)
• Familiarity with common MCU, CPU, FPGA devices and technologies.
• Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.
• Experience in design for signal integrity / power integrity.
• Knowledge of modern analog and digital electronics and electronic circuits.
• Competence with test equipment such as oscilloscopes, logic analyzers, thermal chambers, current-probes, and automation of tests.
• Proficient with Altium Designer or equivalent electronic design automation design tool
• Eligible to obtain and maintain an active U.S. Top Secret security clearance

PREFERRED QUALIFICATIONS

• Understanding and familiarity with DO-254, DO-178C, DO-160, DO-311A
• Understanding and familiarity with MIL-STD-810, MIL-STD-704, MIL-STD-461
• Expertise in computer networking
• Experience with implementing enhanced security measures

ABOUT THE TEAM

Anduril’s Electronic Warfare (EW) team is seeking experienced generalist embedded software engineers to build out the software ecosystem supporting a next-generation electronic warfare platform. As an Embedded software engineer, you’ll develop high-performance implementations of numerical algorithms, collaborate with digital systems engineers to enable maximum-performance interfaces between next-gen RF hardware and software, work with DSP and RFML engineers to rapidly deploy bleeding-edge capabilities to our customers, and collaborate with the wider software organization to deliver seamless integration of electronic warfare products with the Anduril Lattice system-of-systems suite. You will apply state-of-the-art software construction techniques to ensure the timely delivery of correct mission-critical code.

WHAT YOU'LL DO

• Work with digital systems engineers and systems programmers to develop high-performance hardware/software interfaces.
• Develop and maintain infrastructure and tools that enable DSP and RFML engineers to rapidly deploy algorithms and models to our assets.
• Develop high-performance implementations of numerical algorithms for generating, manipulating, and visualizing RF data.
• Develop correct, high-reliability software for controlling our electronic warfare assets, seamlessly integrated with the Anduril Lattice ecosystem.
• Utilize infrastructure providing deterministic builds and configuration management for deployment, guaranteeing software traceability and minimizing the maintenance burden of our products.

REQUIRED QUALIFICATIONS

• 7+ years professional experience in software engineering
• Experience (professional or in the setting of an open source community) working with typed functional programming languages (Haskell or Rust)
• Experience with software-defined digital radio systems
• Eligible to obtain and maintain an active U.S. Top Secret SCI security clearance

PREFERRED QUALIFICATIONS

• Experience with MATLAB, especially C code generation.
• Experience with Linux kernel module development
• Experience with FPGA development (Verilog, VHDL, etc.), especially Xilinx devices and tools.
• Experience with graphics programming (OpenGL, DirectX, Vulkan, etc.)
• Experience with Nix/NixOS

ABOUT THE TEAM
Anduril’s Electronic Warfare (EW) team is seeking an experienced embedded software engineer to support next-generation electronic warfare platforms in production. As a Production Embedded software engineer, you’ll develop and maintain EW product software specific to a production environment, collaborate with manufacturing and test automation engineers to improve testability, and collaborate with the wider embedded software organization to ensure a seamless new product introduction.

WHAT YOU'LL DO

• Contribute to design reviews acting as an expert in Built In Test, design for test, and fault isolation and detection.
• Define Built In Test strategy and requirements for automated testing, supporting fault detection, isolation, and reporting.
• Develop and maintain production SW builds that enable testing and troubleshooting at board-level and unit-level RF test stations.
• Develop and regression test high-reliability software for controlling our electronic warfare assets, seamlessly integrated with production test automation.
• Utilize infrastructure providing deterministic builds and configuration management for production deployment, guaranteeing software traceability and minimizing the maintenance burden of manufacturing.

REQUIRED QUALIFICATIONS

• 7+ years professional experience in software engineering
• Experience (professional or in the setting of an open source community) working with typed functional programming languages (Haskell or Rust)
• Experience with Built In Test development
• Eligible to obtain and maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Experience with software-defined digital radio systems
• Experience with MATLAB, especially C code generation.
• Experience with FPGA development (Verilog, VHDL, etc.), especially Xilinx devices and tools.
• Experience with graphics programming (OpenGL, DirectX, Vulkan, etc.)
• Experience with Nix/NixOS
• Experience with Linux boot stages
• Basic understanding of RF test equipment, such as signal generators, spectrum analyzers 

At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines – they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.

As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent’s next-generation RISC‑V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high‑performance computing roadmap.

We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.

This role is hybrid, based in our Boston, MA office.

Who you are

• Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification.
• Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
• Familiar with HDLs such as Verilog/SystemVerilog, and interested in learning Formal verification, Cocotb, and UVM‑based verification methodologies.
• Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl) to automate tasks.
• Detail-oriented problem solver who enjoys debugging complex issues, reasoning about corner cases, and working from specifications.
• Collaborative team member with clear communication skills, able to document work and discuss trade‑offs with RTL, architecture, and validation teams.

What We Need

• Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
• Write and refine verification test plans from architectural and micro‑architectural specifications, with a strong focus on corner cases and coverage.
• Develop constrained‑random and directed tests, run regressions, and triage failures by working closely with RTL designers to root-cause issues.
• Analyze functional and code coverage results, identify gaps, and propose additional tests or checks to drive coverage closure.
• Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time.
• Partner with cross‑functional teams (architecture, design, performance, validation) to align on expected behavior and sign‑off criteria for silicon.
• Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.

What You Will Learn

• End‑to‑end SoC design and verification flow for cutting‑edge RISC‑V and AI accelerator architectures.
• Industry‑standard verification methodologies (SystemVerilog/UVM), including testbench architecture, stimulus generation, and scoreboard/checker design.
• Hands-on experience with simulation, regression, and coverage tools used in large‑scale industrial verification environments.
• How to read and interpret hardware specifications, micro‑architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
• Exposure to high‑performance interconnects, memory controllers, and accelerators, and how they are verified at IP, subsystem, and SoC levels.
• Best practices for collaborating in a silicon development team, including code review, documentation, and cross‑site communication.

USA Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Jan–Apr work term, Sept–Dec recruit.
• Summer Term: May–Aug work term, Oct–Apr recruit.
• Fall Term: Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Austin, TX, Fort Collins, CO or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Santa Clara, CA or Austin, TX

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• You are fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM.
• You have hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
• You bring strong debug and problem-solving skills across design hierarchies and collaborate effectively with design, PD, verification, and test teams.

What We Need

• Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
• Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

What You Will Learn

• How to drive DFT for industry-leading AI/ML architectures, working on high-performance chips with aggressive performance and power targets.
• Practical strategies to reduce test cost while maintaining coverage, and to design DFT hooks that accelerate silicon bring-up and yield learning.
• How to minimize DFT intrusions while integrating cleanly with RTL, verification, physical design, and production test flows.
• How a senior, cross-functional ASIC team collaborates across design, PD, verification, and manufacturing to achieve first-pass silicon success on advanced nodes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we are building open, state of art compute for AI and RISC‑V CPUs. You will lead the technical efforts and strategy around our existing emulation infrastructure for high‑performance CPUs that power these products. Your work will directly enable silicon bring‑up, validation, and customer‑ready systems.

This role is hybrid, based out of Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have strong background in CPU verification, emulation, and debug.
• You are fluent in Verilog and SystemVerilog for complex SoC designs.
• You are a technical leader who drives complex debug efforts, solves ambiguous technical problems, and mentors younger engineers.
• Experience with Zebu emulation platforms is a significant plus.
• You collaborate closely with design, verification, and vendors to move fast and unblock teams.

What We Need

• Lead the technical strategy and execution to scale and optimize existing emulation infrastructure on commercial and open‑source platforms.
• Enable the emulation infrastructure and workflow, including producing reliable emulation builds.
• Drive and lead complex cross-functional debug and root cause analysis efforts.
• Optimize emulation performance and regression flows with Design Verification teams and tool vendors.

What You Will Learn

• How to bring state of art AI and CPU architectures to life on emulation.
• How to design large‑scale emulation regressions that mirror real customer workloads.
• How to tune emulation performance across different vendors and hardware platforms.
• How open hardware and software come together across Tenstorrent’s full compute stack.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors. This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies.
• Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc).
• Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.
• Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

What We Need

• Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST).
• Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc).
• Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs.
• Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness.
• Participate in ATE targeted test patterns, validation and silicon- debug
• Work closely with test and product engineering teams on silicon characterization and validation.

What You Will Learn

• Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies
• In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes
• Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success
• Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is accelerating the future of AI and high-performance compute by building industry-leading CPU and AI architectures. As an Automotive and Robotics SoC Architect, you will define scalable, top-down system architectures that unify our CPU and AI technologies for next-generation automotive applications. This senior technical role shapes the architectural direction of our automotive and robotics portfolio, ensuring our products meet the industry's highest expectations for performance, safety, reliability, and security. This position is central to how Tenstorrent delivers world-class automotive solutions and requires strong technical leadership, systems thinking, and cross-functional collaboration.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A systems thinker who can architect complex SoCs from concept to execution.
• A strong communicator who can articulate technical direction across engineering teams and external partners.
• Someone with deep knowledge of safety-critical systems and the unique needs of automotive environments.
• An innovator who can identify future use cases and propose next-generation architectural solutions.
• A leader who thrives in a highly technical, cross-functional, fast-moving environment.

What We Need

• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or related field.
• Extensive experience designing complex SoCs, ideally in automotive applications.
• Proficiency in hardware description languages such as Verilog or VHDL.
• Experience with hardware/software co-design and co-verification.
• Knowledge of automotive safety standards (e.g., ISO 26262) and security principles.
• Someone comfortable with up to 25% international travel. 
• Experience with both cameras, sensors, and others is a plus.

What You Will Learn

• How cutting-edge CPU and AI architectures are adapted for automotive-grade environments.
• Best-in-class methodologies for safety-critical SoC design, verification, and system integration.
• How to translate emerging automotive use cases into scalable, future-proof SoC architectures.
• Approaches to hardware-level security, robustness, and cyber-resilience in automotive compute systems.
• Cross-functional collaboration strategies that drive innovation across architecture, software, DV, and product teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking a highly motivated and passionate CPU Architect to join our processor architecture team, focusing on the CPU’s load-store unit. In this role, you will contribute to the design, analysis, and optimization of cutting-edge CPU architectures with an emphasis on a high-performance load-store unit. This is an excellent opportunity to work alongside world class architects in high-performance computing and processor design.

This role is Remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Drive the architecture, micro-architecture, design and optimization of the CPU load-store unit for Tenstorrent’s high-performance out-of-order RISCV CPUs
• Propose new implementations to optimize load-store PPA
• Perform simulations, modeling, and performance analysis of advanced CPU features and state-of-the-art data prefetchers
• Collaborate with hardware and software teams to optimize memory access patterns and system performance.
• Stay up to date with industry trends and emerging technologies in CPU architecture and the memory subsystem
• Support documentation and presentation of architectural decisions, trade-offs, and findings.

Experience & Qualifications:

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience).
• Strong understanding of computer architecture fundamentals, including memory hierarchy, cache coherence, and data prefetching
• Familiarity with performance modeling and simulation tools (e.g., Gem5, SimpleScalar, or similar).
• Basic knowledge of hardware description languages (e.g., Verilog, VHDL) and system-level programming (C, C++).
• Problem-solving skills and ability to analyze complex system interactions.
• Excellent communication and teamwork abilities.
• Hands-on experience with performance profiling tools and benchmarking methodologies.
• Exposure to parallel processing architectures and multi-core systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the unit specification, RTL design, and unit verification.

This role is Remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Key Responsibilities:

• RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure.
• RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA.
• AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process.
• Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team.

Qualifications:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V.
• Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…)
• Deep understanding of CPU microarchitecture and PPA trade-off.
• Basic understanding of RISC-V Architecture including V-extension is preferred.
• Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.
• Excellent problem-solving abilities and analytical skills.
• Strong communication skills, with the ability to convey complex technical concepts to diverse audiences.
• Ability to work collaboratively in a team-oriented environment and across multiple disciplines.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Who we are

Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.

As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.

What you will be doing

We are seeking a highly skilled CODEC Video Compression Engineer/Developer to build low cost FPV digital video, similar to DJI 04.

They will design, optimize, and implement low-latency advanced video compression algorithms while maintaining high visual quality, for real time video streaming application. You will work closely with cross-functional teams to deliver high-quality, low-latency wireless video. This role blends deep knowledge of video processing, mathematics, and software/hardware optimization to enable video transmission with minimum latency and reduced bandwidth usage.

Responsibilities

• Design and implementation of dual CPU/GPU hybrid video compression encoder architecture that can seamlessly combine SW and HW encoding engines
• Design, develop, and optimize video compression algorithms in C/C++, Assembly, Rust or similar languages
• Implement and optimize encoder/decoder pipelines for real-time applications
• Analyze and improve codec performance for speed, quality, and efficiency across CPU, GPU
• Perform error handling
• Conduct performance benchmarking, debugging, and quality assurance testing: Develop and use objective and subjective metrics to evaluate codec performance
• Collaborate with hardware and software teams to integrate CODEC solutions into products, using high-level synthesis, or FPGA/ASIC design flows
• Stay updated on emerging video standards, compression techniques, and industry trends

You should have the following

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field
• Solid understanding of video compression theory, motion estimation, transform coding, MC DCT, VBSMC, entropy coding, and rate control
• Codec implementation experience in developing actual software and hardware that encodes and decodes video data according to a specific compression format
• System Verilog experience (HLS/C++)
• Solid understanding of video compression standards (H.264, H.265/HEVC, H.266, VP9, AV1) and rate control algorithms
• Experience with hardware implementations using dedicated chips (FPGAs, ASICs, DSPs), and hybrid implementations using software for control logic with hardware accelerators GPUs (NVENC, NVDEC). Experience with GPU acceleration (CUDA, Vulkan, OpenCL)
• Strong proficiency in C/C++ and experience with SIMD optimizations (SSE, AVX, NEON)
• Front-end development for ****control of performance-critical code
• Experience with multithreaded programming and performance profiling tools, debugging, and performance optimization
• Excellent problem-solving skills and ability to work in a collaborative environment

Nice to have

• Backend development (FFmpeg framework, GStreamer)
• Knowledge of container formats (MP4, MKV, MPEG-TS)
• Experience with ML–based video enhancement or compression

US Salary Range

$120,000 - $220,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.

We’re an equal opportunity employer. We welcome all applicants without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

About Epirus

Epirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques that allow power-hungry systems to do more with less.  

Job Summary: This is an exciting role in an innovative company. The ideal candidate for the position is someone who has experience developing high-performance real-time, autonomous software systems to rapidly develop next-generation products.  Employ your expertise by developing software systems that support functions such as autonomous target tracking, agile electronic beam-forming, and real-time hardware control.

Responsibilities: 

• Design and implement software of embedded devices and systems from requirements to production and deployment 
• Design, develop, code, test, and debug system software 
• Build real-time control software for a variety of projects 
• Analyze and enhance the efficiency, stability and scalability of system resources 
• Direct software QA and optimize I/O performance 
• Interface with hardware design and development 
• Assess third-party and open-source software 
• Lead teams to create minimum viable products from an idea 
• Derive software frameworks and architectures to accelerate development 
• Mentor peers to advance team velocity

Basic Qualifications:

• 5+ years of development in C and C++ 
• 3+ years working with embedded systems 
• Additional experience with one or more modern systems language(s): Python, Java, VHDL, Verilog, Go, Rust, etc. 
• Versed in multithreaded design (concurrency primitives, resource management, etc.) 
• Competent in computer science concepts (algorithms, data structures, object-oriented programming, etc.) 
• Strong foundations in mathematics and linear algebra 
• Adequate knowledge of reading schematics and data sheets for components 
• Bachelor’s degree in computer science or a similar discipline, Master’s degree preferred
• This is an on-site position; availability to work in our HQ in Torrance is required

Preferred Skills and Experience:

• 2+ years of experience with Xilinx FPGA and Embedded Cortex CPU architectures 
• Experience building software for real-time operating environments with specific latency requirements 
• Experience with Embedded Linux and/or software integration with FPGA firmware 
• Knowledge or experience with digital signal processing (DSP) or radio frequency (RF) technologies 
• User experience with DevOps Pipeline tools 
• Experience with Docker or Helm  
• Scrum Master Certification 
• Desire to mentor new hires 
• Exposure or interest in sensor fusion, machine learning, or AI

ITAR REQUIREMENTS: 

• To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

At Epirus, you’ll work with technical peers and great people—and get first crack at some of the defining technology challenges of our time. Here, “impossible” is just a challenge. We're a diverse, fast-growing team of change-makers fueling the future of energy with revolutionary solutions. Join us and rewrite the rules. 

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.

Key Responsibilities

• Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
• Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
• Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
• Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• SystemVerilog/Verilog familiarity.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

At Optiver we pride ourselves on being real engineers, not just coders. Our engineers work closely with traders to identify the business problems we face and determine how they should be solved. We apply a disciplined and scientific approach. We engineer simple, well-architected solutions that meet the dynamic needs of our traders. Our passion is to solve problems which really matter to the business, and we take pride in the quality of our solutions.

Hardware Engineers at Optiver build hardware-based trading systems ranging from low latency algorithms to high bandwidth computation. They are responsible for owning all aspects of the development process from ideation to implementation creating bespoke solutions to our complex trading problems. Their systems have little room for failure which add to the stability of the market, not detract from it. Working in close collaboration with software engineers and traders, hardware engineers deeply understand our trading problems and create dynamic, well-architected systems that make an impact in a matter of days and weeks rather than months and years.

What you’ll do: 

• Accelerate network infrastructure and trading system components with high-speed hardware designs.
• Research new low-latency techniques and platforms and identify opportunities for integration with our trading system.
• Work in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware available or build in-house versions to ensure our FPGAs can interface with cutting edge server hardware.
• Manage relationships with 3rd party vendors.

What you’ll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• A Bachelor’s degree in CE, EE, CS, or related technical field.
• Experience designing, coding, testing, and verifying FPGAs and/or ASICs.
• Experience coding in VHDL, Verilog, SystemVerilog as well as C or C++.
• Experience with RTL synthesis, writing timing, area, and other relevant constraints.
• Experience with digital simulators and self-checking test benches.
• Experience supporting post-silicon bring-up and debugging a plus.
• Ability to work closely with software developers to rapidly deliver integrated systems.

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Optiver Chicago’s culture parallels the energetic city we’re immersed in. Home to the Chicago Board of Trade, Chicago Board Options Exchange, and Chicago Mercantile Exchange, Chicago has established itself as the trading capital of the US. Active on leading US exchanges, Optiver’s Chicago office trades a wide range of products from listed derivatives to cash equities, ETFs, bonds and foreign exchange

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Optiver’s hardware research, development, and manufacturing team, based in Austin, builds some of the world’s fastest and most competitive trading systems. As we continue to grow, we’re looking for a software engineer to help develop the OS and software that powers our custom hardware.

This role spans everything from low-level hardware integration to collaborating with infrastructure teams that manage production systems and traders who configure them to fit their specific needs. While we primarily use Python and Linux, you’ll also encounter a diverse tech stack including TCL, C, C++, ASM, VHDL, and DSLs across platforms from x64 servers to embedded cores.

What you’ll do:

As Software Engineer, your key responsibilities include:

• Designing and maintaining the OS and software stack behind our trading hardware
• Building and supporting Python-based interface layers to control and monitor hardware systems
• Developing software for STM processors embedded on prototype boards
• Managing and supporting a fleet of hardware systems in a live production environment
• Collaborating closely with hardware, infrastructure, and trading teams to ensure seamless system performance
• Contributing to infrastructure automation and transitioning into embedded development and low-level hardware logic over time

What you’ll get:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Strong foundation in computer science fundamentals and hardware systems
• Proficiency in Python, including familiarity with relevant libraries and APIs
• Experience writing software in C/C++
• Creative problem-solving skills at the system level
• Ability to collaborate with developers and researchers

Nice to have:

• Experience with low-level hardware/software interactions (drivers, buses, pins, registers, etc.)
• Ability to read and interpret datasheets and electrical engineering schematics
• Familiarity with devices and drivers in Linux
• Experience with FPGA design using VHDL/Verilog and the Vivado suite of tools
• Knowledge of communication protocols, especially Ethernet
• Exposure to network equipment operating systems like Cisco IOS, Arista EOS, or Juniper MOS
• Experience working with high-performance trading network hardware (both packet- and circuit-switched)

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Optiver is looking to add FPGA Engineers to its Automated Trading Systems (ATS) team. ATS solve a variety of problems with high degrees of difficulty: managing scarce bandwidth resources, responding to market events with extremely low latency, and automatically pricing diverse sets of financial instruments with near-zero error tolerance. We build systems with little room for failure which add to the stability of the market, not detract from it. These systems must be simple, flexible, and well-architected so they can quickly be changed to meet the dynamic needs of our traders. We already have a team of great engineers, but we need more.

Optiver Hardware Engineers:

• Accelerate network infrastructure and trading system components with high speed hardware designs.
• Research new low-latency techniques and identify opportunities for integration with our trading system.
• Work in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware available, ensuring our FPGAs can interface with cutting edge server hardware.

What you'll need:

• A Bachelor’s degree in CE, EE, CS, or related technical field
• Experience designing FPGAs in VHDL or Verilog. We use VHDL.
• Experience coding in VHDL, Verilog, SystemVerilog, C, or C++
• Experience with digital simulators and self-checking test benches a plus
• Ability to work closely with software developers to rapidly deliver integrated systems.

Who we are:

Optiver is a tech-driven trading firm and leading global market maker. As one of the oldest market making institutions, we are a trusted partner of 70+ exchanges across the globe. Our mission is to constantly improve the market by injecting liquidity, providing accurate pricing, increasing transparency and acting as a stabilising force no matter the market conditions. With a focus on continuous improvement, we participate in the safeguarding of healthy and efficient markets for everyone who participates.

Based in ‘The Domain’ neighborhood, Optiver’s Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software and hardware engineering initiatives. With tech innovation an integral part of our core business, the booming city proved an ideal backdrop for our heavy investment into machine learning, research infrastructure and big data computing. What’s more, with world-class music, food and art scenes, as well as countless scenic outdoor activities, the quality of life for Austin Optiverians is second to none.

About Epirus  

Epirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques which allow power-hungry systems to do more with less.

Job objective: This is an exciting role an innovative, high-growth defense technology company. The ideal candidate for the position is someone who has experience designing, verifying, and integrating state-of-the-art FPGA systems and embedded processing solutions for RF applications. As a Sr. FPGA Engineer, you will work closely with a talented, multi-disciplinary engineering team in a fast-paced environment to apply emerging technologies in innovative ways to rapidly produce new products.     

Duties  

• Design and verification of RTL modules for FPGA applications
• Ownership of entire FPGA designs from initial architecture trades through implementation, verification, and hardware bringup, including FPGA sizing estimation and IO planning.
• Lead initial testing and bring-up of custom FPGA circuit cards, validating functionality of on-board peripherals including memory interfaces, Ethernet controllers, and integrated sensors.
• Automating test environment (up to and including hardware-in-the-loop testing), lab equipment, and measurement devices
• Capturing design tradeoffs, state machine flow, system address maps, and block diagrams 

Required Qualifications  

• Bachelor’s degree in Electrical Engineering or a related field.
• 5+ years of experience in FPGA design, implementation, and testing
• Extensive experience implementing FPGA designs and embedded processing designs on embedded hardware
• Experience working with latest generation state-of-the-art Xilinx/Intel Parts and associated tool sets (Vivado, Quartus)
• Understanding of common digital communication protocols (SPI, I2C, UART)
• Development Experience of Integrated Embedded Applications (ARM, GPU)
• Experience with standard bus and streaming protocols, such as AXI and AXI-Stream
• Experience with Continuous Integration and Continuous Delivery processes
• Active Secret or Top Secret clearance, or ability to obtain one desired but not required.  

Desired Qualifications   

• Experience with design automation, scripting languages (TCL, Python, Perl, Matlab)
• Knowledge of Advanced Firmware Verification Testbench Development (UVM, System Verilog)
• Skilled with Advanced High-Speed Verilog/VHDL Designs including High Speed Memory Interfaces (DDR4, HBM) and High Speed SerDes IO and Protocols (100GE, JESD204B, Interlaken)
• Experience implementing Complex DSP Algorithms on FPGAs using tools such as Matlab, Simulink, HDL Coder to implement advanced communications or other designs in FPGA
• Experience collaborating with software engineering team in an SoC environment to develop designs that incorporate HDL combined with embedded Linux
• Good written and oral communication skills
• Collaborative; capable of working across all levels of the organization
• Organized; comfortable working in a fast-paced, ever-changing environment 

About the Position

We are looking to hire an Engineer with experience in both software and hardware design to help us build our FPGA-based applications. 

We're big believers in the ability of tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our FPGA Engineering work, and we’re looking for people who are interested in using programming language technology to improve the process of designing, testing, and validating hardware designs. We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly integrated into our development environment, so you’ll also gain lots of exposure to the libraries and tools that are foundational to our internal systems. No previous knowledge of Hardcaml is required.

In this role, you’ll work on the ground-up design and implementation of new FPGA applications, and help extend and refine the high-level design and testing tools that we use internally. Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration, but you can also expect to work with some Verilog and C. While you don’t need to have worked with OCaml specifically, a good background in typed programming languages is a plus.

If you’d like to learn more, you can read about our interview process, meet some of our newest hires, or check out our OCaml All The Way Down talk and Programmable Hardware podcast episode.

About You

We don’t expect you to have a background in OCaml, finance, or any other specific field—we’re looking for smart programmers who will approach hardware design with a software engineering mindset. We’re more interested in how you think and learn than what you currently know. You should be:

• A top-notch programmer with a love for technology
• Comfortable with a software programming language
• Intellectually curious, collaborative, and eager to learn
• Humble and unafraid to ask questions and admit mistakes
• Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
• Experienced working with FPGA vendor tools (Vivado or Quartus)
• Experienced with building a working FPGA project through an academic, professional, or personal project
• Interested in learning how to use FPGAs in the context of networking

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

About Epirus 

Epirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques which allow power-hungry systems to do more with less.  

At Epirus, we’re always looking ahead—and that includes building relationships with forward-thinking engineers who want to shape the future of defense technology. While we may not have an immediate opening that matches your background, we invite you to express interest in future Software Engineering opportunities.

Whether your strengths lie in Backend Software, Frontend/UX/UI, Software Testing (HIL), or Software Infrastructure, there could be a place for you on our team as we grow.

**This posting is for resume collection in anticipation of future opportunities. A member of our Talent Acquisition team will contact you if a suitable position becomes available.**

Learn More about our Software Engineering Roles:

Software Engineering Roles (backend or embedded)

• Design and implement software of embedded devices and systems from requirements to production and deployment 
• Design, develop, code, test, and debug system software 
• Build real-time control software for a variety of projects 
• Analyze and enhance the efficiency, stability and scalability of system resources 

Frontend UX/UI Engineering Roles

• Collaborate effectively with UX/UI designers to ensure the seamless translation of design concepts into functional, user-friendly interfaces
• Collaborate effectively with our backend teams to improve API designs
• Integrate novel front-end tech into our stack
• Optimize not just performance but developer experience, CI/CD, and testing

Infrastructure Engineering Roles

• Design a cloud infrastructure that is secure, scalable, and highly available on AWS.
• Work collaboratively with software engineering to define infrastructure and deployment requirements.
• Provision, configure, and maintain AWS cloud infrastructure defined as code.
• Ensure configuration and compliance with configuration management tools.

Basic Qualifications

• 2+ years of experience in development in C and C++ 
• Bachelor’s in Computer Science, Electrical Engineering, Computer Engineering, or related field,
• Experience with one or more modern systems language(s): Python, Java, VHDL, Verilog, Go, Rust, etc. 

Preferred Qualifications

• Strong foundation in networking concepts and Linux system administration
• Experience with Xilinx FPGA and Embedded Cortex CPU architectures. Experience with
• Drone Control Software (e,g. ArduPilot, PX4)
• Professional front-end/UI development experience, JavaScript and TypeScript Expert
• Mastery in building UI applications with React
• Experience building and maintaining AWS infrastructure (VPC, EC2, Security Groups, IAM, ECS, CodeBuild, S3, RDS

ITAR REQUIREMENTS:  

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.   

At Epirus, you’ll work with technical peers and great people—and get first crack at some of the defining technology challenges of our time. Here, “impossible” is just a challenge. We're a diverse, fast-growing team of change-makers fueling the future of energy with revolutionary solutions. Join us and rewrite the rules. 

CHAOS Industries is redefining modern defense with omniscient systems purpose-built for today’s realities. Designed and built by top U.S. military veterans and Silicon Valley innovators, CHAOS Industries’ products are powered by Coherent Distributed Networks (CDN™), empowering warfighters, commercial air operators, and border protection teams to act faster, adapt rapidly, and stay ahead of evolving threats. In a world where technological threats move at unprecedented speed, CHAOS Industries delivers advanced sensing and detection solutions that give the ultimate advantage: time.   

CHAOS Industries was founded in 2022 and has raised $1B in total funding from leading investors including 8VC, Accel, and NEA. The company is headquartered in Los Angeles, with offices in Washington, D.C., San Francisco, Seattle, and London. For more information, please visit www.chaosinc.com. 

Role Overview:

CHAOS is seeking a highly-skilled and motivated FPGA Engineer to join our team supporting our R&D and product engineering initially focusing on our next-generation radar products. This is a highly collaborative role which will allow you to work on multiple capabilities within our product offerings. As a member of our engineering team, you also have the opportunity to expand your skillset across our product families.   

Responsibilities: 

• Design and implement complex FPGA designs targeting our next-generation sensor products
• Support system integration of FPGA designs with complex software systems
• Support deployed FPGA capabilities in the hands of our U.S. and international customers
• Work full-time on-site in our office in Hawthorne, California

Minimum Requirements:

• Bachelor’s or higher degree in Computer Engineering, Electrical Engineering, Computer Science or related degree
• 5+ years of experience in a professional setting performing detailed digital RTL design targeting FPGAs
• Extensive experience with the entire FPGA design life cycle: RTL design, behavioral simulation, place and route, timing analysis, hardware integration
• Extensive experience developing in Verilog and SystemVerilog
• Extensive experience with the ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream)
• Extensive experience with the AMD (Xilinx) Vivado Design Suite and SoC FPGAs (Zynq, Ultrascale/Ultrascale+, Versal)
• Experience with Network Protocols (TCP/UDP/IP)
• Experience with Serial Protocols (I2C, JTAG, UART, SPI, CAN)
• Experience using Bash and Python for scripting and testing
• Experience modifying software drivers and applications when needed to validate FPGA designs
• Experience with Agile lifecycle processes including Scrum, Continuous Integration, and Test-Driven Development Methodologies
• Ability to work with minimal supervision and collaborate on small teams
• U.S. Person status is required as this position will require the ability to access U.S.-only data systems 

Preferred Requirements:

• Experience designing and implementing highly performant baseband signal processing in an FPGA
• Experience translating high level algorithms from Simulink/MATLAB or similar into RTL including FPGA Vendor IP implementations
• Experience developing and implementing software drivers (C/C++/Python) to interface with FPGA designs
• Experience with FPGA Ethernet IP blocks (1G/10G/40G/100G)
• Experience with Software-Defined Radios (SDRs) (e.g. Ettus, NI, HackRF)
• Experience with Analog Device Transceivers
• Experience in Ground or Airborne Sensors (Radars, EO/IR, EW, etc.)
• Experience with Time Synchronization technologies (NTP / PTP)
• Experience with HLS Synthesis and languages (C/C++/SystemC/Chisel)
• Experience with VHDL
• Experience with high-speed, multi-layer, digital printed circuit board (PCB) design
• Current or previous DoD security clearance 
• Experience with GPUs and/or AI engines
• Experience with git
• Experience with Bitbucket CI, Jenkins or similar CI/CD flows
• Experience with DoD & related System/SW Architectures and messaging standards (e.g. OMS, SOSA, Link-16, etc) 

Why CHAOS?

• Health Benefits: Medical, dental, and vision benefits 100% paid for by the company
• Additional benefits: 401k (+ 50% company match up to 6% of pay), FSA, HSA, life insurance, and more
• Our Perks: Free daily lunch, ‘No meeting Fridays’, unlimited PTO, casual dress code
• Compensation Components: Competitive base salaries, generous pre-IPO stock option grants, relocation assistance, and (coming soon!) annual bonuses
• Team Growth: 200 employees and counting across 5 global offices

The stated compensation range reflects only the targeted base compensation range and excludes additional earnings such as bonus, equity, and benefits. If your compensation requirements fall outside of the range, we still encourage you to apply. The salary range for this role is an estimate based on a range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations.

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