Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

Tenstorrent is looking  for a STA methodology engineer who owns timing across advanced-node, high-performance, low-power designs, bringing deep expertise with PrimeTime, noise/crosstalk/OCV analysis, and strong scripting skills. They will lead the development and optimization of end-to-end STA methodologies and flows, drive data- and ML-assisted timing automation, and partner closely with logic, physical design, DFT, and EDA vendors to solve complex timing challenges across multiple IPs and products. 

This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Fort Collins, CO.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who you are

• An experienced Static Timing Analysis (STA) / timing methodology engineer with a BS/M in Electrical or Computer Engineering (or equivalent experience) 5+ years in industry, focused on high-performance and low-power designs at advanced technology nodes. As well as a deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• You are fluent with PrimeTime and related signoff tools (e.g., PT-SI, PTPX, PT-ECO) and have extensive hands-on experience driving signoff correlation, advanced static timing analysis, and signoff closure.
• You are strong at debugging timing constraints, resolving timing correlation issues, and developing effective timing closure strategies.
• You write robust, production-quality scripts in Tcl, Python, and/or Perl and are comfortable building and maintaining CAD utilities and flow components.

What we need

• A senior methodology owner to lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes. Experience developing and enhancing STA methodologies across the full RTL-to-GDS flow, including: Early timing estimation and timing feasibility checks. Timing optimization techniques in synthesis and place-and-route. Timing signoff methodologies and criteria. Post-route timing ECO strategies and execution.
• A technical leader to architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA (Power, Performance, Area) and runtime efficiency.
• A methodology engineer who can explore and deploy data-driven and ML-assisted techniques to: Improve STA automation. Predict and prioritize timing risk. Guide optimization strategies across blocks and full-chip. Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity.
• A methodology owner who continuously refines workflows and introduces new technologies to ensure robust, PPA-optimized timing solutions across all product lines.

What you will learn

• How to scale STA methodologies across a diverse portfolio of IP and SoC programs, balancing aggressive performance targets with strict power and area constraints.
• Best practices for integrating data-driven and ML-assisted approaches into timing flows to improve automation, predictability, and decision-making.
• How to influence tool roadmaps by partnering closely with leading EDA vendors on advanced-node timing, noise, and variability challenges.
• How to operate within and help shape a rapidly evolving startup design environment, including tradeoffs between quick solutions and long-term methodology investments.
• Deeper cross-functional insight into how logic design, physical design, and DFT interact with STA methodology, and how to build flows that serve all of these stakeholders effectively.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

ABOUT THE JOB

Anduril is seeking a Payloads Integration Engineer to join the Maneuver Dominance team at our Costa Mesa HQ. The Maneuver Dominance (MD) Team at Anduril develops aerial robotic systems designed to operate in large coordinated teams in concert with ground maneuver forces. We leverage existing Anduril drone platforms like Ghost, Altius, or Roadrunner, in addition to bringing 3rd party platforms into Anduril’s Lattice ecosystem. We develop perception and autonomy algorithms to solve some of the hardest problems facing our customers.

As a Payload Integration Engineer, you will lead/enable mechanical design, analysis and integration of Anduril payloads into host platforms. This is a unique opportunity to grow your expertise in one of the most challenging and differing engineering domains; large autonomous air vehicles. You will work closely with the program leadership and a wide spectrum of cross-departments as part of a team focused on solving hard problems and changing the industry forever.

WHAT YOU’LL DO:

• Lead or support efforts performing integration, verification and/or validation of weapon systems on Anduril’s Unmanned Aircraft Systems platforms
• Develop program plans, estimates, and schedules
• Develop system/architecture designs, perform system level analysis, and generate requirements
• Troubleshoot conflicting design/development requirements
• Develop and present technical material for reviews and meetings
• Support lab, ground, and flight test events
• Develop/maintain Interface Control Documents, Software Requirement Specifications, Performance Specifications, presentations and review test plans/procedures
• Coordinate and interface with customers, contractors, and engineering groups assigned to projects
• Support ongoing operation of the weapons systems
• Provide support for proposals/white papers for future efforts or capabilities
• Provide direction to design and to technical staff

REQUIRED QUALIFICATIONS

• Bachelor’s degree, Master’s degree or PhD in engineering, computer science or a related technical discipline from an accredited institution and progressive engineering experience as follows; nine or more years of experience with a bachelor’s degree, seven or more years of experience with a master’s degree or five or more years with a PhD. May substitute equivalent engineering experience in lieu of education.
• Software programming or embedded systems experience (familiarity with C++, MATLAB, Python, PERL scripting, etc.)
• Familiarity with Air-to-Air weapons, MIL-STD-1553, and logical Interface Control Documents
• Experience integrating weapons, payloads, or avionics onto aircraft
• Experience with weapon or tactical datalinks
• Must be customer focused with the ability to formulate and implement plans to resolve technical engineering problems
• Ability to travel to support program and test events (up to 25%)
• Must be eligible to obtain and maintain a U.S. TS clearance

PREFERRED QUALIFICATIONS

• Experience in NX/Teamcenter
• Experience in Solidworks
• Experience designing mechanical parts and test equipment (CAD).
• Understanding of manufacturing methods (machining, sheet metal, composites, 3D printing, injection molding, composite lamination, etc)
• Experience developing subsystem layouts, performing architectural trade studies, and evaluating vendor performance data

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are looking for a dynamic, self-motivated, experienced engineer to architect and lead functional test coverage and test methodologies for NVMe SSDs.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Manage Enterprise server infrastructure, execute Customer Qual tests and debug failures
• Execution of enterprise SSD qualifications in customer systems.
• Communicate with team lead to understand qualification processes and test plans. Report status of qualifications and manage customer expectations.
• Coordinate  with internal team and customer test engineers to execute qual plans as per schedule. Teams will be both local and remote.
• Triage test failures and do a first level FA. Design and execute experiments to root cause defects and verify fixes in coordination with development teams.
• Provide feedback to functional test teams on issues seen in customer quals to better functional test coverage.
• Contribute in Triaging customer field issues and provide support for timely resolution of customer issues.
• Identify automation opportunities and help Automation team to continue to improve and add to the existing framework.

What You Bring

• BS in Computer Science or related technical field with 10+ years of system level testing or development of enterprise servers and enterprise storage systems experience or MS with 8+ years preferred.
• Experience with at least storage protocol like NVMe/PCIe, SAS, SATA, Fibre Channel
• Familiar with one of protocol analyzers like LeCroy, SerialTek, or Xgig System or device level performance analysis
• Proficiency in server operating systems especially system debug tools such as system logs.
• Knowledge of enterprise storage/server system technologies.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, Test execution and bug management tools.
• Scripting experience such as in Perl, Shell or Python
• Experience with SSD or HDD testing
• NetApp/HPE/Dell/IBM System Experience
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Layout to lead the development of next-generation SRAM solutions.

• Lead the development and execution of full-custom SRAM memory layout and sign-off verification flows (including compiler automation where applicable).
• Collaborate closely with circuit designers to translate schematics into efficient, high-performance physical layouts, own floor planning, placement, routing, and tape-out.
• Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power, yield, and manufacturability.
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification.
• Debug and resolve layout issues efficiently, including process-specific challenges in advanced nodes.
• Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques, design-rule compliance, and knowledge sharing.
• Develop automation scripts (Perl, Tcl, SKILL, etc.) to improve productivity.
• Address reliability concerns such as EM/IR drop, soft errors, and process variability. 
• Work cross-functionally with circuit, architecture, verification, and foundry/process teams to ensure first-pass silicon success and support product integration

What You Bring

• Bachelor's degree with 10+ years of experience in custom SRAM, memory compiler and IC physical layout design or master's degree 8+ years of experience strongly preferred. 
• 3 year’s experience in leadership of management role preferred.
• Extensive experience in SRAM layout design in advanced process nodes (e.g., 3nm, 2nm, or below).
• Demonstrated ability to lead, mentor, and manage a team of layout engineers. 
• Strong project management skills to handle complex schedules and cross-functional collaboration. 
• Strong proficiency with industry-standard EDA tools: 
• Candence Virtuoso (or Custom Compiler/IC Compiler) for custom/analog layout. 
• Physical verification tools for DRC/LVS/ERC flows. 
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification. 
• Experience with RC extraction, parasitic reduction, and memory-specific verification. 
• Scripting/automation skills (Perl, Tcl, SKILL, etc.) are highly valued. 
• Proven ability to drive layout quality, constraints, and closure while collaborating in global, cross -functional teams. 
• Prior work on high-speed, low-power SRAM in leading-edge nodes preferred. 
• Mentoring or technical leadership experience preferred. 
• Understanding of SRAM architecture, timing, power analysis, and yield optimization preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design  to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms.

This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design.

• Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm).
• Optimize SRAM designs for performance, power and area (PPA) and yield.
• Develop custom layouts and perform physical design verifications (e.g., DRC, LVS).
• Evaluate trade-offs between speed, power, and area to meet design targets.
• Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification.
• Work with product and test engineers to develop test plans and support silicon bring-up.
• Mentor Junior engineers, providing guidance on SRAM design techniques and best practices.
• Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance.
• Contribute to patents, technical papers, or industry conferences to advance SRAM technology.

What You Bring

• Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. 
•  Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes.
• Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.).
• Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths.
• Familiarity with timing analysis, power analysis, and design for manufacturability (DFM).
• Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc.
• Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks.
• Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams.
• Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond).
• Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling).
• Background in silicon debug and root-cause analysis.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change. 

#LI-SF1

Memory IO Lab is part of Samsung’s Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume. Memory IO’s vision is to provide memory interface technology solutions which can be adopted in DDR, LPDDR, GDDR, and more. We are an integral part of Samsung’s paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps.

Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy

What You'll Do

• Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES.
• Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary.
• Ownership of circuit and system specifications.
• Simulate designs with state-of-the-art CAD tools.
• Document designs and simulation results.

What You Bring

• BS 10+ years experience, MS 8+years of experience, PhD 5+ years experience in Electrical Engineering, Computer Science preferred. 
• 5+ years of experience working with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes.
• Prior experience in design of any one of the standard high speed interfaces like DDR, LPDDR, , GDDR, HBM I/O interface.
• Needs to be an expert in providing and understanding layout requirements of high speed circuits.
• Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design.
• Experience working closely with device/process team to define transistor specs
• The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
• Ability to troubleshoot and analyze complex problems.
• Excellent communication (written and verbal) and interpersonal skills
• Experience in high frequency clock distribution design, implementation, and analysis.
• Deep understanding of PPA (performance, power, and area) trade-offs.
• Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools
• Experience on silicon bring-up and automatic measurement using script
• Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Design and development of high performance firmware and software for cutting-edge enterprise SSD products.
• Debug, optimize, and validate SSD firmware on complex embedded multi-core architectures.
• Support customer qualification and adoption of SSD products.
• Participate in ground-breaking advanced SSD storage development and research projects.

What You Bring

• BS in Computer/Electrical Engineering or Computer Science with 3+ years of working experiences in silicon development or MS in Computer/Electrical Engineering or Computer Science with 1+ years of relevant working experience or PhD and 0+ years of relevant experience in storage firmware development is required.
• Strong programming experience and demonstrated proficiency in C/C++ for embedded systems, including development of algorithms, manipulation of complex data structures, and implementing highly optimized code, is required.
• Relevant hands on experience in embedded software or firmware development, including storage devices or other embedded platforms is required.
• Experience with one or more of the following storage related technologies: NVM Express, PCI Express, SAS, SCSI, NAND Flash/FTL, Fibre Channel, SATA, eMMC, or UFS is beneficial.
• Experience with ARM or equivalent embedded multi-core microprocessor architectures is required.
• Hands on experience with JTAG/ICE debuggers and protocol analyzers is required.
• Some scripting experience in one of Python/Perl/Javascript is desired.
• Familiarity and experience with modern agile software development methodologies and practices is preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Responsibilities and Description: 

The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. 

Required Qualifications: 

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Minimum 5 years of experience in digital physical design and verification.
• Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff.
• Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification.
• Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
• Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
• Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell.

Preferred Qualifications: 

• Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
• Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. 
• Experience in DFT (Design For Test) flows and ATPG.
• Experience in I/O design flow in multi-voltage power domain.
• Experience in building chip floor-plan including pin placement, partitions and power grid.
• Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints.
• Experience with build tools such as CMake and Bazel.
• Experience with code coverage and regression setup.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

The Solutions Engineer Team

We believe Solutions Engineers at Okta are involved in all stages of the customer’s digital transformation.  Solutions Engineers are experienced using presentations, email, phone and social media to connect with customers virtually and in-person. We are looking for great teammates who can build and deliver sales presentations and customized product demonstrations to help educate Okta’s Customers (everyone from developers to product managers to C-level executives) on best practices during their cloud security technology journey. We believe Okta’s Solutions Engineers empathize with Customers and quickly discern their true technical needs by asking detailed, clarifying questions while presenting solutions that specifically address those needs. Okta Solution Engineers have the rare combination of technical acumen and business insight; in a career where you can utilize both. As a Solutions Engineer at Okta, you will further develop each of these skills by advising a diverse set of customers on the value they will gain by using Okta’s Identity Platform.

The Solutions Engineer Opportunity

Reporting to the Senior Manager of Solutions Engineers Enterprise West, the Solutions Engineer is a functional business consultant,  with a passion for technology and the advanced ability to develop, position and demonstrate product-specific solutions during sales cycles, while achieving quarterly and annual sales goals for an assigned territory.

What you’ll be doing

• Work alongside the sales team as the technical and domain expert of a customer-facing sales team to help Customers understand the value of Okta’s solutions
• Understand customer challenges and business issues and provide product demonstrations to align our solutions with customer needs
• Answer product feature and technical questions from customers, partners and Okta colleagues
• Plan and deliver Proof Of Concepts for customers who have more complex use cases, collaborating with other Okta engineering teams as needed
• Provide feedback to product management about product enhancements that can address customer needs and provide additional value
• Share and learn best practices and re-usable assets with other Solutions Engineers to enhance the quality and efficiency of the team
• Stay current on competitive analysis and market differentiation
• Support marketing events including executive briefings, conferences, user groups, and trade shows
• At times, be asked to learn and lead your team as a subject matter expert (SME) with various product solutions and/or competitive knowledge

What you’ll bring to the role

• 8+ years pre-sales engineering experience and solution selling.
• A passion to serve the Customer, demonstrated in a customer-facing role, such as presales or professional services, but ideally in a pre-sales capacity.
• An ability to quickly communicate complex ideas around a technical topic, ideally on the fly, using a whiteboard.
• Deployed apps in cloud platforms: AWS, Azure, GCP, Vercel, etc.
• Experience with at least one standard network security protocol. (eg. OAuth, OAuth2, SAML, LDAP)
• Experience working with REST APIs and SDKs
• Hands-on experience in one or more of the following areas: web (JavaScript, HTML, frontend frameworks) development, backend (Java, C#, Node.js, Python) development, scripting (Bash, Powershell, Perl)
• An understanding of core security concerns within a typical application. (password hashing, SSL/TLS, encryption at rest, XSS, XSRF)
• You're an exceptional communicator, adept at simplifying complex technical concepts for diverse audiences, including highly skilled experts in large group settings.
• A confident and articulate presenter, you excel at sharing knowledge and insights with experienced technical professionals and large expert audiences.
• Demonstrated ability to effectively communicate complex technical information to highly skilled and experienced audiences, whether one-on-one or in large presentations.
• Territory management skills, including pipeline building and working with Sales counterparts to guide execution excellence
• Diagramming experience for user journey flows, complex architecture diagrams, etc.
• Typically 25% travel.
• Bachelor's degree in Engineering, Computer Science, MIS or a comparable field is preferred.

You ideally have

• Proven experience designing, implementing, and managing Privileged Access Management (PAM) solutions in enterprise environments.
• Deep understanding of the challenges and best practices associated with securing privileged accounts, including just-in-time (JIT) access, session recording, credential vaulting, and secrets management.
• Practical experience managing Windows Server, Active Directory, LDAP, and Federation services.
• Proficiency in UNIX/Linux, database security, network security, scripting, and DevOps practices preferred.
• Relevant experience with enterprise applications, security management, systems management, identity management, and/or policy management solutions, particularly in the areas of Identity and Privileged Access

P24432_3342674

LI -Remote

LI-LS

Position Description:

The Services PreSales Architect is a technical authority on both cloud and on-premises based IAM systems and is responsible for ensuring the successful design and implementation of Okta’s & Auth0’s industry leading cloud identity platform for our customers. Your main focus will be on driving the success of Okta's and Auth0's identity offerings. You will cultivate strong, trusted partnerships with customers, concentrating on their success and helping them achieve their business goals by promoting innovative and creative solutions. A key part of your role is to translate customer business needs and insights into a clear, actionable strategy that the delivery team can execute to help customers achieve tangible results and high business value from their initiatives. This is a key member of the Professional Services (PS) Pre-Sales team.

Job Duties and Responsibilities:

• Lead the pre-sales discovery of functional and technical requirements required to establish an Identity platform for our customers. 
• Lead Partners, Customers and Engagement Managers to document and mitigate technical risk identified during discovery.
• Create estimates to implement the proposed solution.
• Review services estimates to ensure project scope can be successfully delivered as outlined - technical risk is appropriately mitigated and timelines follow staffing guidelines.
• Lead and develop co-delivery proposals by identifying and engaging appropriate partners.
• Drive New Product Introduction (NPI) across PS by training Engagement Managers and developing associated assets such as scope modules, SKUs, success stories and enablement toolkits.

Minimum REQUIRED Knowledge, Skills, and Abilities:

• 10+ years of overall IT / software development experience, solution design and technical architecture experience
• 5+ years of Okta implementation experience
• 5+ years of consulting experience
• 5+ years driving application architecture design
• 5+ years of experience with (IAM) architectures
• Experience with employee and customer identity use cases: HR driven identity, Active Directory, SSO, SaaS application integrations.
• Experience with Identity Governance and Privileged Access Management use cases. 
• Demonstrated ability to work and interact with high-level customer executives and technical resources.
• Experience in leading discovery workshops to derive customer requirements and specifications.
• Experience in developing functional specifications and system design specifications for customer engagements.
• Strong knowledge of Security Architecture, Design and Operations, LDAP, Active Directory, SSO, SAML, OIDC, RBAC, OAuth, JSON, REST.
• Experience integrating with a multitude of On-Prem and SaaS based products.
• Exhibits confidence and a deep understanding of emerging industry practices when solving business problems.
• Identifies critical issues with ease.
• Effectively communicates technical information to non-technical audiences.
• Manages customer expectations effectively.
• Application design experience.
• Clear and Dynamic Communication.
• Ability to travel up to 50%

Highly Desirable Knowledge, Skills, and Abilities:

• Knowledge of software development security and cryptography.
• Familiarity with IAM solution providers.
• Experience with API Gateways, CASB, and Reverse Proxies (NGINX)
• Proficiency with various open-source software and development tools
• Proficiency in one or more of the following: .Net, Ruby, Java, Python or Perl

Education and Certification

• A Bachelor’s degree (or equivalent) in Computer Science, Information Technology or related discipline required.
• Okta Certified Technical Architect or a combination of Okta Certified Consultant and Okta Certified Developer is a plus.
• CISSP certification is a plus.
• TOGAF certification is a plus.

#LI-BF1

#LI-Hybrid

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ABOUT THE TEAM

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for an Electrical Test Design Engineer to join our rapidly growing team in Reston, Virginia. You will deliver test systems for Anduril’s electronic products. As a strong Test Automation Engineer you will need to have a proven track record of delivering turn key test solution for electronic components and systems and has a background in hardware, software, integration and sustainment. This person will work with the rest of the organization to identify gaps in test coverage and own the design and delivery of the hardware and software test solution. Anduril develops test systems used to ensure the quality and reliability of our aerial and ground based systems. The team works on air vehicles such as Roadrunner, Ghost, Anvil and Fury and develop complex manufacturing test solutions to our internal manufacturing team or contract manufacturers. We work closely and cross-functionally with the rest of our Product Engineering groups that include Electrical, Mechanical and Firmware Engineering to solve and improve our manufacturing process, product quality and reliability.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree or Master’s Degree in Electrical Engineer or equivalent.
• 5+ years of experience designing functional test equipment and PCBAs.
• Experience in Schematic Capture and PCBA layout.
• Working knowledge of scripting language to develop automation. Python, Matlab, PERL, Labview or SHELL.
• Understanding of peripherals and developing test and validation strategies.
• Experience with computer hardware communication bus protocols: USB, I2C, I2S, CSI, Ethernet, SPI, PCIe, HDMI, CAN, etc.
• Understanding of memory hierarchy and developing test and validation strategy.
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase.
• Collaborate with a cross-functional team to support product development from prototype to production.
• Currently possesses and is able to maintain an active U.S. Secret security clearance.

PREFERRED QUALIFICATIONS

• Master’s Degree in Electrical Engineering or equivalent.
• A detail-oriented individual who strives in an environment that values effective team collaboration.
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase.

ABOUT THE TEAM 

Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers’ most pressing national security requirements.

ABOUT THE JOB

We are looking for an Senior Electrical Test Design Engineer to join our rapidly growing team in Santa Ana, CA. You will deliver test systems for Anduril’s electronic products. As a strong Test Automation Engineer you will need to have a proven track record of delivering turn key test solution for electronic components and systems and has a background in hardware, software, integration and sustainment. This person will work with the rest of the organization to identify gaps in test coverage and own the design and delivery of the hardware and software test solution. Anduril develops test systems used to ensure the quality and reliability of our aerial and ground based systems. The team works on air vehicles such as Roadrunner, Ghost, Anvil and Fury and develop complex manufacturing test solutions to our internal manufacturing team or contract manufacturers. We work closely and cross-functionally with the rest of our Product Engineering groups that include Electrical, Mechanical and Firmware Engineering to solve and improve our manufacturing process, product quality and reliability.

REQUIRED QUALIFICATIONS

• Bachelor’s Degree or Master’s Degree in Electrical Engineer or equivalent
• 5+ years of experience designing functional test equipment and PCBAs
• Experience in Schematic Capture and PCBA layout
• Working knowledge of scripting language to develop automation. Python, Matlab, PERL, Labview or SHELL
• Understanding of peripherals and developing test and validation strategies
• Experience with computer hardware communication bus protocols: USB, I2C, I2S, CSI, Ethernet, SPI, PCIe, HDMI, CAN, etc
• Understanding of memory hierarchy and developing test and validation strategy
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase
• Collaborate with a cross-functional team to support product development from prototype to production
• Currently possesses and is able to maintain an active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Master’s Degree in Electrical Engineering or equivalent
• Proficiency in MS Word, Excel, PowerPoint and VISIO
• A detail-oriented individual who strives in an environment that values effective team collaboration
• Understanding of Product Release Cycle from prototype to production and key deliverables of each phase

Location

Palo Alto, CA

Job Description

Rhombus’ Data Engineers are instrumental in designing and implementing data engineering activities on topical, mission-driven projects that inform our national security agenda. They analyze, build, and maintain our organization’s data infrastructure and processing systems. 

Additionally, our Data Engineers perform various code development and query needs for integration with new and existing applications, dashboards and machine learning pipelines. Our Data Engineers work cross functionally with other departments to meet business needs. They utilize their skills at all stages of the analytics pipeline to create results that drive business values and customer success.

Responsibilities:

• Develop code using various programming and scripting languages to automate data ingestion and improve data management processes.
• Architect data repositories, stand up data platforms and develop data pipelines for ingestion, transformation, and aggregation.
• Review existing architecture, data strategy, and improve processes for data governance, data quality, and metadata management.
• Extract and analyze raw data from multiple data sources via APIs, SQL Stored Procedures, or Python scripts.
• Ability to develop scripts and programs for converting various types of data into usable formats and support project team to scale, monitor and operate data platforms.
• Collaborate with a multi-disciplinary team of analysts, data scientists, data engineers, developers, and data consumers in a fast-paced, agile environment.
• You’ll use your experience in analytical exploration and data examination while you manage the assessment, design, building, and maintenance of scalable platforms for clients.
• Communicate project status and results to various levels of leadership.

Qualifications:

• At minimum Bachelor’s degree in Data Analytics, Computer Science, Computer Engineering, Information Systems/Sciences, or other relevant area (or equivalent experience) and at least 3 years of professional experience, or a Master’s degree with strong academic project experience and one year of work experience.  
• Experience with 1 or more programming and scripting languages, with a strong focus on Python, Pandas and Numpy. Other languages include: Shell, PERL, Java, C/C++/C#, Scala, etc.
• Experience with 1 or more of the following relational, noSQL and/or file based storage (e.g. MYSQL, MongoDB, SQL Server, Oracle, Postgres, Hbase, DynamoDB, etc.)
• Experience building and maintaining ETL data pipelines
• Experience with software development life cycle including testing, documenting, delivery and support
• Working knowledge of AWS/cloud technologies
• Experience using query optimization as well as data modeling techniques.
• Familiarity with machine learning frameworks (such as TensorFlow, Scikit-Learn, etc.)

Personal Qualities:

• Bias for action: Rhombus seeks ‘doers’ who will get things done with accuracy, speed and at scale.
• Ability to contextualize data as it relates to Rhombus’ vision. We want someone who can understand the “why” and “so what”, and not just the “how”. Our Data Engineers help us transmit the enthusiasm we have around the data work to the individuals doing that work.
• Must have strong problem-solving skills and demonstrated excellent oral and written communication skills.
• We’re seeking folks with strong intellectual curiosity and creativity, with an ability and willingness to learn new skills and apply novel solutions to problems.
• Comfort in a fast-paced start-up environment is crucial, with the ability to consistently revise your approach in response to new information, and to be flexible and adaptive.

Salary Range

• The estimated base salary range for this position is $110,000 to $180,000/year

Benefits 

• Full medical, dental, vision coverage for employee and dependents 
• 401k matching program 
• PTO and Holidays 
• Bonus and other incentive programs
• Access to mental health program
• Access to Flexible Spending Accounts for Health Care, Dependent and Commuter

About Rhombus 

Rhombus Power Inc. (Rhombus) is a startup located in the heart of Silicon Valley at Stanford Research Park in Palo Alto.  We use cutting-edge cross-disciplinary approaches to solve pressing Big Data and Sensing problems in security, energy, and healthcare. Our advisory board includes two Nobel Laureates and a Draper Prize winner. 

Rhombus compensates, motivates, and develops employees, who are trusted, empowered, and involved. Employees have clear roles and expectations – and their roles are flexible enough to move at the speed of innovation in order to meet and exceed client expectations. We have a unique culture of global purpose, rooted in the innovation and progress of Silicon Valley. 

Rhombus knows that diversity is a condition for success. We are committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer. 

Join a team shaping the performance of next-gen CPUs and AI/ML chips. As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating with top engineers to optimize some of the most advanced silicon in the world. 

This role is onsite, based out of Austin, TX or Santa Clara, CA.

Who You Are

• Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS
• Solid understanding of logic design, VLSI, and transistor-level concepts
• Familiar with PnR tools, timing analysis, and power optimization techniques
• Comfortable scripting in Tcl, Perl, Shell, or Python

What We Need

• Support key physical design tasks—synthesis, floorplanning, PnR, clocking, timing closure
• Analyze and improve design PPA (Power, Performance, Area)
• Collaborate with front-end, PD, and architecture teams to influence early design decisions
• Explore and implement new flows, tools, or RTL experiments to optimize designs

What You Will Learn

• End-to-end physical design flow—from RTL handoff to final tapeout
• Deep dive into timing, power, EM/IR, and area trade-offs
• Industry-standard tools and techniques for modern chip development
• How top-tier silicon teams operate at scale

We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes.

This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in STA and passionate about enabling silicon to meet aggressive performance goals.
• Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies.
• A collaborative team player who works well across logic, DFT, and physical design boundaries.
• Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows.

What We Need

• 7+ years of industry experience and a proven record of successful tapeouts.
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
• Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
• Familiarity with SPICE modeling and worst-case corner analysis.

What You Will Learn

• How to close timing on Tenstorrent’s high-performance RISC-V CPUs and AI SoCs.
• Advanced STA methodologies tailored to modern sub-micron process technologies.
• How to collaborate with world-class engineers across RTL, DFT, and physical design teams.
• How to influence chip performance through timing methodology innovation and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is looking for a Staff Product Development Engineer - ATE Content Developer, who will be focused on core content development for high-performance AI/ML silicon. They  will be responsible for developing production test programs on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions, and implementing Streaming Scan Network (SSN) architectures for efficient test data delivery. High level challenges include reducing test cost while maintaining coverage targets, optimizing test time for chiplet and multi-die architectures, and enabling rapid yield learning through robust test methodologies. The work is done collaboratively with a group of highly experienced engineers across DFT, design, product, and manufacturing domains.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced semiconductor test engineer with 7 years and a BS/MS in EE/ECE/CE and a track record testing complex digital devices on advanced nodes.
• Hands-on with Advantest V93K and/or Teradyne UltraFlex+ platforms, comfortable owning production test programs end‑to‑end.
• Deeply familiar with DFT/ATPG flows and test architectures: scan chains, MBIST, compression, JTAG/IEEE 1149.1, and common fault models (stuck‑at, transition, path delay, cell‑aware).
• Proficient in C/C++ or Java, with strong scripting skills in Python, Perl, or TCL to automate flows, pattern handling, and data analysis.
• Skilled at debugging across ATE hardware, test programs, and silicon, and at using data to drive root‑cause analysis and yield improvement.

What We Need

• Develop and optimize production test programs on Advantest V93K using the SmarTest 8 environment, from bring‑up through high‑volume manufacturing.
• Translate ATPG patterns (STIL/WGL) into production‑ready test content, balancing test time, coverage, and cost for chiplet and multi‑die AI/ML devices.
• Implement and debug Streaming Scan Network (SSN) based content for high‑speed scan delivery, ensuring robust and scalable scan test infrastructure.
• Own test content for scan, BIST, and memory test structures, collaborating with DFT teams on pattern debug, fault diagnosis, and coverage improvement.
• Support silicon bring‑up and debug in the lab and at manufacturing sites, including correlation, corner characterization, and PVT studies.
• Build and maintain automation scripts and test methods that improve productivity, repeatability, and quality across the test lifecycle.
• Document test architectures, flows, and debug procedures so they can be scaled across products, sites, and engineering teams.

What You Will Learn

• How to test and scale cutting‑edge AI/ML silicon with chiplet and multi‑die architectures, including exposure to 2.5D/3D packaging and HBM integration.
• Deeper expertise in SSN architectures, high‑speed scan delivery, and next‑generation DFT/test methodologies for complex HPC/AI devices.
• How to drive end‑to‑end yield learning: from ATE data and STDF analytics through to design, DFT, and manufacturing process feedback.
• How a fast‑growing AI hardware startup coordinates DFT, design, product, and manufacturing to bring new silicon from first silicon to high‑volume production.
• Opportunities to influence test strategy, infrastructure, and automation roadmaps for future products and platforms as Tenstorrent’s portfolio scales.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with industry-standard tools (FusionCompiler, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
• Experience driving physical design requirements from early architecture through final signoff.

What You Will Learn

• How to implement cutting-edge AI accelerators, high-performance CPUs and the SOCs that host them on the most advanced process nodes.
• Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
• End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
• Direct impact on products that are redefining the landscape of AI and high-performance computing.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We’re looking for a Physical Design Engineer – EMIR to join our silicon team. In this role, you’ll lead EM and IR-drop simulations to ensure robust power delivery, signal integrity, and long-term reliability for high-performance ICs. You’ll work with RTL, physical design, and analysis teams to implement power grid strategies that optimize performance, power, and area (PPA), particularly at advanced nodes like 7nm and below. You’ll also support EMIR sign-off and waiver methodologies across the chip hierarchy.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A physical design specialist with deep experience in EMIR analysis and signoff.
• Comfortable navigating advanced technology nodes and power integrity challenges.
• Proactive and detail-oriented, with a passion for pushing performance and reliability boundaries.
• Collaborative and effective across teams working on RTL, physical design, packaging, and reliability.

What We Need

• 7+ years of experience in physical design or signoff, with a focus on EMIR.
• Hands-on with RedHawk, Voltus, or equivalent industry-standard EMIR tools.
  Strong understanding of IR-drop mitigation, EM compliance, and power grid design.
• Proficiency with layout extraction flows, RC modeling, and metal density checks.
• Experience working in advanced nodes (7nm, 5nm, 3nm), and with scripting languages like TCL, Python, Perl, or Shell.
• Knowledge of floorplanning, bump/RDL design, and sign-off flows (DRC/LVS, timing closure).

What You Will Learn

• How to architect and analyze robust power delivery for Tenstorrent’s RISC-V CPUs and AI chips.
• How to integrate EMIR signoff into fast-paced, high-performance chip design cycles.
• Best practices for hierarchical analysis and EMIR methodology across pre- and post-layout flows.
• Cross-functional collaboration for optimizing PPA while meeting stringent reliability goals.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a highly skilled and experienced Engineer to lead post-silicon power characterization and correlation activities for cutting-edge semiconductor products. In this role, you will be responsible for developing and executing detailed power measurement strategies on silicon, correlating results with pre-silicon models, and driving improvements across power architecture, design, and modeling methodologies. You will serve as a key technical leader, interfacing across design, architecture, validation, and systems teams to ensure silicon meets power and performance specifications under all operating conditions.

This role is hybrid, based out of Toronto, ON or Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• A Principal-level engineer with 8+ years in silicon power analysis and characterization, and a Master’s or PhD in EE, CE, or related field.
• Deep understanding of digital and mixed-signal power domains, including DVFS, leakage vs. dynamic power, and power gating.
• Highly proficient in lab-based power measurement using oscilloscopes, current probes, power analyzers, and SMUs, plus Python/Perl/MATLAB for automation and analytics.
• A strong debugger and collaborator, comfortable driving cross-functional investigations and clearly communicating technical findings.

What we need

• Own the post-silicon power measurement strategy end-to-end across operating modes, voltages, frequencies, and workloads.
• Build and maintain lab infrastructure, automated workflows, and data analysis pipelines for high-fidelity, repeatable power characterization.
• Correlate silicon power data to pre-silicon models (RTL, gate-level, sign-off), drive root-cause analysis, and refine power estimation methodologies with design and modeling teams.
• Characterize power across PVT corners and work with bring-up/validation teams to develop test content, debug power anomalies, and ensure products meet power and performance specs.

What you will learn

• How state-of-the-art SoCs behave in real silicon across diverse workloads, system configurations, and operating conditions.
• How to influence power architecture, RTL design, and modeling flows by feeding silicon insights directly back into early design phases.
• Best practices for building scalable, automated post-silicon power infrastructures that support multiple products and generations.
• Advanced correlation, margining, and variability analysis techniques that deepen your expertise in both SoC-level power and system-level behavior.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.

This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
• Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
• Strong problem solver who excels at debugging complex issues across design hierarchies.
• Collaborative team player who thrives in fast-paced, technically challenging environments.

Tenstorrent is seeking an experienced Silicon Validation Engineer to validate and qualify our cutting-edge die-to-die (D2D) subsystem, AI, and Processor IP testchips for the rapidly growing chiplet ecosystem. You'll develop hardware infrastructure for validation platforms, perform comprehensive electrical characterization, and support customer silicon bring-up. If you’re passionate about hands-on silicon testing and want to help usher in the chiplet era of semiconductor products, join us.

This role is on-site, based out of Santa Clara, CA; or Toronto, Canada. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on engineer with 5+ years of silicon test and characterization experience in lab environments.
• Expert with oscilloscopes, BERTs, and test equipment who can independently debug complex validation challenges.
• Self-driven problem solver with strong EE fundamentals in both digital and analog circuit design.
• Excellent communicator who collaborates effectively with design teams and tracks progress meticulously.

What We Need

• BS/MS in Electrical Engineering with 5+ years of hands-on silicon validation using Keysight/Tektronix equipment.
• Proven experience with high-speed measurements (Tx jitter, Rx JTOL) and test automation scripting (Python, Perl, LabVIEW).
• Strong understanding of datacomm circuits (amplifiers, PLLs, equalizers) and signal integrity concepts.
• Track record of independently running validation tests and driving issue resolution with design teams.

What You Will Learn

• State-of-the-art die-to-die chiplet validation methodologies for next-generation semiconductor architectures.
• How to build and evolve hardware infrastructure for advanced D2D validation and demo platforms.
• Customer-facing silicon bring-up techniques and product qualification best practices.
• The opportunity to shape validation standards in the emerging chiplet ecosystem at a fast-moving startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Visual Concepts, we believe great games are made by diverse and empowered teams with a shared passion for play. As one of the world’s top game development studios, we have shipped over 100 multi-sku titles to critical acclaim and commercial success. Our teams are independent and ambitious. Our studios in Novato, Irvine, Budapest, Shanghai, Austin, Boise, Seoul and Parksville, Canada are committed to artistry and ground breaking technology, offering top candidates the opportunity to learn and grow with some of the hardest working and most creative minds in the industry.

What We Need:

We’re seeking a Senior Engineer with a passion for server-side development to join the NBA 2K team! In this role, you’ll take ownership across a broad technical landscape- working in distributed systems, large-scale computing, and efficient databases to build high-performance backend services. Your work will play a key role in delivering world-class online experiences that power one of the most popular sports game franchises in the world. This role reports into Lead Director of Programming.

What You Will Do:

• Work in the backend architecture and services that support NBA 2K’s online features
• Design and optimize distributed systems to ensure scalability, reliability, and fault tolerance
• Build and maintain large-scale computing solutions that handle millions of concurrent players
• Develop efficient database structures and queries to support high-volume, real-time transactions
• Deliver high-performance backend services with a focus on low latency and stability
• Partner with engineering and design teams to enable seamless online gameplay experiences.

Who Will Be A Great Fit:

• 5+ years of professional software development experience, with a strong focus on backend and server-side systems
• Strong proficiency in C++ with a solid understanding of object-oriented programming principles
• Proficiency in one or more scripting languages such as Python, PHP, Perl, or Ruby, with a strong preference for Python
• Understanding of distributed and scalable systems
• Proven experience with multithreaded programming, driving efficiency and stability across large-scale, real-time environments
• Demonstrated ability to research, evaluate, and integrate emerging technologies and trends to enhance team capabilities, platform performance, and product innovation
• BS in Computer Science or equivalent experience in large-scale software development
• Experience developing secure transaction systems, including virtual currency and account-based features, a strong plus
• Skilled in database optimization, including connection management and query performance tuning
• Familiarity with online gaming architectures and service design for live, connected player experiences
• Working knowledge of SQL databases such as MySQL, Microsoft SQL Server, or similar systems
• Video game console development experience is highly beneficial
• Love for video games (not just ours!)

This is a fully remote role that may be based anywhere in the United States. Below are the expected salary and wage ranges for applicants based in locations where the pay transparency law is in effect: California: $130,700 - $174,300 per year. New York State (inclusive of New York City): $117,700 - $157,000 per year. Washington: $130,700 - $174,300 per year. New Jersey: $117,700 - $157,000 per year. British Columbia: $115,700 -$154,300 (CAD) per year. However, base pay offered is based on market location, and may vary further depending on individualized factors for job candidates, such as job-related knowledge, skills, experience, and other objective business considerations. Subject to those same considerations, the total compensation package for this position may also include other elements, including a bonus and/or equity awards and eligibility to participate in our 401(K) plan and Employee Stock Purchase Program. Regular, full-time employees are also eligible for a range of benefits at the Company, including: medical, dental, vision, and basic life insurance coverage; 14 paid holidays per calendar year; paid vacation time per calendar year (ranging from 15 to 25 days) or eligibility to participate in the Company’s discretionary time off program; up to 10 paid sick days per calendar year; paid parental and compassionate leave; wellbeing programs for mental health and other wellness support; family planning support through Maven; commuter benefits; and reimbursements for fitness-related expenses. Ontario only: The use of Artificial Intelligence is not being used to screen candidates. The position is for an existing vacancy.

To learn more about Visual Concepts and our studio locations, check out our website at www.vcentertainment.com

At Visual Concepts, we believe great games are made by diverse and empowered teams with a shared passion for play. As one of the world’s top game development studios, we have shipped over 100 multi-sku titles to critical acclaim and commercial success. Our teams are independent and ambitious. Our studios in Novato, Irvine, Budapest, Shanghai, Austin, Boise, Seoul and Parksville, Canada are committed to artistry and ground breaking technology, offering top candidates the opportunity to learn and grow with some of the hardest working and most creative minds in the industry.

What We Need:

We’re seeking a Senior Engineer with a passion for server-side development to join the NBA 2K team! In this role, you’ll take ownership across a broad technical landscape- working in distributed systems, large-scale computing, and efficient databases to build high-performance backend services. Your work will play a key role in delivering world-class online experiences that power one of the most popular sports game franchises in the world. This role reports into Lead Director of Programming.

What You Will Do:

• Work in the backend architecture and services that support NBA 2K’s online features
• Design and optimize distributed systems to ensure scalability, reliability, and fault tolerance
• Build and maintain large-scale computing solutions that handle millions of concurrent players
• Develop efficient database structures and queries to support high-volume, real-time transactions
• Deliver high-performance backend services with a focus on low latency and stability
• Partner with engineering and design teams to enable seamless online gameplay experiences.

Who Will Be A Great Fit:

• 5+ years of professional software development experience, with a strong focus on backend and server-side systems
• Strong proficiency in C++ with a solid understanding of object-oriented programming principles
• Proficiency in one or more scripting languages such as Python, PHP, Perl, or Ruby, with a strong preference for Python
• Understanding of distributed and scalable systems
• Proven experience with multithreaded programming, driving efficiency and stability across large-scale, real-time environments
• Demonstrated ability to research, evaluate, and integrate emerging technologies and trends to enhance team capabilities, platform performance, and product innovation
• BS in Computer Science or equivalent experience in large-scale software development
• Experience developing secure transaction systems, including virtual currency and account-based features, a strong plus
• Skilled in database optimization, including connection management and query performance tuning
• Familiarity with online gaming architectures and service design for live, connected player experiences
• Working knowledge of SQL databases such as MySQL, Microsoft SQL Server, or similar systems
• Video game console development experience is highly beneficial
• Love for video games (not just ours!)

This is a fully remote role that may be based anywhere in the United States. Below are the expected salary and wage ranges for applicants based in locations where the pay transparency law is in effect: California: $130,700 - $174,300 per year. New York State (inclusive of New York City): $117,700 - $157,000 per year. Washington: $130,700 - $174,300 per year. New Jersey: $117,700 - $157,000 per year. British Columbia: $115,700 -$154,300 (CAD) per year. However, base pay offered is based on market location, and may vary further depending on individualized factors for job candidates, such as job-related knowledge, skills, experience, and other objective business considerations. Subject to those same considerations, the total compensation package for this position may also include other elements, including a bonus and/or equity awards and eligibility to participate in our 401(K) plan and Employee Stock Purchase Program. Regular, full-time employees are also eligible for a range of benefits at the Company, including: medical, dental, vision, and basic life insurance coverage; 14 paid holidays per calendar year; paid vacation time per calendar year (ranging from 15 to 25 days) or eligibility to participate in the Company’s discretionary time off program; up to 10 paid sick days per calendar year; paid parental and compassionate leave; wellbeing programs for mental health and other wellness support; family planning support through Maven; commuter benefits; and reimbursements for fitness-related expenses. Ontario only: The use of Artificial Intelligence is not being used to screen candidates. The position is for an existing vacancy.

To learn more about Visual Concepts and our studio locations, check out our website at www.vcentertainment.com

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.

Key Responsibilities

• As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
• Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
• Architect and recommend flow improvements and enhance existing methodology for high performance design.
• Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
• Work with cross function teams to define requirements and specifications to achieve best PPA
• Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity
• Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• 2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Knowledge of agentic AI solutions is a plus.
• Experience working with EDA/IP vendors for both RTL and hard-macro integration.
• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.

Key Responsibilities

• Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
• Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
• Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
• Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• SystemVerilog/Verilog familiarity.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

About Epirus  

Epirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques which allow power-hungry systems to do more with less.

Job objective: This is an exciting role an innovative, high-growth defense technology company. The ideal candidate for the position is someone who has experience designing, verifying, and integrating state-of-the-art FPGA systems and embedded processing solutions for RF applications. As a Sr. FPGA Engineer, you will work closely with a talented, multi-disciplinary engineering team in a fast-paced environment to apply emerging technologies in innovative ways to rapidly produce new products.     

Duties  

• Design and verification of RTL modules for FPGA applications
• Ownership of entire FPGA designs from initial architecture trades through implementation, verification, and hardware bringup, including FPGA sizing estimation and IO planning.
• Lead initial testing and bring-up of custom FPGA circuit cards, validating functionality of on-board peripherals including memory interfaces, Ethernet controllers, and integrated sensors.
• Automating test environment (up to and including hardware-in-the-loop testing), lab equipment, and measurement devices
• Capturing design tradeoffs, state machine flow, system address maps, and block diagrams 

Required Qualifications  

• Bachelor’s degree in Electrical Engineering or a related field.
• 5+ years of experience in FPGA design, implementation, and testing
• Extensive experience implementing FPGA designs and embedded processing designs on embedded hardware
• Experience working with latest generation state-of-the-art Xilinx/Intel Parts and associated tool sets (Vivado, Quartus)
• Understanding of common digital communication protocols (SPI, I2C, UART)
• Development Experience of Integrated Embedded Applications (ARM, GPU)
• Experience with standard bus and streaming protocols, such as AXI and AXI-Stream
• Experience with Continuous Integration and Continuous Delivery processes
• Active Secret or Top Secret clearance, or ability to obtain one desired but not required.  

Desired Qualifications   

• Experience with design automation, scripting languages (TCL, Python, Perl, Matlab)
• Knowledge of Advanced Firmware Verification Testbench Development (UVM, System Verilog)
• Skilled with Advanced High-Speed Verilog/VHDL Designs including High Speed Memory Interfaces (DDR4, HBM) and High Speed SerDes IO and Protocols (100GE, JESD204B, Interlaken)
• Experience implementing Complex DSP Algorithms on FPGAs using tools such as Matlab, Simulink, HDL Coder to implement advanced communications or other designs in FPGA
• Experience collaborating with software engineering team in an SoC environment to develop designs that incorporate HDL combined with embedded Linux
• Good written and oral communication skills
• Collaborative; capable of working across all levels of the organization
• Organized; comfortable working in a fast-paced, ever-changing environment 

The Opportunity:

As an Executive Director and Head of Research Computational Biology within our Biology Function, the individual will oversee the scientific and strategic direction of systems biology research and preclinical computational biology initiatives. The individual will lead a team of computational biologists and bioinformaticians focused on acquisition, organization, and analysis of large multi-omics data sets, using both public and proprietary data sources, that will help inform treatment strategies and guide patient stratification for a growing pipeline of RAS(ON) and targeted oncology therapeutics. We are looking for an experienced leader with strong interpersonal skills and an ability to lead a strong and diverse computational biology team. Key aspects of the role include:

• Strategic vision and leadership: Develop and implement a long-term strategy for research systems biology and bioinformatic activities to support a growing pipeline of RAS(ON) and novel targeted inhibitors. Lead and supervise a team of experienced computational biologists and bioinformaticians to generate, organize, and interpret large data sets to inform therapeutic and combination strategies for patients with cancer.

• Cross-functional collaboration across research, translational, development and medical affairs groups: Work across functions to support advancement of programs from early discovery into clinical development using biological insights derived from computational approaches. Additionally, leverage clinical data from RVMD investigational agents to generate proprietary insights into RAS mutant tumor biology and RVMD RAS(ON) inhibitor mechanisms of action.

• Technical leadership and innovation: Lead a team analyzing large, high-dimensional datasets. Work with colleagues in Information Sciences and Information Systems to oversee data integration, analysis and visualization using cloud-based platforms (AWS, Azure, GCP). Direct the development and application of cutting-edge statistical analysis, AI/ML methods, generative AI models, and MLOps principles to elucidate findings and generate new insights related to biomarker discovery, drug target identification, and predictive modeling. Establish and implement modern workflow management systems (Snakemake, Nextflow) and reproducible research practices.

• External collaboration: Cultivate and manage academic and industry collaborations, including CRO partnerships. Represent the company at scientific conferences through presentations and thought leadership. Maintain an active publication record in high-impact, peer reviewed journals. Drive intellectual property strategy and patent filings related to computational discoveries.

Required Skills, Experience and Education:

• Education: A Ph.D. in systems biology, computational biology, bioinformatics, or a related biological or biomedical discipline.

• Experience: Minimum of 15+ years total experience with significant pharmaceutical/biotechnology industry and management experience.

• Scientific knowledge: Deep expertise in systems biology, computational biology, and bioinformatics, including proficiency with multi-omics data integration, modeling, and analysis. Experience with single-cell technologies, spatial transcriptomics, proteomics, and epigenomics. Oncology research experience preferred but not required.

• Technical: Advanced programming skills in R, Python, and at least one additional language (Perl, C/C++, Java). Proficiency with high-performance computing (HPC) and cloud platforms (AWS, Azure, or GCP). Knowledge of workflow management tools and version control systems. Understanding of MLOps principles, model deployment, and generative AI applications in drug discovery.

• Leadership and management: Demonstrated ability to lead, mentor, and inspire interdisciplinary teams while fostering a collaborative culture. Experience managing budgets and strategic planning at the department level. Proven track record of advancing research programs from discovery through development.

• Strategic thinking: Proven strategic thinker who can align research and drug development objectives and leverage innovative technologies effectively.

• Communication: Excellent communication and presentation skills for interacting with technical teams, senior leadership, and external partners. #LI-Hybrid  #LI-GL1

Aurora hires talented people with diverse backgrounds who are ready to help build a transportation ecosystem that will make our roads safer, get crucial goods where they need to go, and make mobility more efficient and accessible for all. We’re searching for a Staff, SI/PI Engineer.

In this role you will

• Lead Signal Integrity(SI), Power Integrity(PI)  implementation in advanced autonomous driving hardware systems, Sensors and hardnesses.
• Develop and implement simulation methodology for PCB, high speed channel and SOC to optimize SI/PI performance.
• Model complex 3D structures, such as PCB Connector and cables
• Extract and characterize high speed channel and compliance against industry standards
• Lead  high speed interfaces validation in lab with high end scope, VNA and spectrum analyzer

Required qualifications

• MS (PhD preferred) in Electrical Engineering or related Engineering Degree, with 6 + years of industry experience
• Experience with design and implementation of high speed electrical interfaces, such as PCIE Gen4/Gen5, high speed or automotive ethernet, DDR/LPDDR4/5, MIPI, HDMI, USB,etc
• Good EM  knowledge and proficient at SI/PI simulation tools, HFSS/SIwave, ADS or Cadence Sigrity.
• Solid understanding  transmission line theory,  S-parameter, signal processing and PCB material, Stackup and fabrication process.
• Strong lab skills and experience with VNA, real time Scope, spectrum analyzer and TDR, etc

Desirable qualifications

• Experienced with automotive hardware development
• Experience with mix signal design 
• Knowledge of scripting languages, such as Perl or Python

The base salary range for this position is $181,000 - $290,000 per year. Aurora’s pay ranges are determined by role, level, and location. Within the range, the successful candidate’s starting base pay will be determined based on factors including job-related skills, experience, qualifications, relevant education or training, and market conditions. These ranges may be modified in the future. The successful candidate will also be eligible for an annual bonus, equity compensation, and benefits.

#Mid-Senior 

PsiQuantum’s mission is to build the first useful quantum computers—machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. 

Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportation, materials, and other foundational industries. 

Our architecture and approach is based on silicon photonics. By leveraging the advanced semiconductor manufacturing industry—including partners like GlobalFoundries—we use the same high-volume processes that already produce billions of chips for telecom and consumer electronics. Photonics offers natural advantages for scale: photons don’t feel heat, are immune to electromagnetic interference, and integrate with existing cryogenic cooling and standard fiber-optic infrastructure. 

In 2024, PsiQuantum announced government-funded projects to support the build-out of our first utility-scale quantum computers in Brisbane, Australia, and Chicago, Illinois. These initiatives reflect a growing recognition that quantum computing will be strategically and economically defining—and that now is the time to scale. 

PsiQuantum also develops the algorithms and software needed to make these systems commercially valuable. Our application, software, and industry teams work directly with leading Fortune 500 companies—including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical—to prepare quantum solutions for real-world impact. 

Quantum computing is not an extension of classical computing. It represents a fundamental shift—and a path to mastering challenges that cannot be solved any other way. The potential is enormous, and we have a clear path to make it real. 

Come join us. 

Job Summary:

PsiQuantum is searching for a highly motivated, excellent CAD Engineer to join the Electronic-ICTeam. The successful candidate will have solid EE background with an in-depth understanding of circuits, layouts and VLSI design. We are looking for someone whit experience writing code to automate design processes and who enjoys working in groundbreaking process technologies! A strong background in Skill, Perl and Python are needed for this position. The job involves both development and support. 

Responsibilities:

• Maintain and support design databases, data integrity, and version control systems (e.g., IC Manage, Cliosoft, or similar).
• Install, configure, and support foundry PDKs.
• Develop automation using Perl, Python, and Cadence SKILL.
• Own and maintain the custom design environment used by custom schematic and mask designers.
• Support and maintain CAD tools used by IC designers including:
  • Virtuoso ADE, ADS various simulation environments
  • HSPICE and other simulation tools
  • Verilog / System Verilog flows
• Maintain and improve the cloud-based design environment, including compute infrastructure and user workflows.
• Work with CAD tool vendors to evaluate new tools, solve bugs, improve usability, etc.
• Develop infrastructure to support design work in new process technologies.
• Troubleshoot and resolve design environment issues to ensure high team productivity

Experience/Qualifications:

• B.S. (or equivalent experience) in Electrical Engineering with 5+ years of experience or M.S. in Electrical Engineering and 3+ years’ experience.
• A basic understanding of MOSFET device behavior, CMOS layout, and VLSI design.
• Excellent programming, debugging, and problem-solving skills.
• Experience with version control and design data management systems.
• Experience with Perl, Cadence SKILL, Python.
• Great communication skills.
• Passionate about providing excellent support for end-users.

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Overview of Role

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.

Location

• San Diego or San Jose, CA

Responsibilities

• Complete entire physical implementation of the block and chip level
• Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
• Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
• Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route
• Implement ECOs for timing closure
• Signal EM/Noise and Power IR/EM analysis and fix
• DRC/LVS/ERC/ANTENNA analysis and clean up
• Timing verification and signoff
• Physical verification and sign off

Minimum Qualifications

• Master’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experience
• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC
• Netlist (or RTL)-GDS physical implementation experience
• In depth knowledge of major EDA tools/design flows
• Strong Cadence experience/background
• Experience with TSMC N22 or below technology
• Experience in chip integration and signoff
• Experience in Perl/TCL language programming

Preferred Qualifications

• Strong experience in Low-power implementation methodology
• Strong experience in Advanced timing signoff methodology
• Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows
• Able to independently complete Netlist-GDS P&R, signoff task
• Proven record in multi-million gate design production tapeouts