Job Description

We are looking for a motivated SoC Test Intern to support validation and characterization of next-generation wireless SoC products. This role provides hands-on experience with RF and digital testing in a fast-paced semiconductor environment.

What You’ll Gain

• Hands-on experience with real silicon in production-like environments
• Exposure to end-to-end SoC development and validation flow
• Mentorship from experienced RF and digital engineers
• Opportunity to contribute to cutting-edge wireless technologies 

Key Responsibilities:

• Assist in bring-up, validation, and characterization of SoC silicon in lab environments
• Execute RF and/or digital test plans under guidance from senior engineers
• Support debugging and failure analysis at chip, board, and system levels
• Collect, analyze, and summarize test data; identify trends and anomalies
• Develop and maintain automated test scripts (e.g., Python, MATLAB)
• Work with cross-functional teams (design, DV, system, and product engineering) to resolve issues
• Document test procedures, results, and findings clearly
• Generate test reports, data summaries, and presentations for cross-functional teams.

Qualifications:

• Master Degree or bachelor’s in electrical engineering/computer engineering (or equivalent experience).
• Fundamental knowledge of digital circuits and/or RF concepts.
• Understanding of basic lab equipment (oscilloscope, signal generator, spectrum analyzer, etc.)
• Programming experience in Python, MATLAB, or similar
• Strong troubleshooting and problem-solving mindset.
• Good communication skills across cross-functional teams.
• Detail-oriented and disciplined with documentation.
• Team-oriented, adaptable to R&D and production environments.

Preferred Qualifications:

• Preferred Qualifications
• Exposure to RF systems (e.g., Wi-Fi, Bluetooth, cellular)
• Familiarity with SoC architecture and mixed-signal systems
• Experience with lab bring-up or hardware debugging (academic or project-based)
• Understanding of signal integrity, noise, and measurement techniques
• Experience with test automation frameworks

Overview of Role

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.

Location

• San Diego or San Jose, CA

Responsibilities

• Complete entire physical implementation of the block and chip level
• Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
• Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
• Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route
• Implement ECOs for timing closure
• Signal EM/Noise and Power IR/EM analysis and fix
• DRC/LVS/ERC/ANTENNA analysis and clean up
• Timing verification and signoff
• Physical verification and sign off

Minimum Qualifications

• Master’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experience
• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC
• Netlist (or RTL)-GDS physical implementation experience
• In depth knowledge of major EDA tools/design flows
• Strong Cadence experience/background
• Experience with TSMC N22 or below technology
• Experience in chip integration and signoff
• Experience in Perl/TCL language programming

Preferred Qualifications

• Strong experience in Low-power implementation methodology
• Strong experience in Advanced timing signoff methodology
• Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows
• Able to independently complete Netlist-GDS P&R, signoff task
• Proven record in multi-million gate design production tapeouts

Job Description

We are looking for a highly motivated, creative and experienced SoC Test Engineer to develop and implement test solutions for RF connectivity SoC (System-on-Chip) devices. This role involves developing advanced test solutions to ensure high performance and quality for Wi-Fi and Bluetooth SOC products. The ideal candidate will possess strong expertise in RF testing, test equipment, and semiconductor manufacturing processes.

Key Responsibilities:

• Design and implement RF test plans for Wi-Fi and Bluetooth devices and modules, and systems.
• Measure key RF parameters: gain, noise figure, S-parameters, ACPR, EVM, phase noise, harmonic distortion, etc.
• Characterize devices across temperature, voltage, and frequency ranges.
• Investigate test failures and differentiate between device, test setup, and measurement issues.
• Work closely with design engineers to feedback test results, helping optimize circuit/layout.
• Develop scalable test solution for high-volume manufacturing.
• Generate test reports, data summaries, and presentations for cross-functional teams.

Qualifications:

• Bachelor’s degree or higher in Electrical Engineering/Computer Engineering (or equivalent experience).
• Familiar with RFA fundamentals, measurement and instruments.
• Hands-on RFA testing, characterization, and debugging experience.
• Hands-on hardware schematic capture and layout design or test automation development using Python/C++ experience.
• Good understanding of firmware-based test methodologies.
• Strong troubleshooting and problem-solving mindset.
• Good communication skills across cross-functional teams.
• Detail-oriented and disciplined with documentation.
• Team-oriented, adaptable to R&D and production environments.

Preferred Qualifications:

• Experience with production test or ATE platforms (Teradyne, Advantest, Chroma).
• Familiar with wireless standards WiFi & Bluetooth.
• Understanding of statistical methods (Cp/Cpk, Gage R&R, etc).

We’re seeking a Senior Staff Firmware Engineer to join our collaborative team in developing robust and reliable firmware for next-generation IoT devices. In this role, you will develop firmware, device drivers and support system integration efforts for  ULP IoT solution, focusing on performance, reliability, and maintainability. Experience with TrustZone and Trusted Firmware-M (TF-M) is required.

Key Responsibilities:
•    Design and develop embedded firmware for IoT devices, targeting ARM Cortex-M micro controllers 
•    Experience with ARM TrustZone  and Trusted Firmware-M (TF-M) for secure firmware partitioning desired
•    Implement and optimize low-level drivers and integrate with hardware abstraction layers (HAL)
•    Develop secure boot and firmware update mechanisms, ensuring robust and reliable device operation
•    Collaborate with cross-functional teams (hardware, software, security) to define and implement firmware features
•    Debug, test, and validate firmware on target hardware, using J-Link, Oscilloscope and logic analyzers
•    Contribute to documentation of firmware architecture, design decisions, and implementation details
•    Security-focused system design, secure boot, and trusted execution environments
•    Memory partitioning and isolation in ARM Cortex-M micro controllers.
•    Secure OTA updates and lifecycle management for IoT devices

Requirements:

•    Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
•    10+ years of experience in embedded firmware development for IoT or embedded systems; 
•    Background or experience in security-related technologies (e.g., cryptography, secure coding practices, cybersecurity).   
•    Strong proficiency in C/C++ and low-level driver development.
•    Familiarity with working on SDK-based development
•    Familiarity with RTOS environments (e.g., FreeRTOS, Zephyr)
•    Hands-on experience with hardware bring-up and debugging tools
•    Excellent communication and collaboration skills
•    Strong problem-solving skills and attention to detail
•    Willingness to learn and contribute to a team-focused environment

As a Sr. Staff/ Principal Digital Design Engineer, you will be working with a team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. In addition to delivering high quality digital solutions in the context of the product architecture, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing, etc.

Key Responsibilities

• Contribute to/review SoC specifications and architectures
• Front to back digital design and verification – RTL through physical implementation
• Hands on technical leadership
• Support schedule and resource planning
• Help define and socialize digital/system design, implementation methodologies and test strategies and flows
• Debug designs and provide timely closure
• Work with System, Software, RF, Analog, and Test teams and provide necessary support

Job Requirements

• MS/PhD EE/CS preferred
• 10 or more years of experience digital SoC development required
• Experience bringing highly integrated mixed signal SoCs to commercial mass production
• Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces
• Deep RTL design knowledge (Verilog/VHDL) and SystemVerilog, checkers, and other design verification techniques
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Proven knowledge of synthesis, static timing, DFT and (Front to Back) F2B digital SoC design flow
• Experience with ATPG, fault grading, scan, BIST, DFT/DFM
• Proven knowledge of SystemVerilog assertions,
• Knowledge of languages such as C/C++, Perl, Tcl and Python
• Strong communication and presentation skills
• Good skills and interest in mentorship
• Ability to foresee issues and design in flexibility and workarounds for both known and unknown unknowns
• Expert in RTL design and implementation (architecture and micro-architecture)
• Deep knowledge of front-end tools and flow - Verilog simulators, linters, synthesis, static timing, clock trees, power simulation, floor plan development, and power supply implementation
• Deep knowledge of system modeling and verification using System Verilog or System C
• Proven knowledge in acquiring and integrating 3rd party IP
• High speed logic design (GHz+) , and high speed clock distribution experience.
• Understanding of mixed signal concepts

 Desirable Skills

• Experience with Cadence F2B design tools
• Experience with formal verification tools
• Able to work effectively with incomplete or changing requirements
• Good mentorship skills
• Strong knowledge of mixed signal concepts
• Focused, goal driven finisher