About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Staff UEFI Engineer to design, develop, and deploy UEFI-based firmware for Graphcore’s hyperscale AI server platforms. 

This role focuses on developing system firmware responsible for platform initialization, hardware configuration, and reliability features across large-scale data center deployments. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

The Firmware Engineering team develops the foundational firmware responsible for platform initialization, hardware configuration, and system reliability across Graphcore’s AI compute infrastructure. 

The team collaborates with silicon engineering, hardware design teams, BMC firmware teams, validation engineers, and platform architects to enable reliable server platform bring-up and operation. 

Responsibilities and Duties 

• Design, develop, and deploy UEFI-based firmware for hyperscale server platforms. 

• Collaborate with ODM partners throughout the design lifecycle from concept to mass production. 

• Integrate UEFI firmware into CI/CD pipelines enabling automated builds, regression testing, and static analysis. 

• Develop firmware functionality supporting platform initialization including CPU, memory, PCIe, and system interconnects. 

• Implement system firmware security features including root of trust, secure boot chains, and signed firmware updates. 

• Develop platform firmware features supporting server reliability, availability, and serviceability (RAS). 

• Build firmware interfaces supporting telemetry, firmware updates, and system management capabilities. 

• Collaborate with hardware, BMC, security, and validation teams to ensure full platform integration. 

• Debug and perform root cause analysis for firmware and hardware issues across lab and production environments. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 

• 10+ years of experience developing UEFI or BIOS firmware for server platforms. 

• Strong expertise with UEFI, TianoCore, and firmware architecture design. 

• Experience developing firmware solutions for hyperscale or cloud data center environments. 

• Strong programming skills in C/C++. 

• Deep understanding of DDR memory training, cache coherency protocols, and PCIe subsystems. 

• Strong knowledge of server platform architecture including power delivery, thermal management, sensors, and FRUs. 

• Experience implementing CI/CD pipelines for firmware development. 

• Experience debugging system firmware using logic analyzers, JTAG, GDB, and similar tools. 

Desirable 

• Experience developing UEFI firmware for ARM-based server platforms. 

• Experience with EDK II codebase development and upstream contribution. 

• Experience working with ODM/JDM partners on server platform development programs. 

• Experience delivering firmware for hyperscale cloud deployments and production environments. 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About the Role

As a Staff Embedded Software Engineer, you will spearhead the development of brand-new camera categories while driving the continued growth and reliability of our ever-expanding global fleet. This role is a high-impact technical leadership position requiring seamless collaboration across the entire stack—including Hardware, Product, Backend, and Frontend teams—to bring first-generation systems to life. Reporting directly to the Camera Firmware Manager, you will work full-time at our HQ in San Mateo to oversee the technical lifecycle of our newest hardware and ensure the operational excellence of a multi-million device, perpetually online IoT footprint.

What You'll Do

• Unlocking New Markets: Lead the end-to-end lifecycle of entirely new camera categories for untapped market segments. Collaborate directly with Hardware and Product teams during the initial co-design phase, to influence HW selection and feature scoping.
• Architectural Leadership: Own the firmware roadmap and drive the large-scale architectural changes required to support novel features across the entire stack—from low-level MCUs to Linux-based edge services.
• System-Wide Technical Depth: Engineer high-performance features across a diverse software landscape, spanning bare-metal MCU firmware, secure bootloaders, Linux kernel optimizations, and concurrent userspace services.
• Complex Problem Solving: Tackle the most "gnarly" system-level challenges, from non-deterministic race conditions and memory corruption to elusive hardware-software timing issues that only emerge at the scale of a million-device fleet.
• Navigate Multi-Dimensional Trade-offs: Systematically balance conflicting priorities—including hardware security hardening, peak performance, power efficiency, and deep fleet observability
• Cross-Functional Optimization: Partner with CV, Streaming, and Storage teams to architect vertically integrated features that push the boundaries of edge computing and real-time computer vision.
• Operational Excellence at Scale: Champion a reliability-first culture for a global fleet of 1.5 million perpetually online devices, designing the deployment and monitoring strategies that ensure 24/7 uptime.

What You Bring

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 10+ years of professional experience in systems software development for performance and resource-constrained environments.
• 5+ years of experience building software for Linux-based platforms.
• Demonstrated experience leading large-scale, cross-functional initiatives from concept to production. You have a history of aligning diverse engineering verticals to deliver complex systems on aggressive timelines.
• Proven experience leading initial board bring-up and hardware-software co-design for first-generation embedded devices.
• Hands-on experience with low-level protocols (SPI, I2C, UART, USB) and the ability to debug complex hardware-software interactions.
• Experience designing, implementing and debugging concurrent/multithreaded firmware services
• Strong understanding of modern operating systems, computer architecture, and trade-offs between compute, memory, and storage.
• Proficient in at least one systems programming language: C++ or Golang.
• Familiarity with Bash scripting and Python for tooling and automation.
• Bonus Qualification: Direct experience with Linux Kernel development, including writing or debugging drivers, managing device trees, or optimizing kernel-space performance.
• Bonus Qualification: Technical depth in MCU firmware and the boot stack, with a focus on RTOS, bare-metal development, or secure boot implementation.
• Excellent communication and documentation skills, with the ability to collaborate across engineering and product teams.

US Employee Benefits

Verkada is committed to fostering a workplace environment that prioritizes the holistic health and wellbeing of our employees and their families by offering comprehensive wellness perks, benefits, and resources. Our benefits and perks programs include, but are not limited to:

• Healthcare programs that can be tailored to meet the personal health and financial well-being needs - Premiums are 100% covered for the employee under at least one plan and 80% for family premiums under all plans
• Nationwide medical, vision and dental coverage
• Health Saving Account (HSA) with annual employer contributions and Flexible Spending Account (FSA) with tax saving options
• Expanded mental health support
• Paid parental leave policy & fertility benefits
• Time off to relax and recharge through our paid holidays, firmwide extended holidays, flexible PTO and personal sick time
• Professional development stipend
• Fertility Stipend
• Wellness/fitness benefits
• Healthy lunches provided daily
• Commuter benefits

Additional Information

• We do sponsor and take over sponsorship of employment visas for this role. If we make you an offer, we will make every reasonable effort to get you a visa.

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Energy/performance profiling and analysis
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing cost and performance under manufacturing process variation 
• Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 5+ years of experience in digital design
• Expertise in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Team Description:

The Robot Software Team builds software that enables scalable neurosurgery that allows safe implantation of the N1 device, ranging from core control, sensors and perception, autonomy, surgery analytics, and more. This role tightly integrates with the robot hardware team, surgery engineering team, as well as the BCI applications team which rely on us to deliver safe and effective implantation of the N1 device. 

Neuralink strives to be a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Description and Responsibilities:

As a Software Engineer Intern on the Robot Software Team, you will be responsible for writing software and making sure your code works on an actual surgical robot, not just simulation. Our robotics integrate actuated devices with microelectromechanical systems as well as novel surgical procedures. These applications place strong emphasis on high-precision, high-repeatability mechanical motion, as well as high reliability and fail-safe design. You will be expected to:

• Develop safety-critical software for the robot; you are responsible for contributing directly to surgery-ready software as an intern
• Take ownership of a project that is integral to robot functioning from design to implementation under the guidance of a robot software team member
• Jump on problems when they arise with a strong bias for action to support robot operation by non-software teams
• Work across different engineering disciplines; your software may involve interactions with the mechanical, electrical, biological, and neuroscience teams

Required Qualifications: 

• Evidence of exceptional ability in engineering or computer science
• Experience in writing performant applications in a system language like C, C++, and Rust
• Ability to work on mission-critical and safety-critical systems
• Strong bias for action and first principles thinking

Preferred Qualifications: 

• Hands-on experience with robotics or high-reliability systems
• Experience coding in Linux and debugging on Linux systems
• Experience in computer vision
• Experience in kinematics and motion planning
• Experience working on medical robots
• Experience working in a high-precision environment

Pay Transparency:

Based on California law, the following details are for California individuals only:

California Hourly Rate:

$35/hr USD

Team Description: 

The Infrastructure Team builds the foundation that enables the company to operate safely, robustly, and move at light-speed. We run a mixture of cloud-based and on-prem systems and have a user base spanning from highly technically proficient engineers to non-technical scientists and doctors; but all of them need solid systems, rugged networking, and bullet-proof software to do their jobs. This role will integrate tightly with teams across the company, and span all layers of the work environment stack, from deployment of physical hardware on the manufacturing line, to custom tooling to stream neural recordings from implants.

Tech Stack:

• Rust, Python
• Terraform
• Bazel and Nix
• Kubernetes
• GitLab CI
• AWS
• Ubuntu, Fedora

Focus:

• Developing the foundations for teams to build the software and systems required for record-breaking BCI experiences.
• Enhancing developer experience with robust tooling and build-system infrastructure.
• Building foundational infrastructure for HITL (hardware in the loop) testing across firmware, BCI, and robot teams.
• Ground-up infrastructure of on-premise solutions as well as cloud architecture.
• Foundational software engineering with a focus on serving internal software teams.

Qualifications: 

• Experience using IAC tools such as Terraform, Docker, Packer, Ansible, Cloud-Init, Kickstart.
• Working knowledge of compiled languages, ideally Rust, Go, or C/C++.
• Working knowledge of major cryptographic protocols and authentication schemes such as TLS, x509, 802.1x, U2F, SAML.
• Familiarity with modern Linux boot process, UEFI, TPM measured boot, Secure Boot, Systemd.
• Systems administration experience on Windows, macOS, and Linux.
• In-depth understanding of modern networking and common protocols.
• Ability to architect, build, and ship 0 to 1 infrastructure quickly and efficiently.

Team Description:

Join the Brain Interfaces Software Team and be part of a team of remarkable and driven engineers accelerating our pathway to human ready brain-computer interfaces. We are a small, but fast-moving team that collaborates with other exceptional teams of mechanical, electrical, and firmware engineers.

Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Description & Responsibilities:

We are looking for a versatile Software Engineer who is passionate about architecting and implementing elegant software solutions and thrives with autonomy to propose creative approaches to problems. You will be responsible for writing software to interact with Neuralink’s implant, as well as building systems for manufacturing and testing the device. Additionally, you will be expected to:

• Develop and improve Neuralink’s implant manufacturing line acceptance software and station
• Develop and improve Neuralink's implant design verification testing software
• Optimize and maintain Neuralink’s implant software build infrastructure
• Develop and improve Neuralink’s implant SDK

Required Qualifications:

• Fluent in Python and at least one system language including Rust, C++, and C (don’t get hung up on this—being an exceptional software engineer matters above all)
• Experience and proficiency with Linux/Unix systems
• Evidence of exceptional ability in engineering, mathematics, or computer science
• Solid understanding of engineering first principles
• Strong intuition for what matters in a production system vs. research-grade environments

Additional Requirements and Competencies:

• You find large challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver; you may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that what matters is delivering reliable solutions (Our ultimate aim is to help people; the “right” solution doesn’t always achieve that)
• You are mission-driven and goal-oriented in your approach to solving problems
• You feel a sense of urgency to get things done sooner rather than later—because there is so much we, as people, can contribute to the world and accomplish in this life, it’s a shame to waste time
• You are resourceful, flexible, and adaptable; no task is too big or too small

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Energy/performance profiling and analysis
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing cost and performance under manufacturing process variation 
• Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• Experience designing and implementing embedded software in C or Rust
• Expertise in SystemVerilog, C/C++, Python
• Experience designing and implementing  emulation models, transactors, and test environments to replicate hardware behavior
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Team Description:

At Neuralink, we're engineering the future of automated surgeries, focusing on the safe and effective implantation of our groundbreaking Neuralink implant. Our team — a cross-functional mix of roboticists, engineers from various disciplines, and medical professionals — collaborates on developing a surgical flow from first principles. In this critical role, you'll straddle the cutting-edge worlds of robotics, software, and neuroscience.

Job Description and Responsibilities:

This is a new and foundational role for our team that will allow you to create new embedded systems from scratch while challenging and refining the old. As a Firmware Engineer, your responsibilities will encompass:

• Developing and optimizing embedded software for robotic surgery applications
• Streamlining our codebase by refining and, when necessary, retiring legacy embedded software
• Rigorous testing and validation of software systems to meet the highest safety and reliability standards
• Participating in peer code reviews
• Writing drivers and applications to extend the functionality of our robotics
• Specifying hardware and software choices as we develop future hardware platforms
• Sharing your findings and progress with the team in a collaborative environment

Required Qualifications:

• Demonstrated track record of success in a science or engineering field, evidenced by outstanding projects, innovations, or advanced problem-solving
• Proven experience in software development, preferably with exposure to embedded systems

Preferred Qualifications:

Embedded Software Development:

• 2+ years of experience with embedded systems
• Proficient with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable/working knowledge of more advanced protocols such as PCIe, MIPI CSI/DSI, USB, and 802.3
• Proficient in at least one embedded language such as C, C++, or Rust
• Proficient with embedded toolchains and workflow
• Experience building and bringing-up MCUs or FPGAs
• Experience with embedded stacks for ARM cores
• Experience developing on embedded Linux platforms
• Experience with embedded Linux kernel configuration and device tree setup
• Experience with kernel driver development
• Experience with ARM bootloaders
• Experience coding drivers for actuators and sensors
• Experience with high speed data acquisition and processing

Electrical Engineering:

• Foundational understanding of MCU architectures and peripheral integration
• Solid knowledge in electrical engineering and DSP
• Ability to interpret electrical schematics and datasheets, along with proficiency in using lab equipment

Team Description:

The Surgery & Robotics Hardware Team is looking for Electrical Engineers who want to advance the future of healthcare solutions with technology. At Neuralink we recognize that increasing healthcare costs, lack of access, and insufficient numbers of neurosurgeons globally require new approaches to enable greater access to our devices. To address these challenges we design fully autonomous robotics systems, human assistive surgical tools, and design entire surgical suites in order to provide better experiences for our customers.

Our team works on our surgical robot system which aims to fully automate the implantation of the Neuralink implant. We design and integrate multi-axis robotic arms, perception systems including custom imaging hardware, optical coherence tomography tissue imaging, power electronics, and safety systems such as 3D spatial mapping/object avoidance sensors. Robotics is part of a larger system of tools we work on. For example, using pre-op MRI scans we generate patient anatomy data that we later use in surgery to register precise surgery site locations. 

In addition to research and development of modern surgical technology, we also are responsible for bringing these technologies to market. We perform full lifecycle testing for all devices we design and ultimately manufacture them for use in human surgeries. To date, our designs have served over 20 individuals, and in the coming years our designs will serve thousands of individuals who wish to use our implant technology.

Job Description and Responsibilities:

As an Electrical Engineer on the Surgery & Robot Hardware Team, you will be expected to design, verify, and oversee the transition to production of a variety of custom electronics systems.  This role offers substantial autonomy and the exciting opportunity to own creative decisions and execute on new, impactful projects such as robotics stage designs, motor drives and controls, custom camera designs, manufacturing automation, and the firmware that enables all of these devices.

Required Qualifications: 

• Bachelor’s degree in Electrical Engineering or a related field or equivalent experience
• Professional experience delivering on all phases of electronics design (requirements, part selection, schematic, layout, manufacturing, test)
• Demonstrated depth in at least one of the following:
  • Power electronics: experience designing custom power conversion, distribution, eFusing, and battery management systems in the low-to-medium (1W-2kW) range
  • FPGA hardware design for time sensitive systems such as image processing, high-speed data acquisition, or real time networking. Professional experience in FPGA selection, RTL development, digital signal processing theory and techniques, and hardware design to interface high speed physical layer devices via PCIe, MIPI, SLVS-ec, LVDS, etc
  • Manufacturing automation design: professional experience architecting and implementing manufacturing automation solutions for products that currently ship at the scale of 1000’s+
• Practical electronics design knowledge including designing for EMC, ESD, thermals and packaging

Preferred Qualifications: 

• A portfolio showcasing your hardware designs 
• Demonstrable experience developing electronics for safety critical systems such as medical devices, aerospace, automotive, or military
• Demonstrable experience shipping code in one of the following languages: C, C++, Python, or Rust
• Altium experience

Team Description:

We build the electrical systems that make high-bandwidth brain–computer interfaces possible. This includes neural signal acquisition and stimulation to wireless power delivery, embedded processing, and system integration—all within devices small enough to be implanted in the human body and efficient enough to operate under strict thermal and power constraints. Our work sits at the intersection of analog, RF, digital, and biological systems. Many problems in this space do not present clean abstractions or clear failure modes. Success often depends on careful measurement, iteration, and engineering judgment across multiple interacting systems.

Job Description and Responsibilities:

We are looking for an experienced, hands-on electrical engineer for implant electronics board design, integration with our custom chips, testing, and quality control. You will have the opportunity to contribute to advanced projects, not only work on incremental changes, and be an integral member of a small, fast-moving team. You will be working on all phases of board design (part selection, schematic design, layout, and bring-up) as well as collaborating closely with chip designers, firmware engineers, mechanical engineers, and microfabrication experts for system integration.

• Utilize electrical engineering fundamentals and best system design practices to build on your ability to deliver high-performant, reliable, and manufacturable extremely size-constraint systems
• Gain understanding of all phases of system and board design, from system definition to part selection, schematic design, layout, bring up, and design verification
• Contribute to R&D investigations and experiments to demonstrate feasibility of new technology for the implant and the charger
• Gain experience working cross functionally to ensure successful systems integration
• Contribute to system improvements that decrease latency and increase battery life, reliability, and safety
• Develop ability to design and deploy systems for implant-charger hardware in the loop testing, and manufacturing line quality control

Required Qualifications: 

• Strong EE fundamentals
• Experience designing PCBs for low power and size constrained applications
• Experience with PCB CAD tools (Altium, Eagle, KiCad, Allegro)
• Experience with sensors, power management, and signal/power integrity
• Comfortable with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable with lab equipment (oscilloscope, VNA, etc.)
• Basic C and Python programming skills

Preferred Qualifications:

• Experience with firmware development for embedded systems (C/C++)
• Experience with wireless systems (BLE, WIFI, Zigbee)
• Experience building and bringing-up MCUs or FPGA
• Proficiency with ME CAD tools (Solidworks, AutoCAD)
• Experience with analog circuit design

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

ICON is looking for a Senior Robotics Software Engineer to join our Software team in Austin, TX. As a Senior Robotics Software Engineer, you will help develop and maintain robotic control software for all of ICON’s robotic systems. You will be responsible for developing high-performance C++ software to drive complex arm motions, integrating real-time sensor data, and ensuring reliable motion planning. This role is based at ICON’s Austin, TX headquarters, and will report to the Director of Embedded Software Engineering.

RESPONSIBILITIES

• Design, develop, and optimize high-performance C++ software for controlling and coordinating large-scale robotic arms.
• Develop robust motion planning and trajectory generation algorithms to safely navigate industrial arms through complex workspaces.
• Implement real-time sensor fusion and state estimation algorithms (using sensors like IMUs, LiDAR, etc.) to improve arm localization and end-effector precision.
• Program robotic arm motions in coordination with other systems.
• Develop and maintain simulated environments and automated test frameworks to support continuous integration and system verification.
• Lead system integration and validation efforts across hardware and software.
• Participate in architecture decisions for controls and electrical systems, including component selection and standardization.
• Participate in design & code reviews to maintain consistency and high-quality output.

MINIMUM QUALIFICATIONS

• Masters Degree or higher in Software Engineering, Robotics, Mechanical Engineering, or a related field.
• 5+ years of professional experience in robotics software development.
• Expert-level proficiency in modern C++ (17 or newer) and Python within a professional robotics software development environment.
• Deep foundational understanding of robotic arm kinematics (forward and inverse), multi-body dynamics, and motion planning.
• Hands-on experience with robotic platforms, sensors, actuators, localization, perception, and control systems.
• Practical experience designing and optimizing sensor fusion and state estimation algorithms (e.g., Kalman Filters).
• Strong knowledge of autonomy algorithms, robotics frameworks (such as ROS), and simulation environments.

PREFERRED QUALIFICATIONS

• Experience programming industrial robots in high-level languages.
• Experience in formal control theory and linear algebra.
• A general understanding of how to manage redundant kinematic chains or stabilize dynamic systems.
• Proven track record of delivering products to end users and production environments.
• Familiarity with hardware design, prototyping, and manufacturing processes.
• Excellent problem-solving skills and a strong analytical mindset to identify issues, propose innovative solutions, and make data-driven decisions.
• Ability to earn trust, maintain positive and professional relationships, and contribute to a culture of performance.

Senior Post Silicon Validation Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Principal Security Firmware Engineer to design, implement, and validate security mechanisms within embedded firmware and low-level system software supporting Graphcore’s AI compute platforms. 

This role focuses on protecting hardware platforms through secure firmware architecture, trusted boot mechanisms, and secure firmware update frameworks while working closely with hardware, firmware, and security architecture teams. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

The Firmware and Platform Security team is responsible for securing Graphcore’s AI infrastructure platforms across firmware and hardware interface layers. 

The team collaborates with silicon engineering, hardware design teams, firmware developers, and security architects to implement trusted boot chains, secure firmware update mechanisms, and hardware-rooted security capabilities. 

Responsibilities and Duties 

• Design and implement secure firmware architectures for embedded and hardware systems. 

• Develop secure boot, firmware authentication, hardware root of trust, and secure firmware update mechanisms. 

• Define threat models and security requirements for firmware components. 

• Develop and maintain secure embedded firmware using languages such as C, C++, and Rust. 

• Integrate cryptographic libraries and hardware security modules (HSM/TPM). 

• Implement protections against firmware tampering, side-channel attacks, fault injection, and reverse engineering. 

• Perform firmware security assessments, code reviews, and vulnerability analysis. 

• Conduct penetration testing, fuzz testing, and other security validation techniques. 

• Collaborate with hardware teams to integrate chip-level security features. 

• Ensure firmware implementations align with industry standards such as NIST, FIPS, and Secure Development Lifecycle practices. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related discipline. 

• 5–10+ years of experience in embedded systems or firmware development. 

• Strong programming experience in C and C++. 

• Deep understanding of secure boot architectures and trusted boot chains. 

• Strong knowledge of cryptographic protocols and secure firmware design practices. 

• Experience working with embedded operating systems such as FreeRTOS, Zephyr, or Linux. 

• Experience implementing secure firmware update systems and cryptographic key management. 

Desirable 

• Programming experience in Rust. 

• Experience integrating TPM or hardware security modules (HSM). 

• Experience with static analysis and security tools such as Coverity. 

• Knowledge of secure silicon architectures and trusted execution environments. 

• Experience contributing to open-source firmware security projects. 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Senior Embedded SW/FW Engineer (Bringup)

Salary $156,500 - $211,700 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Principal Hardware Diagnostics Engineer to design and develop diagnostics software used to monitor hardware health and diagnose system-level issues across Graphcore’s AI infrastructure platforms. 

This role focuses on building diagnostics agents, tools, and analytics frameworks that enable engineers and automation systems to identify, isolate, and resolve hardware issues across blade-level servers and rack-scale clusters. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.    

The Systems Engineering and Platform Validation team ensures Graphcore’s AI compute platforms are reliable, diagnosable, and operationally robust at scale. 

The team collaborates with hardware engineering, firmware, cloud infrastructure, and automation teams to develop tools and frameworks that monitor system health, detect hardware failures, and accelerate root-cause analysis across AI clusters. 

Responsibilities and Duties 

• Design and develop automated hardware diagnostics solutions for blade-level servers and rack-scale AI systems. 

• Architect and implement diagnostic agents, monitoring tools, and analytics frameworks to track hardware telemetry. 

• Collaborate with hardware teams to integrate low-level diagnostic modules into monitoring systems. 

• Develop diagnostics tools capable of detecting hardware health conditions and isolating failures. 

• Create diagnostic modules used for internal validation and production data center operations. 

• Provide detailed hardware fault information to system engineers to accelerate troubleshooting. 

• Define remediation workflows and insights for hardware fault scenarios across nodes and clusters. 

• Collaborate with firmware, networking, and cloud platform teams to integrate diagnostics across the system stack. 

Candidate Profile 

Essential 

• Bachelor’s, Master’s, or PhD in Computer Science, Computer Engineering, or related discipline. 

• Strong software engineering experience in Python, C++, or C#. 

• Experience developing diagnostics or monitoring systems for hardware platforms. 

• Experience working with distributed systems or cloud infrastructure. 

• Strong knowledge of Linux environments and system-level diagnostics tools. 

• Experience collaborating with CM/ODM partners on manufacturing diagnostics and fault isolation. 

• Strong analytical and debugging skills. 

• Excellent communication and collaboration abilities. 

Desirable 

• Experience working with AI hardware platforms or accelerator-based computing systems. 

• Familiarity with hyperscale data center infrastructure. 

• Experience building cluster-level monitoring or diagnostics systems. 

• Experience interacting with internal or external customers during diagnostics solution development. 

Principal Embedded SW/FW Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Principal Post Silicon Validation Engineer (Bringup)

Salary $241,100 - $326,100 + Phantom Equity + Benefits 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing.  

We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. 

The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team.  

Responsibilities and Duties 

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon 
• Deploy silicon validation tests on first silicon and debugging them 
• Develop automated test framework and regression test suites in Python to optimize validation efficiency 
• Collaborate closely with engineers from many other disciplines on a variety of topics 
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies 
• Analyse test results, identify and debug failures/defects 
• Contribute to shared test and validation infrastructure 
• Provide feedback to architects 

Essential skills: 

• Strong experience in Bare metal / embedded C/C++ 
• Good knowledge of digital ASICs
• Be highly motivated, a self starter, and a team player  
• Ability to work across teams and programming languages to find root causes of deep and complex issues 
• Experience of the post-silicon validation process applied in digital ASIC environments 
• Python, Linux 
• Excellent communication skills and the ability to collaborate with others to solve problems
• Excellent problem-solving, analytical & diagnostic skills 

  Desirable skills: 

• Driver level experience with one or more of the following is highly desirable: 
  • PCIe 
  • Ethernet 
  • Memory technologies (LPDDR, DDR, HBM, …) 
  • Other peripherals such as I2C, I3C, SPI, … 
• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable
• Experience of Arm CPUs, System IP and debug tools
• Experience of AMBA protocols
• Understanding of ML applications and their workloads
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Position Overview

The Corporate Security Manager is responsible for architecting, implementing, and governing enterprise-wide physical security programs across aerospace manufacturing, R&D, test, and corporate facilities. This role places strong emphasis on facility protection, ingress and egress controls, and intellectual property (IP) safeguarding within export-controlled and program-restricted environments.

The position ensures the safety and security of employees, visitors, flight hardware, prototypes, tooling, and controlled programs by integrating physical security operations with EH&S, Legal, Compliance, IT Security, Facilities, and Program Leadership. The Corporate Security Manager must balance life safety, regulatory compliance, operational continuity, and high-value IP protection within a fast-paced aerospace manufacturing environment.

Key Responsibilities

Enterprise Physical Security Management

• Design, implement, and maintain comprehensive physical security programs across manufacturing, R&D, integration, test, and corporate facilities.
• Conduct recurring risk assessments, threat analyses, and vulnerability audits, with focus on restricted manufacturing areas, program-controlled spaces, and IP-dense environments.
• Oversee security infrastructure including CCTV, electronic access control systems, intrusion detection, alarms, perimeter security, lighting, and monitoring platforms.
• Establish and enforce enterprise security standards, policies, and procedures aligned with aerospace regulatory, contractual, and customer requirements.

Ingress and Egress Control Governance

• Architect and manage secure ingress and egress processes controlling movement of employees, contractors, visitors, customers, and vendors.
• Administer enterprise access control programs including badging, biometrics, key control, escorting procedures, and visitor management systems.
• Define zoning strategies, tiered access levels, and program-specific restrictions for sensitive manufacturing, R&D, and test environments.
• Partner with Facilities, IT, HR, and Program Management to ensure access provisioning and deprovisioning align with onboarding, transfers, program assignments, and terminations.
• Lead emergency evacuation and shelter-in-place planning, ensuring life safety measures do not compromise controlled or classified assets.

Intellectual Property (IP) Protection

• Implement physical safeguards protecting export-controlled technologies, proprietary designs, trade secrets, prototypes, tooling, and flight hardware.
• Establish secure handling, storage, transport, and destruction protocols for sensitive materials and physical media.
• Coordinate with Legal, Compliance, IT Security, and Program Leadership to ensure physical controls align with ITAR/EAR and contractual obligations.
• Monitor, investigate, and remediate suspected IP compromise or unauthorized physical access incidents.
• Support internal and external audits related to controlled areas, asset accountability, and IP protection frameworks.

Incident Response and Investigations

• Lead security incident response for events impacting personnel safety, restricted facilities, export-controlled programs, prototypes, and hardware in coordination with EH&S leadership.
• Operate within a joint Security–EH&S incident command structure prioritizing life safety, IP containment, regulatory compliance, and program continuity.
• Conduct investigations related to unauthorized access, IP compromise, injuries within secure areas, or environmental incidents impacting restricted spaces.
• Integrate EH&S root cause analysis methodologies with security investigations to address systemic breakdowns in both life safety and physical controls.
• Ensure evidence preservation, chain of custody, and documentation meet regulatory, contractual, and customer standards.
• Lead containment actions including access lockdowns, badge audits, material accountability checks, and secure storage verification.
• Co-author corrective and preventive actions (CAPA) addressing facility hardening, zoning improvements, access control enhancements, and secure material handling processes.
• Plan and execute joint drills and tabletop exercises addressing aerospace-specific threat scenarios.

Vendor and Stakeholder Management

• Manage third-party security providers, guard services, and security technology vendors.
• Establish performance standards, KPIs, service level agreements, and cost controls.
• Serve as primary liaison to EH&S, Facilities, HR, Legal, IT, Engineering, Program Management, and executive leadership on physical security matters.

Training and Security Culture

• Develop and deliver security and IP protection training for employees, contractors, and visitors.
• Promote a culture of shared accountability for security, compliance, and asset protection.
• Advise leadership on emerging threats, insider risk trends, and evolving physical security best practices impacting aerospace operations.

Qualifications

Education

• Bachelor’s degree in Security Management, Criminal Justice, Risk Management, Engineering, or related field; or equivalent professional experience.
• Military or government physical security credentials acceptable in lieu of formal education.

Experience

• 7+ years of progressive experience in enterprise physical security, preferably within aerospace, defense, or advanced manufacturing environments.
• Demonstrated experience securing IP-dense, export-controlled, or restricted manufacturing facilities.
• Strong operational knowledge of electronic access control systems, CCTV platforms, investigations, and incident command frameworks.
• Proven track record leading cross-functional investigations and managing high-impact security incidents.

Preferred Qualifications

• CPP (Certified Protection Professional), PSP (Physical Security Professional), or equivalent certification.
• Direct experience supporting ITAR/EAR or classified programs.
• Familiarity with EH&S management systems, CAPA methodologies, and regulatory audit processes.
• Experience operating in multi-site or program-centric aerospace organizations.

Soft Skills

• Executive-level communication and stakeholder management capability.
• High integrity and discretion handling sensitive and export-controlled information.
• Analytical and risk-based decision-making approach.
• Strong crisis leadership and structured incident management capability.
• Ability to influence cross-functional teams in high-consequence environments.

Technology Stack

• Enterprise Access Control Systems (e.g., badge systems, biometric platforms)
• CCTV and video management systems
• Incident reporting and investigation platforms
• Visitor management systems
• Microsoft Office Suite
• Security analytics and monitoring tools

Physical Requirements

• Ability to walk manufacturing floors, R&D labs, and test facilities regularly.
• Ability to respond onsite to incidents during non-standard hours as required.
• Capability to participate in emergency drills and facility assessments.

Our team has built a high-performance RISC-V CPU from the ground up and is committed to building the best AI platform possible. We value collaboration, curiosity, and a passion for solving hard technical problems across software, compute, networking, and semiconductors.

As part of the Platform Architecture team, the Data Movement Architecture Intern will help shape the performance of our next-generation AI, CPU, and heterogeneous platforms. You’ll work closely with architects and software engineers to design, model, and analyze how data movement subsystems impact system behavior and application-level performance.

This role is remote, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO.

Who You Are

• A highly motivated student who enjoys deep technical exploration and performance analysis.
• Curious about how data moves across compute, memory, and networking in complex AI/CPU systems.
• Comfortable interpreting simulation data and evaluating architecture tradeoffs.
• A strong communicator who collaborates well across multidisciplinary teams.

What We Need

• Pursuing an MS/PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• Solid understanding of computer architecture topics such as interconnects, memory hierarchies, and caching.
• Proficiency in C/C++ and scripting languages like Python or Shell.
• Experience with RTL design and simulation.

What You Will Learn

• Designing and optimizing data movement subsystems including CPU controllers, DMA engines, and accelerators.
• Conducting performance exploration for CPU controller features and system-level data movement.
• Performing PPA analysis and developing reduced data movement kernels for modeling and emulation.
• Working with software, RTL, and architecture teams to understand real-world AI/CPU workloads.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is hybrid based in Austin, TX

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

Who You Are

What We Need

• Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
• Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
• Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
• Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.

What You Will Learn

• How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
• Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
• Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
• Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.

Join the team building high-performance RISC-V CPU cores at Tenstorrent. As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and performance engineers to ensure our designs meet real-world performance demands. This is a hands-on role that spans simulation, emulation, debug, and analysis.

This role is on-site, full-time (40 hours/week) in Santa Clara, CA or Austin, TX.

Who You Are

• Pursuing a BS, MS, or PhD in EE, ECE, CE, or CS with strong academic performance.
• Experienced with assembly, C/C++, and scripting in Python or Perl.
• Familiar with CPU architecture and performance concepts, including pipelines, memory systems, and branch prediction.
• Comfortable working through complex debug problems in a methodical, detail-oriented way.
  
  

What We Need

• Interns who can create performance test plans and write stimulus to stress real CPU scenarios.
• Engineers who can run simulations and emulations to validate performance metrics.
• Contributors who can bring up and debug workloads ranging from open-source benchmarks to industry-standard suites.
• Teammates who can investigate mismatches between RTL and performance models and help root-cause bottlenecks.
  
  

What You Will Learn

• How CPU performance is measured, validated, and optimized before silicon.
• How performance models, RTL implementations, and debug tools come together in a real chip development workflow.
• Techniques for balancing tradeoffs in microarchitecture to hit performance targets.
• What it takes to collaborate across architecture, design, and post-silicon teams in a high-performance CPU project.

In this role, you will learn Functional verification of high-performance CPUs going into industry leading AI/ML architecture. You will be mentored by and work alongside a group of highly experienced engineers across various domains of the AI chip.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

This is for our Fall 2026 Semester

• Leadership to drive compiler development across multiple layers of the stack, including custom dialects, transformation passes, and runtime integration.
• Alignment with hardware, software, and ML teams to ensure the compiler supports realistic performance and deployment needs.
• Technical ownership of roadmap priorities, planning, and mentorship for a high-performing engineering team.
• Insight to identify bottlenecks, debug performance issues, and improve developer workflows across the stack.

• Experience building compilers or similar systems, with strong fluency in C++ and Python.
• Strong knoweledge of MLIR, LLVM, or related infrastructure, with hands-on work in dialect design or optimization passes.
• You have a strong understanding of modern AI frameworks like PyTorch, TensorFlow, or JAX, including how models are transformed and executed.
• A background in working across teams to ship reliable, scalable tools in fast-paced engineering environments.

• How to build compiler infrastructure that supports both training and inference at scale across custom chip architectures.
• New approaches for human-in-the-loop optimization using TT-Explorer and other internal tooling.
• Best practices for evolving MLIR dialects like TTIR, TTNN, and TTKernel to support next-generation AI workloads.
• How Tenstorrent delivers open, performant, and developer-friendly AI infrastructure that scales with industry demands.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

• Experienced compiler engineer with deep knowledge of GCC and LLVM internals, comfortable optimizing for custom hardware targets.
• Strong C/C++ developer with a solid grasp of algorithms, data structures, and performance analysis.
• Collaborative and analytical, able to work across hardware and software domains to deliver efficient, high-performance toolchains.
• Passionate about enabling breakthrough compute architectures through compiler innovation and software-hardware co-design.

• Design, develop, and optimize GCC and/or LLVM compilers for Tenstorrent’s custom RISC-V hardware and AI vector engines.
• Contribute to the co-design of Tenstorrent’s hardware and software stack to maximize performance and programmability.
• Benchmark, analyze, and tune performance of core applications across RISC-V and AI software environments.
• Collaborate with ML engineers to identify and implement compiler support for emerging AI workloads and frameworks.

• How compiler design directly impacts the performance and efficiency of next-generation RISC-V and AI architectures.
• Advanced techniques in hardware-software co-optimization and compiler-driven performance tuning.
• Integration of custom compilers with leading ML frameworks and runtime environments.
• The end-to-end toolchain flow that enables Tenstorrent’s scalable, high-performance AI compute systems.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking an IP Software Generalist to develop and optimize the software stack for our IP customers, enabling them to successfully integrate our AI and RISC-V hardware into their systems. In this role, you will build and support a versatile range of software components, from bare-metal firmware and drivers to system-level tools and APIs, ensuring a seamless customer experience. You will partner closely with hardware engineering, IP delivery, customer support, and product teams to deliver robust, scalable, and high-performance software solutions tailored to diverse customer architectures. Success in this role requires adaptability, strong system-level debugging skills, and the ability to bridge the gap between complex hardware IP and user-friendly software integration.

This role is hybrid, based out of Austin, TX; Toronto, ON; or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced software engineer with a strong foundation in C/C++, system programming, and low-level software design.
• Background in firmware, device drivers, embedded systems, or hardware-software co-design.
• Skilled at navigating and troubleshooting complex, full-stack software environments.
• Known for working effectively with cross-functional teams and external customers to resolve integration challenges.
• Able to balance versatile, hands-on coding with high-level architectural problem-solving.

What We Need

• Develop, optimize, and maintain software components for Tenstorrent’s hardware IP offerings.
• Define and build reference software, SDKs, and toolchains to streamline the customer integration process.
• Diagnose and resolve complex hardware/software interaction issues during customer bring-up and deployment.
• Drive the creation of high-quality documentation, test suites, and integration guides for IP software deliverables.
• Partner cross-functionally with hardware and architecture teams to ensure future IP designs are optimized for software usability.

What You Will Learn

• How to build and deploy robust software stacks for cutting-edge AI and RISC-V silicon IP.
• How to drive successful hardware-software integration across a diverse range of customer environments and architectures.
• Firsthand exposure to the complete silicon IP lifecycle, from initial bring-up to massive-scale customer deployment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are seeking a junior-to-mid level SOC Emulation Engineer to support our hardware emulation infrastructure and internal chip design teams. This role focuses on integrating vendor and custom hardware transactors, developing Python-based test frameworks, and providing technical support to emulation users across multiple chip projects.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Background in Electrical/Computer Engineering or Computer Science with 1-3 years of experience in chip design, verification, or emulation.
• Proficient in Python for automation and test development, with a working knowledge of C++ and the ability to navigate SystemVerilog RTL.
• Skilled at using modern AI tools (Claude, ChatGPT, Copilot) to accelerate code generation, debugging, and documentation analysis.
• Energetic about supporting diverse teams, from high-level software to low-level firmware, to solve complex runtime and build issues.

What We Need

• Ability to integrate vendor and custom transactors into RTL testbenches while handling clock domain and tri-state resolution.
• Experience building Python APIs (using pybind11) and maintaining CMake-based compilation flows for emulation libraries.
• Solid understanding of standard chip interfaces, bus protocols, and hardware synchronization (resets/clocking).
• A commitment to triaging and debugging the full stack, spanning from Python tests and C++ bindings down to hardware.

What You Will Learn

• Deepening your expertise with world-class platforms like Synopsys Zebu for massive-scale silicon validation.
• Gaining a holistic view of chip development by bridging the gap between hardware RTL and software drivers.
• Building and optimizing large-scale emulation build and run tooling for high-performance engineering teams.
• Refining your ability to gather requirements and facilitate communication between hardware designers and software engineers.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Software Engineer on the Metal Runtime team at Tenstorrent, you’ll work on the low-level software that powers our AI accelerators. You’ll design fast, efficient runtime systems that run close to the hardware, and define the host and device APIs that expose these capabilities to the rest of the software stack. We believe APIs are a core part of systems design: they encode hardware semantics, performance tradeoffs, and concurrency models, and they live longer than any single implementation.

If you enjoy pushing performance, working close to the metal, and designing abstractions that make complex systems usable without sacrificing control, this is your kind of role.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong coder in C or C++, and enjoy working close to hardware.
• Comfortable thinking in terms of threads, processors, and memory movement.
• Care deeply about API design, abstraction boundaries, and developer experience in low-level systems.
• Experienced (or interested in) designing libraries or interfaces used by other engineers.
• Think about long-term maintainability, usability, and clarity when designing systems.
• Curious about how runtimes and bare-metal software come together to power AI.
• Collaborative by nature and enjoy solving tough problems with smart people.

What We Need

• Design and evolve host and device APIs that expose Metal runtime capabilities clearly and efficiently.
• Translate low-level hardware behavior into intuitive, high-performance abstractions.
• Collaborate closely with runtime, kernel, and higher-level software teams to align API design with real-world usage.
• Ensure APIs balance performance, control, safety, and ease of use.
• Contribute to runtime implementation where needed to support API design and integration.
• Debug, analyze, and improve usability and performance across the software stack.

Nice to have:

• Experience designing or evolving non-trivial C++ APIs used by other engineers.
• Familiarity with APIs for accelerator systems (e.g., CUDA, SYCL, Vulkan, or similar).

What You Will Learn

• How to design APIs and abstractions for cutting-edge AI hardware.
• How to balance performance, control, and usability in low-level system design.
• How to translate hardware capabilities into clean, developer-friendly interfaces.
• Best practices for building maintainable, high-performance systems software.
• How software and hardware co-evolve in a fast-paced AI startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As a Software Engineer on the Metal Runtime team at Tenstorrent, you’ll work on the low-level software that powers our AI accelerators. You’ll build and optimize high-performance runtime systems that execute directly on the hardware, focusing on scheduling, memory movement, and efficient execution across massively parallel processors. We believe runtime systems are a core part of performance: they determine how hardware resources are utilized, how data flows through the system, and how efficiently workloads are executed at scale.

If you enjoy pushing performance, working close to the metal, and solving complex systems challenges at the hardware/software boundary, this is your kind of role.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong coder in C or C++, and love working close to hardware.
• Comfortable thinking in terms of threads, processors, and memory movement, and experienced writing fast, parallel code across multiple processors.
• Enjoy optimizing execution, scheduling, and memory systems for performance at scale.
• Comfortable debugging at the hardware/software boundary and reasoning about system behavior end-to-end.
• Curious about how runtimes and bare-metal software come together to power AI.
• Collaborative by nature and enjoy solving tough problems with smart people.

What We Need

• Build and optimize the Metal runtime that executes directly on our AI accelerators.
• Develop bare-metal systems that manage compute execution, scheduling, and resource utilization.
• Optimize memory movement and data flow across massively parallel hardware.
• Work closely with hardware teams to maximize performance and efficiency of our architecture.
• Debug, analyze, and tune runtime behavior across complex, distributed systems.

What You Will Learn

• How to design high-performance runtime systems for cutting-edge AI hardware.
• How execution, scheduling, and memory systems interact at scale.
• How to make custom ASICs and co-processors work efficiently across the chip.
• Best practices for debugging complex, performance-critical software.
• How software and hardware co-evolve in a fast-paced AI startup.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As our TT-Distributed Software Engineer, you will develop and optimize distributed software systems that power the most efficient and highest-performing AI and HPC clusters. In this role, you'll work on distributed programming across multiple nodes, utilizing systems programming, inter-node communication, and Tenstorrent’s scalable architectures to advance the state-of-the-art distributed inference and training infrastructure.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong C or C++ engineer with solid foundations in systems programming, operating systems, and distributed systems principles.
• Enthusiastic about distributed computing, including IPC, socket programming, and cluster resource coordination.
• Comfortable reasoning about scalability, fault tolerance, and performance across multi-node environments.
• Curious and first-principles thinker who challenges conventional approaches to distributed system design.
• Motivated to grow into a deep technical expert in large-scale distributed AI infrastructure.

What We Need

• Architect, implement, and optimize distributed software systems that coordinate computation and communication across clusters of AI accelerators and CPUs.
• Design and build distributed APIs enabling data-parallel and tensor-parallel AI workloads.
• Leverage MPI-based technologies and related frameworks to scale programming models across multiple hosts and compute nodes.
• Develop robust systems using IPC, inter-node sockets, and distributed communication primitives to ensure reliability and high performance.
• Build and maintain testing, debugging, profiling, and monitoring tools for large-scale distributed workloads and collaborate with model and systems teams on cluster bring-up.

What You Will Learn

• How large-scale distributed inference and training systems are architected across thousands of accelerators.
• Advanced techniques in collective communication, synchronization, and parallel workload distribution.
• The performance characteristics of Tenstorrent hardware in multi-node cluster environments.
• How distributed programming models integrate with compilers, runtimes, and AI frameworks.
• The real-world challenges of deploying, debugging, and scaling next-generation AI clusters.

Tenstorrent is building the world’s fastest, most efficient AI compute clusters. TT-Fabric is the high-performance nervous system of this platform: the low-level networking layer that lets thousands of RISC-V and AI processors snap together into a single, massively parallel distributed supercomputer. If you love squeezing nanoseconds out of hot paths, designing protocols that move data at absurd scale, and turning messy hardware constraints into elegant distributed systems, this is an opportunity to shape the fabric that future AI models will run on

This role is hybrid based out of Santa Clara, CA; Austin, TX; or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who We Are

• Strong systems engineer with deep C or C++ experience and comfort working in low-level or bare-metal environments.
• Passionate about hardware-software interaction, performance tuning, and eliminating inefficiencies at the protocol level.
• Curious about networking, synchronization, and communication across large clusters.
• Comfortable reasoning from first principles and challenging industry conventions.
• Motivated by building infrastructure that directly impacts large-scale AI training and inference performance.

What We Need

• Architect, implement, and maintain TT-Fabric, our low-level networking library powering distributed inference and training.
• Design scalable communication systems capable of coordinating thousands of AI processors efficiently and reliably.
• Optimize protocols, synchronization strategies, and data movement to extract maximum hardware performance.
• Integrate TT-Fabric APIs into the broader programming model in collaboration with AI and hardware teams.
• Help define the long-term architecture of Tenstorrent’s distributed systems stack.

What You Will Learn

• How large-scale AI clusters are architected from the networking layer up.
• The performance characteristics of custom AI hardware and RISC-V processors at scale.
• Advanced synchronization, collective communication, and interconnect optimization techniques.
• How distributed systems design decisions directly influence model throughput and training efficiency.
• How hardware and networking software co-evolve in next-generation AI infrastructure.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Our diverse team of technologists have developed a high performance RISC-V-based CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Great at identifying problems and developing solutions.
• Enjoys building tools and optimizing work flows.
• Skilled in C++ and Python, with an understanding of industry-standard tools for compilation, simulation and emulation.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre-silicon environments.
• Knowledgeable in architecture and microarchitecture of high-performance CPU cores.
• Ideal candidates would possess experience in infrastructure, methodology and performance verification.

What We Need

• Join a team driving improvements in CPU microarchitecture, verify performance and correlate with the RTL.
• Enhance design environment, tools, and methodologies to improve development efficiency.
• Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.
• Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through performance convergence and validation.
• Hands-on experience optimizing CPU designs in both pre-silicon and post-silicon phases.
• Integration of open-source and industry-standard tools to improve flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Join the team revolutionizing AI computing at Tenstorrent. You'll work on TT-Forge, our MLIR-based compiler that enables developers to run AI on all configurations of Tenstorrent hardware using an open-source, performant, and general-purpose compiler. You will be at the forefront of the AI hardware revolution, building compiler technologies that redefine what’s possible.

 This role is hybrid, and can be based out of Santa Clara, CA; Austin, TX; or Toronto; ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A passionate software engineer eager to work on compiler technologies and the challenges of AI hardware, whether from compilers, systems, or broader software backgrounds.
• Fluent in C++ and Python, with experience building complex systems that bridge high-level frameworks to low-level execution.
• Excited by compiler optimization and machine learning, with experience in PyTorch, JAX, TensorFlow, or deep systems programming.
• A collaborative problem-solver who thrives in open-source and enjoys working closely with hardware and software engineers.

What We Need

• A drive to solve novel challenges in AI compilation, from optimizing computational graphs to creating custom dialects and transformation passes.
• Experience or strong interest in MLIR and how modular compiler frameworks connect AI models to advanced hardware.
• Motivation to build technology that impacts the future of AI, knowing your work will enable the next wave of breakthroughs.

What You Will Learn

• How to build open-source compiler frameworks supporting diverse AI models and workloads, including training and multi-chip scaling.
• Deep expertise in compiler technologies including custom MLIR dialects (TTIR, TTNN, TTKernel) and transformation passes.
• New methods for human-in-the-loop compiler optimization using TT-Explorer, making advanced tuning tools usable by all developers.
• How compiler technology powers Tenstorrent’s mission to deliver affordable, open-source AI computing in a highly competitive space.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, we build open, state of art compute for real workloads and real developers.

You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You bring 8+ years in CPU verification or closely related digital design.
• You know high‑performance out‑of‑order CPU microarchitecture in depth.
• You work comfortably with RTL, waveforms, logs, and complex debug scenarios.
• You communicate clearly across design, DV, emulation, and post‑silicon teams.

What We Need 

• Plan and drive functional verification for CPU core features and microarchitectural scenarios.
• Develop UVM, assembly, and C/C++ stimulus for ISA and microarchitectural coverage.
• Develop/debug C++ functional models of RISC-V extensions and un-core components such as APIC and IOMMU.
• Debug simulation and emulation regressions using waveforms, logs, and RTL understanding.
• Build and refine coverage models to track and close architectural and microarchitectural coverage.
• Improve core, cluster, and chip‑level testbenches and debug infrastructure.
• Support design bring‑up across simulation, emulation, and post‑silicon environments.
• Collaborate with design, test, and validation to deliver robust CPU cores and clusters.

What You Will Learn 

• How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.
• Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.
• Ways to scale coverage, debug, and infrastructure across multiple CPU programs.
• How open hardware and software fit into Tenstorrent’s broader compute roadmap.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is looking for a Staff Product Development Engineer - ATE Content Developer, who will be focused on core content development for high-performance AI/ML silicon. They  will be responsible for developing production test programs on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions, and implementing Streaming Scan Network (SSN) architectures for efficient test data delivery. High level challenges include reducing test cost while maintaining coverage targets, optimizing test time for chiplet and multi-die architectures, and enabling rapid yield learning through robust test methodologies. The work is done collaboratively with a group of highly experienced engineers across DFT, design, product, and manufacturing domains.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced semiconductor test engineer with 7 years and a BS/MS in EE/ECE/CE and a track record testing complex digital devices on advanced nodes.
• Hands-on with Advantest V93K and/or Teradyne UltraFlex+ platforms, comfortable owning production test programs end‑to‑end.
• Deeply familiar with DFT/ATPG flows and test architectures: scan chains, MBIST, compression, JTAG/IEEE 1149.1, and common fault models (stuck‑at, transition, path delay, cell‑aware).
• Proficient in C/C++ or Java, with strong scripting skills in Python, Perl, or TCL to automate flows, pattern handling, and data analysis.
• Skilled at debugging across ATE hardware, test programs, and silicon, and at using data to drive root‑cause analysis and yield improvement.

What We Need

• Develop and optimize production test programs on Advantest V93K using the SmarTest 8 environment, from bring‑up through high‑volume manufacturing.
• Translate ATPG patterns (STIL/WGL) into production‑ready test content, balancing test time, coverage, and cost for chiplet and multi‑die AI/ML devices.
• Implement and debug Streaming Scan Network (SSN) based content for high‑speed scan delivery, ensuring robust and scalable scan test infrastructure.
• Own test content for scan, BIST, and memory test structures, collaborating with DFT teams on pattern debug, fault diagnosis, and coverage improvement.
• Support silicon bring‑up and debug in the lab and at manufacturing sites, including correlation, corner characterization, and PVT studies.
• Build and maintain automation scripts and test methods that improve productivity, repeatability, and quality across the test lifecycle.
• Document test architectures, flows, and debug procedures so they can be scaled across products, sites, and engineering teams.

What You Will Learn

• How to test and scale cutting‑edge AI/ML silicon with chiplet and multi‑die architectures, including exposure to 2.5D/3D packaging and HBM integration.
• Deeper expertise in SSN architectures, high‑speed scan delivery, and next‑generation DFT/test methodologies for complex HPC/AI devices.
• How to drive end‑to‑end yield learning: from ATE data and STDF analytics through to design, DFT, and manufacturing process feedback.
• How a fast‑growing AI hardware startup coordinates DFT, design, product, and manufacturing to bring new silicon from first silicon to high‑volume production.
• Opportunities to influence test strategy, infrastructure, and automation roadmaps for future products and platforms as Tenstorrent’s portfolio scales.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Scope

Ambiq is seeking an Edge AI Firmware Engineer to build and optimize the embedded software stack that powers real-time, battery-powered on-device AI. You will develop Ambiq’s AI runtimes, performance-critical operator libraries, and profiling/debug tooling that enable customers to deploy efficient inference on resource-constrained devices.

While the cloud has been the default home for AI, the next frontier is distributing intelligence everywhere—directly onto real-world devices. Edge AI enables real-time responsiveness, stronger privacy, lower bandwidth cost, and reliable operation even without connectivity. This role helps accelerate the shift to on-device intelligence across a rapidly growing ecosystem of health and fitness wearables, smart glasses, industrial IoT, and always-on sensors.

You’ll work closely with platform, silicon, and applied ML teams—and directly with customers—to ensure our software extracts maximum performance and energy efficiency from Ambiq hardware while remaining easy to integrate into production embedded toolchains.

Responsibilities 

• Develop and support Ambiq’s embedded AI runtimes (HeliaRT—our fork/extension of TensorFlow Lite for Microcontrollers—and HeliaAOT) with focus on portability, correctness, performance, and usability.
• Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components.
• Build and maintain on-device profiling and performance analysis tools, including converting PMU counters into actionable insights.
• Drive improvements in latency, memory footprint, and energy (e.g., joules/inference) through compute/bandwidth and memory-hierarchy analysis.
• Develop benchmark harnesses, microbenchmarks, and regression tests to ensure numerical correctness and prevent performance regressions.
• Enable seamless customer integration across embedded environments and toolchains (bare metal, FreeRTOS, Zephyr).
• Improve memory planning/runtime efficiency and manage upstream/fork health; publish and maintain customer-facing assets (docs, guides, examples, benchmarks).

Qualifications 

• BS in Electrical/Computer Engineering, Computer Science, or related field + 5+ years relevant experience (or equivalent practical experience). MS is a plus, especially in embedded systems, compilers, computer architecture, or ML systems.
• Strong experience designing, developing, and testing embedded software in C/C++.
• Strong debugging discipline with an emphasis on correctness, reproducibility, and performance regression prevention.
• Solid understanding of compute, memory, and bandwidth/cache effects on deterministic latency and energy efficiency in constrained systems.
• Ability to interpret hardware/software documentation (datasheets, reference manuals; schematics a plus).
• Proficiency with Git (or equivalent version control).
• Efficient use of AI-assisted development tools to improve productivity while maintaining engineering rigor.
• Experience with embedded development workflows: Arm toolchains, GDB + J-Link/SEGGER-class probes, and CMake/Make build systems.

Nice to have:

• Python for profiling/analysis tooling, automation, and developer utilities.
• Rust experience.
• Familiarity with TensorFlow Lite for Microcontrollers (or similar embedded inference runtimes).
• Experience optimizing for embedded acceleration targets (e.g., DSP, vector extensions, NPU).
• Familiarity with CMSIS-NN, CMSIS-DSP, and/or Vela (or similar).
• Working knowledge of quantized inference (e.g., int8, per-channel) and embedded debugging implications.
• Packaging/integration (e.g., CMSIS-Pack/CPM.cmake) and/or lab measurement experience (power/debug with basic bench tools).

Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

Austin is home to Optiver’s hardware research, development, and manufacturing group. We build some of the world’s most competitive trading hardware—high-speed, high-density systems that push the limits of performance, reliability, and manufacturability.

We’re growing fast and looking for a Manufacturing Test Engineer focused on PCBA test development and deployment. You’ll own board-level test solutions from early prototypes through volume production—building fixtures, developing automation, driving debug, and partnering closely with contract manufacturers and our internal EE/ME/FPGA/firmware teams.

We’re a small, highly technical team, and this role comes with real autonomy: you’ll have the runway to improve how we do test, raise the bar on factory readiness, and build scalable processes as our hardware footprint grows.

Who we are

Optiver is a tech-driven trading firm and leading global market maker. As one of the oldest market making institutions, we are a trusted partner of 70+ exchanges across the globe. Our mission is to constantly improve the market by injecting liquidity, providing accurate pricing, increasing transparency and acting as a stabilizing force no matter the market conditions. With a focus on continuous improvement, we participate in the safeguarding of healthy and efficient markets for everyone who participates.

Based in ‘The Domain’ neighborhood, Optiver’s Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software and hardware engineering initiatives. With tech innovation an integral part of our core business, the booming city proved an ideal backdrop for our heavy investment into machine learning, research infrastructure and big data computing. What’s more, with world-class music, food and art scenes, as well as countless scenic outdoor activities, the quality of life for Austin Optiverians is second to none.

What you’ll do

• Own PCBA manufacturing test strategy across the product lifecycle:
• EVT/DVT/PVT → ramp → sustaining
• coverage definition, limits/thresholds, logging, and yield monitoring
• Design and build PCBA test fixtures spanning:
• ICT & Functional verification test (FVT)
• Burn-in / reliability screening
• Final assembly tests (FATP)
• System interoperability testing
• Develop automated test software with strong emphasis on Python scripting, maintainability, and scalability
• Partner with contract manufacturers to deploy tests on the line, train vendor teams, and drive continuous improvement.
• Drive DFT/DFM feedback into design reviews with EE and ME teams
• Define and maintain test documentation:
• Test plans, work instructions, golden unit strategy, calibration/maintenance procedures, and acceptance criteria.
• Use modern tooling (including AI-assisted workflows where helpful) to speed up debug, log triage, and documentation—without compromising repeatability and traceability.
• Travel periodically to supplier sites to support NPI builds, line bring-up, and ramp

Who you are

Requirements

• BS in Electrical Engineering, Computer Engineering, or related discipline.
• 3+ years of industry experience
• Strong Python skills: automation, hardware I/O, parsing logs, data analysis, packaging/CI practices.
• Ability to understand register maps and leverage HALs for creation of test scripts
• Proficient ECAD skills to develop schematics and oversee layout work: Altium, Mentor Graphics, Cadence or equivalent.
• Hands-on experience developing and deploying manufacturing PCBA tests in a production environment.
• Comfortable with hardware debug using scopes, DMMs, logic analyzers, protocol analyzers; strong troubleshooting instincts.
• Experience working with contract manufacturers and external vendor engineering teams, including clear communication and escalation management.

Nice to have

• Familiarity with FPGA prototyping and basic RTL concepts (enough to support debug/bring-up and test hooks).
• Familiarity with C and/or C++ for embedded firmware development
• Experience with high-speed digital board debug (clocking, SERDES links, power sequencing, SI/PI-related failure modes).
• Solidworks familiarity.

What you’ll get:

• Work alongside best-in-class professionals from over 40 different countries.
• Performance based bonus structure that is unmatched anywhere in the industry. We combine our profits across desks, teams and offices into a global profit pool fostering a truly collaborative environment to work in.
• Ownership over initiatives that directly solve business problems.  

Alongside this you will get great other benefits such as 25 paid vacation days and market holidays, fully paid health insurance, daily breakfast and lunch, training opportunities, 401(k) match up to 50% and charitable match opportunities, regular social events and clubs, and many more.

At Optiver, we are committed to creating a diverse and inclusive environment of mutual respect. Optiver recruits, employs, trains, compensates and promotes regardless of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics. 

Payroll Project Manager & Administrator (Contract)

We are seeking an experienced Payroll Project Manager & Administrator on a contract basis to oversee and execute payroll-related projects while managing day-to-day payroll administration. This role combines strategic project leadership with hands-on payroll processing to ensure accurate, compliant, and timely payroll delivery.

Key Responsibilities

Lead payroll system implementations, migrations, or upgrades from planning through go-live, managing timelines, budgets, and stakeholder communication. Oversee end-to-end payroll processing, including calculating wages, deductions, bonuses, and tax withholdings. Develop and document payroll processes, controls, and standard operating procedures. Identify and resolve payroll discrepancies, conducting root cause analysis to prevent recurrence. Manage relationships with external payroll vendors and benefits providers. Prepare payroll reports, reconciliations, and audit documentation as needed.

Qualifications

Minimum 5 years of experience in payroll administration, with at least 2 years managing payroll projects. Proficiency with major payroll platform; ideally Paychex & ADP. Proven ability to manage multiple workstreams, meet deadlines, and communicate effectively across all levels of an organization. CPP (Certified Payroll Professional) or PMP certification is a plus.

Contract Details

This is a contract engagement with a defined scope and timeline, to be discussed during the hiring process. Remote or hybrid arrangements may be available depending on project requirements.

Optiver is seeking Quantitative Researchers to join our High-Frequency Trading (HFT) Team, where we run fully automated trading strategies powered by Machine Learning. As part of this high-impact, collaborative team, you’ll play a key role in developing, improving, and executing trading strategies, directly shaping our research and execution pipeline.

What you'll do:

• Conduct alpha, signal, and feature research, developing models to enhance predictions and improve trading algorithms
• Collaborate with peers to review research, solve complex problems, and refine trading strategies
• Optimize research workflows to increase efficiency and effectiveness
• Contribute to strategic discussions, helping shape the future direction of the business

What you'll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• 2+ years of quantitative research experience on a successful futures/equities trading team
• Proven track record of developing profitable trading strategies, with strong analytical and mathematical skills
• Experience in computationally intensive research
• BS, MS, and/or PhD in a quantitative or technical field
• Proficiency in programming languages (C++, C, Python, Java)
• A highly collaborative team player, valuing diverse perspectives and building strong partnerships
• A self-starter who takes initiative, sets ambitious goals, and proactively identifies opportunities for impact

Who we are:
At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Austin is home to Optiver’s main research, design and manufacturing facility for our custom trading system hardware. Fully understanding the components we use and the (exchange) environments in which our systems operate is critical to our success. We’re looking to expand the team with a quantitative researcher to help in hardware R&D.

With your quantitative skills and affinity for hardware, you’ll work with the engineers in the lab devising experiments, gathering data, running analysis and ultimately building an understanding of how things actually work. Using this knowledge to help to improve our designs, systems and the strategies that run upon them.

What you’ll do

You’ll be involved in a wide variety of tasks which focus around your quantitative skills and understanding of hardware. This is just a few of the things you’ll do:

• Design, build and run experiments to characterize hardware such as switches, routers and trading systems at picosecond scales
• Work with execution researchers at all of our offices to understand real world vs lab performance of our trading systems and strategies
• Work with our software engineers in the lab to scale out and automate your research such that we can apply it at a global scale
• Be part of designing the next generation of systems and strategies which take your findings into account
• Your experience with lab measurements makes you a valuable resource for anyone looking at production data or trying to improve our production captures
• Help run the lab, make sure we have everything we need to run upcoming experiments and manage the queue of work
• Be involved with suppliers to test and understand next generation systems and measurement equipment

What you'll get

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• Highly competitive compensation package
•  Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are

The ideal candidate combines a strong quantitative background with a deep understanding of hardware and can combine both of these skills to drive analysis that helps us improve our designs and strategies:

• You have a strong understanding of quantitative analysis methods and have the ability to present findings to others
• You are grounded in physical reality; you have an understanding of how hardware works and have the ability to use this knowledge to form hypothesis, conduct physical experiments and draw conclusions from that
• You are comfortable working with Python and Jupyter notebooks
• You’re not afraid to be hands on in a datacenter lab environment
• Programming experience in low level languages such as C/C++ or VHDL is a strong plus
• Experience with (low-latency) networks and related hardware is a strong plus
• An educational background in Statistics, Mathematics, Engineering, Computer Science, or similar (Masters/PhD preferred)
• A preference for working collaboratively with like-minded people
• A passion for solving problems and a drive for results

Who we are

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Based in ‘The Domain’ neighborhood, Optiver’s Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software, and hardware engineering initiatives. With tech innovation an integral part of our core business, the booming city proved an ideal backdrop for our heavy investment into systems, infrastructure, machine learning, big data and computing R&D efforts. What’s more, with world-class music, food and art scenes, as well as countless scenic outdoor activities, the quality of life for Austin Optiverians is second to none.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

The Optiver Research Platform (ORP) is a vertically integrated platform team that manages both high-performance compute infrastructure and the software platform layered on top. ORP enables Optiver’s global research teams to define and execute large-scale computational problems such as simulations and model training through streamlined orchestration of complex workflows. By owning the full stack, from datacenter hardware to distributed research tooling, ORP provides the fastest possible turnaround time for experiments and continually expands Optiver’s ability to generate insights from the markets we operate in.

What you’ll do:

• Expand the Optiver Research Platform’s capabilities by building features and improving performance across service orchestration, job scheduling, cluster management, big-data processing, and other core services that business teams directly interface with.
• Build and evolve a fully managed compute & data platform layer for improved scale & reliability in Python & Rust.
• Explore cutting-edge technologies and integrate them into Optiver’s research workflows to enhance performance and allow deriving better insights.
• Collaborate globally with Optiver business teams including traders, researchers, and engineers to push their understanding of the market to new heights.

What you’ll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Experience leading large-scale engineering projects
• Strong engineering instincts and a deep understanding of computer science fundamentals
• Experience in distributed systems
• Expertise in Python is required; experience with C, C++, or Rust is a plus
• Experience working with GPUs and the CUDA ecosystem is a plus
• Ability to tackle complex technical problems at the intersection of infrastructure and research enablement
• Commitment to continuous learning and improvement in a rapidly evolving environment
• Excellent communication and collaboration skills for working with global researchers and engineers
• Readiness to set technical direction, promote engineering principles, and do the right thing

Who we are:

Optiver is a global market maker driven by technology. Our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency and stabilizing the market no matter the conditions. With a focus on continuous improvement, we prioritize safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software development and hardware engineering. The team here plays a central role in advancing our heavy investment in machine learning, research infrastructure and big data computing. Located in The Domain neighborhood, the office is surrounded by world-class music, great food and easy access to outdoor spaces, providing a vibrant setting for the team.

We value in-person collaboration across disciplines, and this role is based on-site in our Austin office.

Applicants may submit up to three application per calendar year across all open roles.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Optiver’s hardware research, development, and manufacturing team in Austin designs some of the world’s most competitive trading systems. Within this group, our hardware research team explores how every device in our environment behaves under real-world conditions from low-level network cards to custom hardware.

As we continue to grow, we’re looking for a software engineer with a research mindset to join this team. In this role you will investigate the behavior and performance of all devices we use or interact with in our trading environment. We’re looking for someone who can apply strong software engineering principles to the systems we build to do this.

You’ll collaborate closely with teams across the organization, applying your knowledge to improve our systems and trading strategies.

What you’ll do:

As Software Engineer in Hardware Research, your key responsibilities include:

• Design and develop software to help investigate the performance and behavior of trading hardware and communication devices
• Conduct hands-on research with a wide range of hardware components and network protocols
• Collaborate with hardware, trading, and infrastructure teams to share findings and improve systems
• Interact directly with low-level devices, drivers, and embedded systems using C/C++

What you’ll get:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Strong foundation in computer science fundamentals and programming
• Proficiency in Python, including familiarity with libraries and APIs
• Comfortable conducting research and data analysis in Python using Jupyter Notebooks
• Experience writing software in C/C++
• Creative problem-solving skills at the system level
• Solid understanding of the OSI model and networking fundamentals

Nice to have:

• Experience with low-level hardware/software interactions
• Familiarity with devices and drivers in Linux
• Experience with low-level communication APIs and frameworks such as EFVI, RoCE, DPDK, and Onload
• Hands-on experience with high-precision timestamping of electrical signals and network packets
• Experience working with high-performance trading network hardware (both packet- and circuit-switched)
• Knowledge of communication protocols, especially Ethernet
• Exposure to network equipment operating systems like Cisco IOS, Arista EOS, MOS or similar

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics

Optiver’s hardware research, development, and manufacturing team, based in Austin, builds some of the world’s fastest and most competitive trading systems. As we continue to grow, we’re looking for a software engineer to help develop the OS and software that powers our custom hardware.

This role spans everything from low-level hardware integration to collaborating with infrastructure teams that manage production systems and traders who configure them to fit their specific needs. While we primarily use Python and Linux, you’ll also encounter a diverse tech stack including TCL, C, C++, ASM, VHDL, and DSLs across platforms from x64 servers to embedded cores.

What you’ll do:

As Software Engineer, your key responsibilities include:

• Designing and maintaining the OS and software stack behind our trading hardware
• Building and supporting Python-based interface layers to control and monitor hardware systems
• Developing software for STM processors embedded on prototype boards
• Managing and supporting a fleet of hardware systems in a live production environment
• Collaborating closely with hardware, infrastructure, and trading teams to ensure seamless system performance
• Contributing to infrastructure automation and transitioning into embedded development and low-level hardware logic over time

What you’ll get:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Strong foundation in computer science fundamentals and hardware systems
• Proficiency in Python, including familiarity with relevant libraries and APIs
• Experience writing software in C/C++
• Creative problem-solving skills at the system level
• Ability to collaborate with developers and researchers

Nice to have:

• Experience with low-level hardware/software interactions (drivers, buses, pins, registers, etc.)
• Ability to read and interpret datasheets and electrical engineering schematics
• Familiarity with devices and drivers in Linux
• Experience with FPGA design using VHDL/Verilog and the Vivado suite of tools
• Knowledge of communication protocols, especially Ethernet
• Exposure to network equipment operating systems like Cisco IOS, Arista EOS, or Juniper MOS
• Experience working with high-performance trading network hardware (both packet- and circuit-switched)

Who we are:

At Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilising the market no matter the conditions. With a focus on continuous improvement, we prioritise safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Our Software Engineers build proprietary trading systems which directly impact the financial markets. Our software engineering teams leverage technology to solve a variety of difficult problems.

Our trading strategies must respond to market events in microseconds or less, and we automatically price large, diverse sets of financial instruments with extremely low error tolerance. We continually refine, store, and analyze terabytes of data produced by market activity and our trading systems. Our user interfaces must present coherent, responsive real-time visualizations of market activity and system performance while providing intuitive control of a highly complex system. Our core systems must provide a stable, performant, and trusted foundation on which our systems are built.

Technology at Optiver:

At Optiver we pride ourselves on being real engineers, not just coders. Our engineers work closely with traders to identify the business problems we face and determine how they should be solved. We apply a disciplined and scientific approach. We engineer simple, well-architected solutions that meet the dynamic needs of our traders. Our passion is to solve problems which really matter to the business, and we take pride in the quality of our solutions.

What you’ll do:

• Design, develop, support, and maintain trading systems, tools, and infrastructure
• Collaborate deeply with traders, risk analysts, researchers, and other engineers
• Gain and develop an in-depth understanding of trading theory and practice

What you’ll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Strong engineering instincts and a deep understanding of computer science fundamentals
• Experience writing software in C++, C#, C, and/or Python
• A passion for clean code, simple well-architected systems and continuous improvement
• Ability to collaborate with developers, traders, and business operations

Who we are:

Optiver is a tech-driven trading firm and leading global market maker. As one of the oldest market making institutions, we are a trusted partner of 70+ exchanges across the globe. Our mission is to constantly improve the market by injecting liquidity, providing accurate pricing, increasing transparency and acting as a stabilizing force no matter the market conditions. With a focus on continuous improvement, we participate in the safeguarding of healthy and efficient markets for everyone who participates.

Based in ‘The Domain’ neighborhood, Optiver’s Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software and hardware engineering initiatives. With tech innovation an integral part of our core business, the booming city proved an ideal backdrop for our heavy investment into machine learning, research infrastructure and big data computing. What’s more, with world-class music, food and art scenes, as well as countless scenic outdoor activities, the quality of life for Austin Optiverians is second to none.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

The Optiver Research Platform (ORP) is a vertically integrated platform team that manages both high-performance compute infrastructure and the software platform layered on top. ORP enables Optiver’s global research teams to define and execute large-scale computational problems such as simulations and model training through streamlined orchestration of complex workflows. By owning the full stack, from datacenter hardware to distributed research tooling, ORP provides the fastest possible turnaround time for experiments and continually expands Optiver’s ability to generate insights from the markets we operate in.

What you’ll do:

• Expand the Optiver Research Platform’s capabilities by building features and improving performance across service orchestration, job scheduling, cluster management, big-data processing, and other core services that business teams directly interface with.
• Build and evolve a fully managed compute & data platform layer for improved scale & reliability in Python & Rust.
• Explore cutting-edge technologies and integrate them into Optiver’s research workflows to enhance performance and allow deriving better insights.
• Collaborate globally with Optiver business teams including traders, researchers, and engineers to push their understanding of the market to new heights.

What you’ll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Experience leading large-scale engineering projects
• Strong engineering instincts and a deep understanding of computer science fundamentals
• Experience in distributed systems
• Expertise in Python is required; experience with C, C++, or Rust is a plus
• Experience working with GPUs and the CUDA ecosystem is a plus
• Ability to tackle complex technical problems at the intersection of infrastructure and research enablement
• Commitment to continuous learning and improvement in a rapidly evolving environment
• Excellent communication and collaboration skills for working with global researchers and engineers
• Readiness to set technical direction, promote engineering principles, and do the right thing

Who we are:

Optiver is a global market maker driven by technology. Our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency and stabilizing the market no matter the conditions. With a focus on continuous improvement, we prioritize safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software development and hardware engineering. The team here plays a central role in advancing our heavy investment in machine learning, research infrastructure and big data computing. Located in The Domain neighborhood, the office is surrounded by world-class music, great food and easy access to outdoor spaces, providing a vibrant setting for the team.

We value in-person collaboration across disciplines, and this role is based on-site in our Austin office.

Applicants may submit up to three application per calendar year across all open roles.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

Optiver is looking for Senior Software Engineers to join our High-Frequency Trading (HFT) team in Austin, TX. Our HFT team is comprised of software engineers and researchers who design, improve and execute fully automated trading strategies using machine learning. As a senior engineer, you’ll lead complex technical projects, help shape the direction of our trading infrastructure, and work closely with teams to share knowledge and drive technical progress.

Our software engineers work on some of the most challenging algorithmic problems in the world. The team owns the problem end to end, from data to simulation to the execution of orders in production. The system is built to be robust, enabling research at scale while running complex machine learning models with low latency across thousands of financial instruments.

What you’ll do:

• Establish vision and technical direction for machine learning-driven trading systems that help maintain our position as a leading team in futures and equities trading
• Partner deeply with researchers to solve complex, high-value business problems
• Build and maintain end-to-end trading infrastructure, from research to production execution
• Push frequent, impactful code changes to the production environment
• Contribute to the Optiver stack and our pricing, research and trading models from ideation through to implementation
• Ensure new and existing programs adhere to our coding, architectural, and operational standards
• Develop new and existing programs adhere to our coding, architectural, and operational standards 

What you’ll get:

You’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.

In addition, you’ll receive:

• The opportunity to work alongside best-in-class professionals from over 40 different countries
• A highly competitive compensation package
• Global profit-sharing pool and performance-based bonus structure
• 401(k) match up to 50%
• Comprehensive health, mental, dental, vision, disability, and life coverage
• 25 paid vacation days alongside market holidays
• Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Who you are:

• Experience leading large scale projects
• Solid engineering instincts and a deep understanding of computer science fundamentals
• Strong expertise in C++ is strongly preferred; experience with C, Python, or Linux is a plus
• 2+ years preferred of C++ experience in low-latency systems like market data ingestion, order routing, execution performance, or simulation frameworks.
• Innovative, out-of-the-box thinking grounded in real-world pragmatism
• Desire to continuously improve in a rapidly evolving environment 
• Readiness to set technical direction, promote engineering principles, and do the right thing

Who we are:

Optiver is a global market maker driven by technology. Our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency and stabilizing the market no matter the conditions. With a focus on continuous improvement, we prioritize safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.

Our Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software development and hardware engineering. The team here plays a central role in advancing our heavy investment in machine learning, research infrastructure and big data computing. Located in The Domain neighborhood, the office is surrounded by world-class music, great food and easy access to outdoor spaces, providing a vibrant setting for the team.

We value in-person collaboration across disciplines, and this role is based on-site in our Austin office.

Applicants may submit up to three application per calendar year across all open roles.

Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.

D1 Senior Software Engineer

Build, Deploy, and Maintain AI for an Unpredictable World

Striveworks helps organizations harness the power of artificial intelligence to solve real-world national security and business challenges by serving as the command center between data, models, and business outcomes. Founded by data scientists and engineers, Striveworks set out to make the journey from deployment to ongoing optimization simple and effective.

With Striveworks, organizations aren’t just deploying AI—they’re building systems that remain reliable, adaptable, and ready to scale in an unpredictable world. Mission-critical operations require models that perform where they’re deployed, scale as workloads grow, and adapt rapidly as AI capabilities advance. Striveworks meets these demands, increasing reliability and performance while lowering costs—and enabling confident, data-driven decision-making in dynamic environments.

The Role

As a Senior Data Scientist at Striveworks, you’ll be challenged—and trusted—on day one to be a core contributor to the projects, products, and direction of the company. You will be a key Striveworks representative and technology builder on projects and solutions that leverage Chariot, our proprietary AI operations (AIOps) platform, and you will inform and contribute to future capabilities of that platform. You will work as part of a team of data scientists, machine learning engineers, software engineers, and DevOps engineers to transform machine learning models into functional products.

You’re right for this opportunity if you value and possess technical expertise and enjoy pushing the boundaries of your own capabilities. You’re outcome driven and are passionate about applying both software and data science to solve real-world problems. You know that being customer focused, rigorous in approach, clear in communication, and able to identify repeatable value opportunities are all critical to success. You are able to sense the needs of the customer, identify evolving demands, and then synthesize that feedback into actionable suggestions for Striveworks’ product teams.

Your day-to-day will include:

• Working with customers, engineers, and other stakeholders to define clear requirements that solve customers’ problems and leverage the capabilities of our AIOps platform
• Developing and validating machine learning models and custom analytic algorithms that are applied to image, video, text, geospatial, time series, and structured data
• Orchestrating and automating complex data and analytic pipelines
• Implementing AI-based software solutions for cloud and edge environments
• Conducting mission-critical field work and interfacing with customers and other stakeholders

This position offers a fully remote work environment, or you can work hybrid/on site at our office in northwest Austin, TX. You will be expected to travel up to 25% of the time.

The Right Fit

In addition to the specific skills and expertise detailed below, we are looking for individuals who share our values. Sharing a set of values allows us to move at the speed of trust. 

Collectively, we value a high-trust work environment where people respect each other and use candor kindly and constructively. We value work that intersects passion and perseverance, we geek out about the potential of our contributions, and we find joy in working hard on things that matter. Finally, we value taking ownership, having agency, and feeling individual responsibility for collective results.

Here’s what we’re looking for:

• Bachelor's degree in computer science, machine learning, mathematics, or a related discipline and 6+ years of relevant experience 
• Expertise in machine learning, data science, and their application to image and video data, as well as experience deploying those capabilities to production environments
• Expertise in implementing and analyzing algorithms and data structures
• Proficiency in programming languages and libraries common to machine learning; excellence in Python is essential, as is knowledge of libraries like TensorFlow, PyTorch, and/or scikit-learn
• Exposure to DevOps tooling and best practices (e.g., Git, Docker, Kubernetes, CI/CD)
• Active Secret (or above) US security clearance
• Due to the nature of this role, candidates must have US citizenship

The Wish List

We’re very interested in candidates who possess the above qualifications, and we appreciate and consider the addition of:

• Graduate degree in computer science, machine learning, mathematics, or a related discipline
• Experience processing a variety of unstructured data types (e.g., imagery, full motion video, text, acoustic, sonar, RF, geospatial, graphs, or telemetry signals)
• Experience building AI agents and agentic workflows
• Experience implementing ETL pipelines, data pipelines, and/or workflow automation
• Experience developing solutions in a compiled programming language (Go, Rust, C++, Java, etc.)
• Experience building full-stack applications (back end, front end, REST) or solutions targeted for cloud infrastructure (AWS, Azure, GCP) and/or Kubernetes (K8s)
• Experience leading a small team
• Experience delivering technology solutions in secure government environments
• Experience working with federal, state, and/or local government customers

The anticipated base pay range for this position is $170,000–$200,000/year. Striveworks’ total compensation package includes a competitive base salary, equity grants, and cash bonuses.

The Benefits

• Medical/dental/vision insurance
• Voluntary life, long-term disability, accident, and hospital indemnity insurance
• HSA and FSA (including dependent care FSA) plans 
• 401(k) plan
• Unlimited PTO
• Paid parental leave

Striveworks is an Equal Opportunity Employer and does not discriminate in employment on the basis of race, color, religion, belief, sex (including pregnancy and gender identity or expression), national origin, social or ethnic origin, political affiliation, sexual orientation, marital status, disability, genetic information, age, membership in an employee organization, retaliation, parental status, military service, or other non-merit factors. Striveworks will not tolerate discrimination or harassment of any kind.

If you require assistance or a reasonable accommodation in the application process, please contact Operations at hr@striveworks.us.

In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete an employment eligibility verification form upon hire.

Striveworks is a participating employer in the E-Verify program.