Principal, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab is seeking Principal CPU Architecture & Performance Engineer to lead the definition, analysis, and optimization of next-generation CPU microarchitectures (RISC-V core). This role is focused on end-to-end performance: from architectural trade-offs and workload characterization to micro-architectural modeling, simulation, and silicon bring-up correlation.

You will work closely with architecture, design, compiler, and system teams to drive performance and efficiency across a broad set of real-world workloads

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42918

• Define and evaluate CPU micro-architectural features for future cores (frontend, execution engine, memory hierarchy, interconnect).
• Lead performance analysis using simulators, RTL.
• Help develop and validate performance models (cycle-accurate, trace-driven, statistical).
• Characterize workloads (SPEC, server, client, AI/ML, cloud, internal traces) and translate findings into architectural requirements.
• Identify performance bottlenecks and propose data-driven optimizations.
• Drive architecture-to-implementation alignment with design team.
• Collaborate with compiler, OS, and system architects on cross-stack performance issues.
• Mentor senior and staff engineers; provide technical leadership across projects.
• Work leading to patents and publication

What You Bring

• Master’s with 18+ years of experience in Computer Engineering, Computer Science, or related field.
•  or PhD with 15+ years of experience preferred.
• 10+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC-V, ARM or X86 architectures.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Familiarity with compiler optimizations and hardware/software co-design.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Experience analyzing large performance datasets and traces.
• Proven ability (Tapeout / Patents /Publications) to influence architecture / micro architectural decisions through quantitative analysis.

Preferred Qualifications

• Background in power/performance/area (PPA) trade-off analysis.
• Experience with SIMD/Vectors.
• Experience with compiler optimizations and hardware/software co-design.
• Prior technical leadership at Senior Staff or Principal level. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Job Title: Principal Engineer, AI System Architect (Hardware)

The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a Technical Lead role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42852

What You’ll Do

• Technically Lead the architecture team with strong  direction, shaping system‑architecture strategy and advancing key innovations
• Conduct system-level architectural research for next-generation AI systems, spanning compute, memory, and interconnect/network subsystems.
• Develop and maintain analytical and simulation-based system modeling frameworks to evaluate AI workloads and identify performance, scalability, and efficiency bottlenecks at rack- and system-scale. 
• Analyze representative and emerging system-level architectural research (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power.  
• Drive architecture-level design decisions through quantitative modeling, design-space exploration, and performance/power projections. 
• Perform comparative studies of alternative system architectures, reporting performance and performance-per-watt metrics to guide strategic technology choices. 
• Collaborate closely with cross-functional teams in hardware architecture, memory, interconnect, and system engineering to align modeling insights with implementation realities.  
• Communicate architectural insights and recommendations through clear technical presentations and documentation.   
• Occasional domestic and international travel (<10%).

 What You Bring

• Ph.D. in Computer Science, Electrical Engineering, or a related field preferred,  with 15+ years of experience in system architecture for large-scale computing platforms, with a strong focus on AI workloads 
• Proven hands-on experience developing analytical and event-driven simulation models for system-level performance evaluation. 
• Deep understanding of AI system hardware architectures, including compute, memory hierarchies, and high-performance interconnects.
• Strong knowledge of modern and emerging AI workloads, including LLMs, DLRMs, and large-scale training and inference systems.
• Demonstrated ability to translate workload characteristics and modeling results into actionable architectural design decisions.
• Proficiency in Python, C++, and PyTorch for modeling, analysis, and experimentation. 
• Excellent written, verbal, and presentation communication skills, with the ability to influence technical direction across teams.
• A collaborative mindset, intellectual curiosity, and resilience in tackling complex, open-ended system-level challenges. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Job Title: Principal Engineer, AI System Architect (Hardware)

 What You’ll Do
The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a Technical Lead role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42852

• • Technically Lead the architecture team with strong  direction, shaping system‑architecture strategy and advancing key innovations
  • Conduct system-level architectural research for next-generation AI systems, spanning compute, memory, and interconnect/network subsystems.
• Develop and maintain analytical and simulation-based system modeling frameworks to evaluate AI workloads and identify performance, scalability, and efficiency bottlenecks at rack- and system-scale. 
• Analyze representative and emerging AI workloads (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power.  
• Drive architecture-level design decisions through quantitative modeling, design-space exploration, and performance/power projections. 
• Perform comparative studies of alternative system architectures, reporting performance and performance-per-watt metrics to guide strategic technology choices. 
• Collaborate closely with cross-functional teams in hardware architecture, memory, interconnect, and system engineering to align modeling insights with implementation realities.  
• Communicate architectural insights and recommendations through clear technical presentations and documentation.   
• Occasional domestic and international travel (<10%).

 What You Bring

• Ph.D. in Computer Science, Electrical Engineering, or a related field preferred,  with 15+ years of experience in system architecture for large-scale computing platforms, with a strong focus on AI workloads 
• Proven hands-on experience developing analytical and event-driven simulation models for system-level performance evaluation. 
• Deep understanding of AI system hardware architectures, including compute, memory hierarchies, and high-performance interconnects.
• Strong knowledge of modern and emerging AI workloads, including LLMs, DLRMs, and large-scale training and inference systems.
• Demonstrated ability to translate workload characteristics and modeling results into actionable architectural design decisions.
• Proficiency in Python, C++, and PyTorch for modeling, analysis, and experimentation. 
• Excellent written, verbal, and presentation communication skills, with the ability to influence technical direction across teams.
• A collaborative mindset, intellectual curiosity, and resilience in tackling complex, open-ended system-level challenges. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Join Samsung Semiconductor to guide the development and design evaluation of next‑generation semiconductor packages and memory devices. In this role as a Staff Engineer for Mechanical Simulation, you will partner with cross‑functional, multicultural teams to advance innovative packaging solutions, automate simulation workflows, and bridge the gap between numerical predictions and experimental validation.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy with 10-20% of domestic and international travel.

Reports to: Principal Engineer

What You’ll Do

• Perform advanced numerical modeling and simulation to evaluate and improve the performance and reliability of cutting‑edge semiconductor packages and memory devices.
• Provide mechanical and thermal design support throughout package‑ and system‑development stages—from concept and detailed modeling to qualification and reliability testing.
• Apply hands‑on expertise in mechanical and thermal modeling of micro‑electronic components, including interconnects, solder joints, BGAs, and advanced‑packaging architectures.
• Develop and maintain scripts for process automation (Python, MATLAB, or ANSYS APDL) to streamline pre‑processing, simulation, and post‑processing workflows for parametric and sensitivity studies.
• Leverage a solid understanding of semiconductor manufacturing, advanced‑packaging technologies, material properties, and associated design and reliability constraints.
• Design, execute, and interpret validation experiments that correlate and calibrate simulation models with empirical data.
• Contribute effectively both independently and as a member of cross‑functional, cross‑cultural, and globally distributed teams.

What You Bring

• Ph.D. in Mechanical Engineering, Materials Science, Physics, or a related field. (Equivalent combination of a Master’s degree and extensive professional experience also welcomed).
• 10+ years of hands‑on modeling and simulation experience in the high‑tech or semiconductor industry.
• Proven expertise with leading simulation tools such as ANSYS, Abaqus, HyperMesh, and their associated pre‑/post‑processing software.
• Proficiency in thermal‑analysis platforms Flotherm and Icepak, together with related utilities.
• Extensive experience in static and dynamic simulations, covering linear and nonlinear analyses that involve geometric and material non‑
• Deep knowledge of thermal analysis and cooling‑design strategies for advanced packaging solutions.
• In‑depth understanding of advanced semiconductor packaging, interconnect structures, and reliability‑modeling techniques.
• Strong technical‑writing skills, capable of producing clear, comprehensive documentation and communicating complex concepts to both technical and non‑technical audiences.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

Job Title: Principal engineer, AI Serving Framework Architect (Software)

What You’ll Do    

The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a key role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42853

• As a Tech Lead, leading research teams in Korea and proposing technical direction
• Research on dynamic scheduling methodologies for maximizing AI inference performance in multi-rack scale memory-centric systems, comprised of heterogeneous compute-capable memory and hierarchical memory
• Investigating methods to accelerate search operations in RAG’s vector DB and AI Agent’s knowledge-graph by leveraging compute-capable memory
• Studying strategies for optimally placing KVCache and a vector DB in hierarchical memory to minimize frequent SSD accesses and reduce IO stalls
• Proposing SW design for implementing the derived optimization algorithms on open-source platforms such as vLLM

What You Bring

• PhD in Computer Science or a related field with 10+ years of experience in AI Serving Framework for large-scale computing, with focusing on the AI workloads. 
• Led a project to build and optimize a Large Language Model (LLM) Inference Software Stack on a multi-rack scale system to deliver AI Inference services to over 100,000 users. 
• Extensive experience in designing AI Inference Software Stacks for heterogeneous devices.In-depth understanding of the internal architecture and operation mechanisms of inference engines such as vLLM. 
• Proficiency in AI Inference System Profiling and optimization. 
• Knowledge and practical experience with future AI workloads, including reasoning models, multi-modal solutions, AI agents, and world models. 
• Strong understanding of compute, memory, and networking bottlenecks in AI systems. 
• Required skillsets: PyTorch, Python, and C++ 
• A collaborative mindset, curiosity, and resilience in solving complex challenges. 
• Excellent verbal, presentation, and written communication skills. 
• (Nice to have) Native or fluent Korean speakers are preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build. Understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change 

#LI-SF1

Principal Engineer, SOC Design

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Job ID:  42866

Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy

• Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
• Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
• Reviews 3^rd party IPs including ARM cores, DDR controller, and UCIe PHY 
• Responsible for integrating the third part IPs and sub system at top level
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

What You Bring

• Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
• Highly motivated with good verbal and written communication skills.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
• Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
• Good understanding of PPA (performance, power, and area) trade-offs.
• Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
• Experience in interfacing 3^rd party service companies for DFT/PI/PD.
• Good knowledge and experience in AMBA bus fabric, ARM cores.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

What You’ll Do

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Support trace-driven power modeling, aligned with C/SystemC workload traces.
• Perform synthesis-assisted calibration using average and worst-case power anchors when available.
• Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
• Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
• Contribute to scalable IP-wise composition for full-system power simulation.

What You Bring

• Bachelors degree 20+ years of experience or Masters degree 18+ years of experience.
• Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
• Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
• Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
• Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
• Familiarity with SystemC or transaction-level modeling.
• Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
• Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Preferred Qualifications

• Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
• Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
• Exposure to low-power design and thermal management.
• Exposure to power macromodeling, power estimation flows, or architectural power analysis.

Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

Advanced Circuit and Systems (ACAS) is looking for a highly skilled engineer that has strong background and hands-on experience on RFIC design. The candidate will be developing next-generation RF transceivers and mixed-signal circuits for

What You’ll Do

• Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS technologies.
• Lead efforts to perform chain and chip level design verification and production support tasks.
• Work closely with digital and software developers to develop an implementation that meets
• system requirements.
• Research in advanced wireless techniques for highly integrated RFICs

What You Bring

• Bachelor’s with 20+ years of experience or  Master's with 18+ years of experiences or PhD with 15+ years of experience in a related field.
• Hands-on experience in designing various RF/Analog integrated circuits, such as LNA, Mixer, RF VGAs, PA, VCO, etc., in deep sub-micron CMOS technologies.
• Ability to comprehend RF transceiver system level requirements and translate into circuit level specifications. Excellent problem solving and analytical skills are essential.
• Technical leadership, mentoring, and post-silicon validation expertise are essential.
• Specialized knowledge in high-speed I/Os (SerDes, DDR) or data converters is a bonus.
• Strong knowledge on IC design CAD tools such as Spectre, SpectreRF, Spice, Matlab, and/or ADS.
• Thorough understanding of the physical layout requirement and ability to perform the critical layouts.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

What You’ll Do

Samsung Display’s America R&D Lab is hiring for a Senior Systems Engineer, for a knowledgeable, self-driven individual contributor in field of display metrology and standardization. Our lab works closely with Samsung Display Co. (SDC), which supplies premium displays for smartphones, laptops, monitors, and TVs using industry leading technology. SDC is the first company in the world to mass produce flexible OLEDs, foldables and QD displays, creating the best displays that connect technology and people in a more valuable way.

This role is part of a dedicated team within a large global organization, advancing display metrology, product certifications, and standardization through collaboration with diverse stakeholders to deliver outcomes that directly impact company products.

This is an unique opportunity for a grounded, adaptable professional who is comfortable filling the gap, bringing patience and expertise to shape display eco-system over time.

We believe that innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy with 10-20% of domestic and international travel.

Reports to: Principal Engineer

• Develop industry-leading test methodology and solutions
• Develop display-related standards, ensure alignment with organizations, e.g: VESA, ICDM, SMPTE
• Compare and analyze display performance to standardization targets, and recommend actions.
• Develop display metrology test patterns and test protocols; propose to IEC and ICDM as appropriate.
• Publish in peer-reviewed papers, conferences, and industry magazines that advances the display ecosystems.
• Communicate complex technical concepts clearly and effectively to diverse audience..
• Complete other responsibilities as assigned.

What You Bring

• Minimum of Master’s of Science degree in Physics, Electrical, Optics, or Materials Engineering or related field OR PhD is preferred.
• 3-5 years of relevant industry experience.
• Required expertise with display metrology and related instruments (ie. Spectrometer, colorimeter)
• Experience in Python, Matlab (Octave), or C++
• Conversant with industry forums and standardization procedures is a strong plus.
• Travel internationally several times a year, such as conference presentation, internal standard meetings.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

Senior, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab is  seeking Senior CPU Architecture & Performance Engineer to contribute to performance analysis and microarchitectural optimization of current and next-generation CPU (RISC-V) cores. This role emphasizes hands-on analysis, modeling, and close collaboration with architects and design teams to improve performance across real-world workloads.

You will focus on executing well-defined performance studies, identifying bottlenecks, and helping translate architectural ideas into measurable performance gains

 Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42851

• Perform performance analysis for CPU microarchitectural features under guidance from Staff and Principal engineers.
• Run architectural simulations and analyze results (IPC, CPI stacks, latency and throughput metrics).
• Identify performance bottlenecks in frontend, execution engine, or memory subsystems.
• Assist in evaluating design trade-offs using trace-driven or cycle-accurate models.
• Characterize workloads and benchmarks (SPEC, server, client, internal traces).
• Develop scripts and tools to automate performance analysis.
• Work leading to patents and publication.

What You Bring

• Master’s, or PhD in Computer Engineering, Computer Science, or related field.
• 2+ years of experience in CPU microarchitecture and/or performance engineering.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Experience analyzing large performance datasets and traces.
• Familiarity with compiler optimizations and hardware/software co-design.

Preferred Qualifications

• Experience with RISC-V, ARM or X86 architectures.
• Background in power/performance/area (PPA) trade-off analysis.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Prior tapeout / patent / publication experience. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

What You’ll Do:

As a Principal AI and ML fundamentalist who is an expert at developing cutting-edge AI solutions to complex problems, you will develop code that eventually integrates into production and be responsible for:

• Design, implement, and evaluate novel machine learning and deep learning algorithms.
• Iterate on AI model development; starting from the data needed for training, architecture, input/output representations, evaluation, and deployment. 
• Collaborate with other researcher engineers to prototype and validate complex solutions from academic literature.
• Conduct experiments to benchmark new techniques and evaluate model behavior.
• Develop tools and frameworks to support scalable and reproducible research and development.
• Communicate research findings to leadership in a concise, and convincing manner.
• Stay current with the latest developments in AI/ML and identify relevant innovations.
• Assist in transitioning research prototypes into production-ready systems.

What You Need:

• M.S or PhD degree in Computer Science, or Computer Engineering with strong emphasis on AI and ML.
• Enjoys solving less-defined and complex problems
• Familiarity with good SW practices and development, including code quality, version control, etc.
• Very strong with ML frameworks such as Pytorch, or Tensorflow
• Good understanding of Transformer architectures, attention mechanisms, multi-modal foundation models, diffusion policies, fine-tuning, model distillation, mixture of experts, and other similar topics.
• Has strong ability to debug and determine requirements for AI models in terms of data, training, and evaluation.
• Is up to date with research literature and recent ML techniques and methodologies.

Bonus Qualifications:

• Experience with Reinforcement Learning, self-supervised training, and imitation learning is a plus.
• Experience developing VLA (Vision Language Action) models for robotic manipulation and mobility is a plus.
• Experience developing production AI models is a plus.
• Publications at top conferences are a plus.

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $270,000.00 - $340,000.00 Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is proud to be an Equal Opportunity employer committed to diversity and inclusivity in the workplace. All aspects of employment are decided on the basis of merit, qualifications, and business needs. We do not discriminate based upon race, color, religion, sex, sexual orientation, age, national origin, disability status, protected veteran status, gender identity or any other characteristic protected by federal, state or local laws.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

About the Role

As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.

Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams.

This position is required onsite in San Jose, CA.

Key Responsibilities

• Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms
• Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems
• Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning 
• Serve as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrations
• Interpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutions
• Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on schedule
• Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows
• Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral
• Represent the Leo team in customer technical reviews, design-in engagements, and industry forums

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
• 8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications
• Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
• Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!
• Authorized to work in the US and available to start immediately

Required Experience

• High proficiency in C for embedded firmware development in RTOS environments
• Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
• Proficiency in Python for scripting, test automation, and diagnostic tooling
• Deep hands-on knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
• Experience with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
• Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
• Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
• Experience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines

Preferred Experience

• Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
• Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
• Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
• Experience with server memory performance tuning — latency and bandwidth optimization
• Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus

Compensation

The base salary range for this role is $175,000 – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

The opportunity

As the technical leader of our quality team, you will help define the quality requirements and process controls for our first certified aircraft, Midnight.  You will help us overcome the challenge of providing airline-like levels of safety while offering urban air transportation at a price accessible to all, setting the bar for the entire nascent advanced air mobility industry.  Length of contract is approximately six months.

What you’ll do

• As the lead Metrologist for Archer you will report directly to our Head of Quality, you will have the responsibility for developing and overseeing the metrology program at Archer
• Take a key role in the development and deployment of metrology tools to ensure Midnight meets design requirements.
• Lead the establishment of an aircraft inspection plan during the test phase of the program at both San Jose and Covington
• Execute / Oversee the verification process for the Midnight program incorporating risk based approach to inspection including design reviews and tolerance stack up analysis
• Lead the development and implementation of laser trackers, faro arms and other key metrology equipment
• Specific responsibilities include establishing critical wing dimensions using a laser tracker, develop a plan to use GearPro on CMMs at Archer, develop a program and train inspectors to measure key features on propellers.
• Collaborate and positively influence cross-functional teams to integrate quality into all business processes

What you need

• Knowledge of multiple metrology programs (Calypso, Metrolog, Faro) with at least 10+ years’ experience 
• Experience with complex geometries, model based engineering and GDT.
• Experience with CMMs, laser trackers, broken arms and other metrology equipment
• Experience establishing quality oversight and standardizing inspection techniques
• Experience working in a manufacturing environment in aerospace or other highly regulated environments
• Knowledge of Quality Standards such as AS9100, AS9103, AS9145, and AS6500.

Bonus qualifications

• Experience with composite bonding and verification of non rigid geometries
• Experience with flight line testing and working with the FAA 
• Experience with electric powertrain, gear metrology or aerospace assembly processes

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $143,000 - $183,000 annually.  Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

We are seeking a SAP Security & Platform Systems Engineer. This specialized role is responsible for the secure architecture and technical integration of our SAP S/4HANA RISE environment. The ideal candidate will bridge the gap between traditional SAP Security and modern Cloud Platform administration, ensuring robust, compliant, and well-connected SAP systems.

What You'll Do:

• SAP Security & Access Governance
  • Access Model Ownership: Design, build, and maintain S/4HANA business roles, Fiori catalogs, and authorization groups.
  • Identity Management: Perform configuration and troubleshooting of user provisioning and authentication workflows.
  • Compliance & Audit: Participate in technical efforts for SOX and ITGC audits, managing GRC/IAG (including SoD rulesets and Emergency Access/Firefighter) and providing technical evidence.
  • System and Data-Level Security: Perform vulnerability Assessment, secure Fiori apps/Web services and govern security measures at the CDS-view and OData service layer
• Platform Connectivity & System Administration
  • Cloud Ecosystem Integration: Design and manage technical trust configurations (SAML 2.0, OAuth 2.0, Principal Propagation) across S/4HANA, BTP, and SAP Analytics Cloud (SAC) etc.
  • BTP Management: Administer BTP subaccounts, service entitlements, and technical destinations.
  • Secure Connectivity: Install, configure, and monitor SAP Cloud Connectors to maintain secure data transfer between the RISE private cloud and BTP/external services.
  • Certificate Authority: Manage the full lifecycle of X.509 certificates and SSL handshakes within the entire SAP landscape.
  • RISE Coordination: Serve as the technical liaison with SAP RISE operations for system-level changes (e.g., refreshes, kernel parameters, OS configurations).

What You'll Need: 

• 10+ years in SAP technical roles, with a minimum of 3 years focused on S/4HANA and the Business Technology Platform (BTP).
• Expert proficiency in PFCG, SU24 optimization, and Fiori security architecture.
• Direct, practical experience with the SAP BTP Cockpit and SAP Cloud Connector.
• Proven ability to troubleshoot and manage Identity Protocols: SAML, OAuth2, and OpenID Connect (OIDC).
• Direct experience managing SOX/ITGC compliance requirements in a regulated or publicly traded company, reduce SOD violations
• Skilled in performing comprehensive end-to-end traces (e.g., ST01, browser traces, Cloud Connector logs) to diagnose connectivity and authorization issues. 
• Investigate and resolve Authorization-related issues, performing root cause analysis to prevent future breaches.
• Clear understanding of the SAP RISE shared responsibility model.

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications.

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $152,100 - $190,100. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

We are an equal-opportunity employer committed to creating a diverse and inclusive workplace. All qualified applicants will receive equal consideration for employment without regard to race, color, creed, religion, sex, gender identity, sexual orientation, national origin, disability, uniform service, Veteran status, age, or any other protected characteristic per federal, state, or local law, including those with a criminal history, in a manner consistent with the requirements of applicable state and local laws. 

By applying, you agree to be bound by our candidate privacy policy.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Principal Application Engineer Lead (Semiconductor HW & SW)

Summary:

• You will support Ethernovia’s field team and local customers developing next-generation Automotive, Robotics, and Physical AI platforms to help integrate Ethernovia’s high-performance Ethernet solutions into advanced hardware & software systems. This is a Hybrid-based position based in San Jose, CA.

Key Responsibilities:

• Interface between Ethernovia’s field team and engineering teams, you will bring strong technical competence and the ability to communicate effectively across our multinational teams
• Work closely with field application and business development teams around the world along with internal hardware, software and architecture teams, to support customer designs from early concept and development through validation and production.
• Hands-on role that requires strong problem-solving skills and the ability to operate across fast-moving technical programs
• Work directly with customer engineering teams and the field teams on complex system integration challenges involving high-speed networking, sensor connectivity, AI compute platforms and robotics architectures.
• Day-to-day activities include;
  • Creating design collateral
  • Close collaboration with system and engineering teams
  • Technical customer support and system bring-up
  • Debugging to support integration efforts across Automotive and Robotics applications including sensor fusion and autonomous systems and AI-driven platforms

Required Experience & Skills:

• Semiconductor Industry: 10+ years of embedded development experience with focus on both hardware and software
• Hands-on design experience with at least one of the following:
  • Ethernet PHYs
  • Ethernet switches
  • PCIe 
• Ability to diagnose and debug problems effectively
• Excellent team working abilities across global teams and confident interacting with engineers through to executive management
• Automotive experience at Tier 1, Tier 2 or OEM level
• B.S. or M.S. in Electrical Engineering

Nice to Have (The "Competitive Advantage"):

• Good understanding of embedded software drivers
• Understanding and experience of OSI network layers 2+
• Experience of Ethernet switches and understanding of IEEE802.1 protocols
• Experience with TSN protocols
• Experience with PCIe protocols and topologies
• Experience covering high speed PCB board design, layout and routing constraints
• Experience with ROS / ROS2, Isaac Sim, CUDA, etc

Personal Skills:

• Excellent communication/documentation skills
• Attention to details
• Collaboration across multidisciplinary and international teams
• Self-motivated and able to work effectively both independently and in a team

What You Can Expect From Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $180,000 - $240,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, as well as eligibility for performance bonuses, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)

#LI-Hybrid

Role 

We are looking for a Principal Site Reliability Engineer to join our Infrastructure services and architecture team. This role is hybrid 3 days a week onsite in San Jose, CA, or can be remote reporting to the Senior Manager, Cloud Operations. As a lead engineer, you will leverage deep expertise in IaC/CaC, Linux virtualization, and physical hardware management to drive our infrastructure forward. You will oversee networking services and general software engineering to ensure our systems remain scalable, resilient, and high-performing.

What you’ll do (Role Expectations)

• Mentor junior engineers and lead high-impact infrastructure projects
• Support business operations by responding to alerts and triaging systems to restore mission-critical capabilities
• Ensure the reliability and performance of all customer-facing services
• Design, document, and build technical solutions that align with evolving organizational needs
• Support Agile processes to maintain high velocity and a collaborative environment

Who You Are (Success Profile)

• You possess deep expertise in Kubernetes management and deployment, ensuring containerized environments are optimized and secure.
• You are a champion for Infrastructure/Configuration as Code, maintaining a strict IaC/CaC mindset in every solution you build.
• You operate with a security-first focus, embedding protection and compliance into the foundation of the infrastructure.
• You bring a "go-getter" attitude, proactively identifying problem areas and proposing innovative solutions.
• You are highly proficient in CI/CD pipelines and believe that automated testing is non-negotiable for stable releases.

What We’re Looking for (Minimum Qualifications)

• Expert-level proficiency with Kubernetes
• Deep professional experience with Terraform and Ansible
• Expert-level programming skills in Python or Go
• Hands-on experience with Enterprise Linux distributions such as Rocky, Red Hat, or Alma
• Proven experience using Git within a structured SDLC
• U.S. citizenship due to the nature of the customers assigned to this role

What Will Make You Stand Out (Preferred Qualifications)

• Deep knowledge of Linux Hypervisors, including OpenStack, Proxmox, libvirt, or QEMU
• Technical experience working with FreeBSD
• Familiarity with Identity Access Management tools like HashiCorp Vault, LDAP, or OIDC

#LI-SanJose #LI-Remote #LI-JG1

Role Overview

Astera Labs is seeking a Principal Product Applications Engineer to join our Aries PCIe Retimer team and serve as a critical technical bridge between our customers and engineering organization. As AI infrastructure demands explode, our Aries Smart Retimers are enabling the high-speed, low-latency PCIe connectivity that powers the world's most advanced data centers—and you'll be at the center of that growth.

In this high-impact role, you'll work directly with hyperscalers, OEMs, and system builders to drive successful adoption of our Aries PCIe products. You'll combine deep technical expertise with customer-facing skills to solve complex system-level challenges, create compelling technical documentation, and influence product direction based on real-world customer needs. This is an opportunity to shape how next-generation AI and cloud infrastructure connects and scales.

You'll collaborate cross-functionally with design engineering, validation, sales, and marketing teams while building strong relationships with customers who are defining the future of computing. If you thrive at the intersection of cutting-edge silicon and customer success, this role offers exceptional visibility and impact.

Key Responsibilities

Customer Technical Engagement

• Serve as the primary technical resource for customers during pre-sales evaluation and post-sales deployment of Aries PCIe retimers
• Deliver technical presentations, product training, and demonstrations to customer engineering teams
• Build trusted advisor relationships with key accounts and drive product adoption

System-Level Debug & Validation Support

• Lead root cause analysis and debugging of complex PCIe signal integrity and protocol issues in customer systems
• Support customer lab bring-up, characterization, and validation activities
• Develop and execute test plans to reproduce and resolve customer-reported issues

Technical Documentation & Enablement

• Create application notes, reference designs, and best practices guides for PCIe system implementation
• Develop collateral that accelerates customer time-to-deployment
• Contribute to product documentation including datasheets and user guides

Cross-Functional Collaboration

• Partner with product management and engineering to translate customer feedback into product requirements
• Support sales teams with technical expertise during customer engagements
• Represent the voice of the customer in internal roadmap and feature discussions

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in applications engineering, technical support, or system engineering roles
• Strong understanding of PCIe architecture, protocol, and electrical specifications (Gen4/Gen5/Gen6)
• Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BERT tools
• Experience debugging high-speed serial interfaces at both the physical and protocol layers
• Excellent written and verbal communication skills with ability to explain complex technical concepts
• Develop and modify firmware using C to implement features, optimize performance, and resolve technical issues
• Travel to customer sites worldwide to provide on-site technical support, conduct system integration, and drive issue resolution

Preferred Qualifications

• Experience with PCIe retimers, redrivers, or similar connectivity components
• Familiarity with server, storage, or GPU system architectures
• Background in signal integrity analysis and simulation tools
• Scripting proficiency (Python, TCL) for test automation and data analysis
• Prior experience working directly with hyperscale or enterprise data center customers
• Track record of creating high-quality technical documentation and application notes

Salary range is $158,400 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Overview: 

The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance.

Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs.

Basic Qualifications:

•  Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
•  ≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
•  Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead
• Required experience
• Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet
• Strong problem-solving skills, ability to solve problems independently
• Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

•  Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
•  Familiarity with PCIe or Ethernet especially Electrical Compliance sections
•  Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
•  Working knowledge of C or C++ for embedded FW
•  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
•  Working knowledge of common serial data specifications such as I2C, SPI, etc
•  Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
•  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is USD 203,00 - USD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Overview

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 10 + years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, executing validation plans for complex SoC designs. 

Required Experience:

• Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet.
• Familiarity with Electrical Compliance section of PCIe Base Spec and CEM Spec
• Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ, CDR, etc and concepts such as PAM4
• Experience in PRBS testing and optimization of high-speed PCIe data links over short, med, and long channels
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops
• Hands-on experience with signal integrity, especially as it relates to PCIe testing, Channel Loss budgeting, and de-embedding
• Working knowledge of C or C++ for embedded FW, experience using git-based version control such as github
• Familiarity with PCIe standards and both NRZ and PAM-4 signaling
• Working knowledge of common serial data specifications such as I2C, SPI, etc
• Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is $185,000 USD - $230,000 USD. Your base salary will be determined based on your experience and the pay of employees in similar positions. 

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Education and Experience Requirements

• Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 8-12 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Desired Qualifications

• Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
• Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
• Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
• Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
• Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
• Experience with PAM4 SerDes validation (200G/100G/50G)
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
• Knowledge of Signal Integrity simulation tools
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Job Description

We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
• Familiar with high-speed load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with using Advantest 93k ATE platform.
• Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.
• Experience in running External loopback at wafer sort.
• Familiarity with modern databases

Role Overview
Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.

Key Responsibilities

• Architecture & Technical Leadership
• Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines
• Establish architectural standards and best practices that scale across the design organization
• Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area
• Design Execution & Ownership
• Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up
• Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies
• Own accountability for design quality, schedule, and successful production delivery
• Cross-Functional Collaboration
• Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues
• Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up
• Work with firmware and software teams to optimize hardware-software interfaces
• Mentorship & Process Excellence
• Mentor and develop junior and senior engineers, elevating team technical capabilities
• Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure
• Contribute to organizational knowledge sharing and technical reviews

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure
• Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows
• Track record of delivering multiple high-performance designs to production

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)
• Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems
• Proven contributions to design methodology, CAD automation, or infrastructure improvements
• Experience leading technical teams or driving cross-functional initiatives in data center environments

Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion.
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic qualifications 

• Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Required experience 

• Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget. Experience with PAM4 SerDes is a huge bonus!
• Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
• Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.

The base salary range is $205,000.00 USD – $255,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

Overview: 

As a Senior Principal Validation Engineer, you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets.

You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction.

This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives before production.

Key Responsibilities:

• Design, develop, and execute validation plans. Own end‑to‑end post‑silicon characterization and validation strategies, translating product requirements into measurable test objectives, pass/fail criteria, and schedules.
• Drive design reviews and specification alignment. Participate in architecture and design‑spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.
• Lead hands‑on test execution and bring‑up. Perform silicon bring‑up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time‑to‑data.
• Build and maintain automation frameworks. Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed‑signal test benches.
• Debug and optimize system performance. Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs.
• Root‑cause cross‑domain failures. Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system‑level tests; coordinate with design, package, and firmware teams to implement fixes.
• Collaborate with cross‑functional teams. Work closely with mixed‑signal design, firmware, system engineering, and manufacturing to deliver detailed results, root‑cause analyses, optimization recommendations, and formal validation/compliance reports.
• Document findings and improve methodologies. Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base.
• Develop test software and platform integrations. Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites.
• Measure and communicate impact. Define key validation metrics, track coverage and defect trends, and present data‑driven conclusions to stakeholders to influence product direction and release decisions.

Basic Qualifications

• Education — Bachelor of Science in Electrical Engineering required; Master’s degree preferred to demonstrate advanced technical depth and specialization.
• Experience — At least ten years of hands‑on experience in mixed‑signal, high‑speed lab environments, executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real‑time oscilloscopes, sampling scopes, TDRs, and VNAs.
• Software Skills — Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.
• Retimer Expertise — Practical experience bringing up and debugging retimers, including equalization tuning, pass‑through operation, clocking strategies, and reset and link sequencing.
• High‑Speed Signaling Knowledge — Deep understanding of NRZ and PAM4 architectures and the ability to investigate jitter sources, CDR and PLL behavior, equalization techniques such as DFE, CTLE, and FFE, as well as crosstalk and power integrity issues.
• Post‑Silicon Validation — Proven track record in post‑silicon validation and bring‑up of high‑speed PHYs or retimers, with experience developing characterization flows and validating silicon against specifications.
• Circuit Block Familiarity — Solid working knowledge of key high‑speed building blocks including PLLs, CTLE, DFE, transmitter equalization, and PAM4 signaling fundamentals.
• Analytical Problem Solving — Exceptional troubleshooting skills with the ability to isolate and narrow complex, multi‑layer failures across analog, digital, firmware, and package domains.
• Communication — Excellent written and verbal communication skills for clear documentation of findings, presentation of root cause analyses, and collaboration with cross‑functional teams.

Preferred Experience:

• Mixed‑signal system testing and validation — Demonstrated experience in end‑to‑end mixed‑signal system testing, characterization, validation, and compliance activities, including developing test plans, executing characterization flows, and producing formal compliance reports.
• Signal integrity instrumentation and techniques — Hands‑on proficiency with signal integrity test equipment and methodologies, including BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, and advanced probing techniques for channel and package analysis.
• Ethernet standards familiarity — Working knowledge of IEEE 802.3 family standards and practical experience validating Ethernet PHYs, link training, autonegotiation, and compliance testing across relevant speeds and media types.
• Serial protocol expertise — Practical understanding of common serial interfaces such as I2C, I3C, SPI, UART, and other control/status buses used for device bring‑up, firmware interaction, and system integration.
• Cross‑discipline collaboration — Proven ability to translate SI/PI simulation results into testable lab plans, collaborate with design and firmware teams to close the loop on issues, and document findings that drive design or process improvements.

Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.

The base salary range is USD 205,00 - USD 255,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite.

Basic Qualifications

• Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.
• 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
• Have a proven track record with defining hardware system constraints and high-speed technology roadmaps.
• Cross-functional design mentality with the electrical design community to develop systems.
• Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.
• Proven track record solving problems independently, preferably as a tech lead.
• Entrepreneurial, open-minded behavior, and can-do attitude.
• Authorized to work in the US and start immediately.

Required Experience

• Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects
• 2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets
• EM modeling of BGA and connector structures
• High-speed SERDES channel simulation, and equalization
• PI simulations with Ansys/Cadence toolsets
• Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
• Working knowledge of PCB fabrication limits and trade-offs
• Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections.
• Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome.

Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we're revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution.

In this highly strategic role, you'll serve as Astera Labs' technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You'll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers exceptional scope for impact—your work will directly enable the rack-scale AI infrastructure that's transforming cloud computing and enterprise data centers worldwide.

Key Responsibilities

• Strategic Leadership & Methodology Development
• Define and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols
• Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality
• Represent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verification
• Drive cross-functional collaboration to influence technical direction across the organization
• Technical Execution & Innovation
• Develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications
• Identify key logic components and critical micro-architectural properties essential for ensuring design correctness
• Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs
• Apply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth
• Develop and maintain scripts to enhance FV productivity and streamline verification processes
• Team Development & Cross-Functional Partnership
• Mentor Principal and Lead Engineers across global sites in advanced formal verification techniques
• Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels
• Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback
• Prepare and deliver customer meetings and executive presentations with minimal supervision

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
• 15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization
• Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification
• Advanced scripting abilities with Python or Perl for automation and productivity enhancement
• Proven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision
• Strong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus
• Entrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards

Preferred Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification
• Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold
• Experience with both bug hunting and static proof verification techniques
• Familiarity with automating formal verification workflows within a CI/CD environment
• Deep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink
• Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)
• Patents or publications in formal verification or hardware verification methodologies
• Track record of recruiting, mentoring, and developing formal verification talent across distributed teams

Salary range is $230,000 to $285,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.

Key Responsibilities

• Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
• Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
• Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
• Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
• Work with RTL designers to troubleshoot and resolve design issues.
• Drive verification strategy and methodology for SoCs in server and networking applications.

Required Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred).
• 8+ years of experience in SoC verification, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
• Familiarity with verification of switching architectures, including packet processing and forwarding engines.
• Excellent communication skills and ability to work independently with minimal supervision.

Preferred Qualifications

• Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
• Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
• Knowledge of Ethernet/PCIe switching and central buffer architectures.
• Experience with emulation platforms and hardware-software co-verification

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description:

As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products.  You will be working on projects from conception to the final production stage at contract manufacturer.

The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices.  At the same time we welcome candidates with deep experience in smaller areas with the desire to learn.  Depending on your experience, you may be focusing on design/validation or automation/manufacturing.

Key Responsibilities

• Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.
• Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product
• Bring-up newly manufactured boards and develop the first level of software.
• Isolate and perform root-cause analysis of reported failures
• Support new platform software and hardware features
• Coordinate with the hardware engineering team on bring-up schedules and feature delivery
• Participate proactively in design discussions, design review, and project management
• Work independently as well as in team roles, mentor younger team members

Basic Qualifications/Required Experience

• Bachelor’s in CS/CE or equivalent experience.
• 8+ years of Experience in subset of diagnostic, hardware bring-up, test or manufacturing automation
• Knowledge of modern software development 
• Proficiency in Python, C/C++

Preferred experience

• Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing
• Ability to read schematic/layout
• System debug experience
• Embedded programming and good knowledge of OS internals (Linux/Unix)
• Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.
• Experience with DDR5

The base salary range is $203,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job Description: As a Digital Designer in the DSP SerDes team, you will join a pivotal project to develop advanced high speed SerDes wireline and optical transceivers for AI systems. 

Basic Qualifications:

• Hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5-10 years of experience in digital design for high-speed DSP data path.
• Be proficient in coding System Verilog for complex design blocks.
• Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time.
• Have experience taking design blocks through the full design cycle, from micro-architecture to tapeout.
• Have experience with timing fixes, area and power optimizations, and resolving silicon issues.

Required Experience:

• Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery.
• Code and deliver high-quality RTL to the PD and DV teams.
• Collaborate with the DSP Architecture team to define new features and suggest optimizations for power, latency, and performance.
• Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations.
• Partner with the DV team to root-cause and fix design bugs.

Preferred Experience:

• Experience in digital design for high speed data path in 100G+ PAM4 DSP SerDes
• Experience in designing PAM4 DSP blocks for FFE, DFE, MLSD, and digital timing recovery.

Role Overview

Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

Overview

Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
• Work closely with post-silicon teams to facilitate silicon bring-up and debug.
• Mentor junior engineers to develop their technical skills and expertise.
• Actively contribute to the development and improvement of silicon development processes.
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success.

Required Qualifications:

Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Architecture definition and micro-architecture development
• RTL coding, functional simulation, and synthesis
• Timing closure and gate-level simulation (GLS)
• Design for test (DFT) implementation
• Production experience with advanced CMOS nodes (≤7nm)

Protocols & Integration:

• Deep expertise in at least one high-speed protocol—PCIe , Ethernet, Infiniband, DDR, or similar
• Third-party IP integration and verification.
• Block-level design ownership from architecture through GDS

Tools & Methodologies:

• Proficiency with Cadence and/or Synopsys digital design flows
• Familiarity with UVM-based verification methodologies.
• Silicon bring-up, debug, and failure analysis expertise

Professional Attributes:

• Strong work ethic with the ability to balance multiple priorities in a dynamic environment
• Excellent communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements
• Customer-focused mindset with ability to translate business needs into technical excellence

Preferred Qualifications

• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality

As a Principal Electronics Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. 

Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products.

Key Responsibilities:

• Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.
• Develop comprehensive hardware electrical validation plans using correct test methods and processes.
• Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.
• Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.   
• Rework components on the PCBAs to unblock debugging activities.
• Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.
• Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.
• Support the new designs using knowledge of existing products to de-risk new features and requirements.
• Self-informed of new industry test standards and equipment to introduce modern testing methodologies.
• Specify test equipment, develop test fixtures, help improve hardware lab functions.

Required Skills:

• Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug
• Bachelor degree in EE with 10+ years of experience in hardware test or design
• Define/refine hardware test methodologies and identify appropriate test equipment
• Expert understanding of design and test for power regulators, PDNs, Bode, clock gens
• Ability to produce test description from a schematic design, and execute and document results
• Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM
• Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.
• Automating lab equipment to optimize test processes, Python preferred

Preferred Skills:

• Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.
• EMI/EMC compliance
• Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.
• PLM, Arena or equivalent
• Understanding of the ASIC/silicon product development process

Base salary range is $185,000 USD-$230,000 USD, and will be determined based on the candidate's capabilities and employees in similar positions.

The Role and Its Impact 

Our Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications, providing critical signal conditioning for high-speed connectivity in AI infrastructure. The firmware you develop will manage complex system and IP integration, SERDES configuration, link training sequences, and diagnostic capabilities for these devices deployed in data centers worldwide. 

As a Principal Engineer in our Signal Connectivity Engineering group, you'll contribute to firmware that directly impacts the performance and reliability of Ethernet connectivity solutions powering AI infrastructure globally. Working closely with the SoC software, transceiver module software, and system validation teams, you'll take ownership of feature development and rollout, software integration testing, and customer debug activities. Working at the intersection of embedded systems and high-speed Ethernet connectivity, you'll collaborate closely to bring these systems to production. 

We're a startup, and this role reflects that reality. You'll have responsibilities spanning firmware development, customer engagement, debug and validation support, and cross-functional coordination. We're looking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. 

This position offers strong mentorship opportunities as you work alongside experienced engineers and help bring products from development through customer deployment. 

Level is negotiable based on experience and qualifications. 

Location 

This is an on-site position based in our San Jose, CA office. 

Core Responsibilities 

Firmware Development & Debug 

• Develop and maintain embedded firmware for Ethernet retimers and gearboxes, from low-level hardware abstraction through customer-facing APIs 
• Drive Layer 1 PHY and SERDES debug activities, including link bring-up issues, signal integrity problems, and interoperability failures 
• Support complex IP integration efforts across multiple subsystems within the SoC 
• Implement and optimize link training sequences, equalization tuning, and diagnostic features 
• Assist with software quality gates and validation criteria at each development phase 

Product Rollout & Customer Integration 

• Partner with the software lead to drive product rollout activities from development through production deployment 
• Support customer integration efforts through firmware customization, debug assistance, and technical guidance 
• Investigate field-reported issues and coordinate resolution with internal teams 
• Develop and maintain SDK/API interfaces that enable customer platform integration 

Cross-Functional Collaboration 

• Work extensively with digital SoC teams to understand hardware behavior, register interfaces, and IP integration requirements 
• Collaborate with field applications engineers to support customer bring-up and resolve deployment issues 
• Partner with platform applications teams to ensure firmware meets system-level requirements 
• Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases 
• Provide regular project updates on progress, risks, dependencies, and technical challenges 

What You Bring 

Required Qualifications: 

• BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field 
• 10+ years of embedded C/C++ firmware development in resource-constrained environments 
• Deep understanding of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware design 
• Experience with Layer 1 PHY firmware, SERDES bring-up, or SDK/API development for networking devices 
• Strong proficiency with Linux development tools: gcc/clang, make, bash scripting, gdb, and git 
• Excellent verbal and written communication skills; ability to explain complex technical concepts clearly 
• Demonstrated problem-solving ability and systematic debugging approach on real hardware 
• Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment 

Highly Valued Skills: 

• Experience with PMA, FEC, or related PHY-layer subsystems beyond the PMD/SERDES 
• Familiarity with NIC or switch management software, for system test purposes 
• Exposure to SAI (Switch Abstraction Interface) or OpenBMC 
• Experience with Python for test automation, data analysis, or general scripting 
• Hands-on experience building and maintaining Jenkins CI/CD pipelines and automated test infrastructure 
• Background in retimer or gearbox firmware/API, active electrical cables, or high-speed Ethernet connectivity 
• Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, BERT, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar 
• Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin 
• Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments 
• Experience with RTOS, device drivers, or coroutines 
• Prior technical lead, mentorship, or team lead experience 

Compensation 

Salary range is $185,000 USD - $203,000 USD depending on experience, level, and business need. This role will include a discretionary bonus, competitive equity package, comprehensive health/dental/vision coverage, professional development opportunities, and a culture that values technical excellence, collaboration, and innovation.

We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation.  The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues.  The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.

Basic qualifications:

• Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.
• Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required experience:

• Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols.
• High level of proficiency in System Verilog and verification environments.
• Experience understanding software and hardware co-simulation limitations and debug methods.
• Experience in programming and scripting languages (like perl/python/C).
• Currently based locally or open to relocation.

Preferred experience:

• Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.
• Experience in modeling for emulation and prototyping, and/or non-UVM environments

Role Objective

As the gatekeeper of IP Management, Methodology and Quality at Astera Labs, you will lead the strategic development of our AI-powered IP Lifecycle Management and IP Quality Assurance Platform. You won't just run tools; you will architect a scalable, user-friendly system that serves as the foundation for our "AI-first" IP ecosystem. Your mission is to ensure every IP, whether internal or external is easily accessible, physically, logically, and structurally "SOC-ready," preventing late-stage integration breaks that delay tape-outs. Our vision is to revolutionize IP Management and Quality Assurance with an AI-first approach.

The candidate will be responsible for developing the platform, auditing and qualifying internal and external IP (Hard/Soft Macros, PHYs, Memories and standard cells libraries among other IPs). The IPLM and IPQA tools will scale to cover SOC QA and be a key element of the tape out sign-out requirements. The successful candidate will have the right expertise to run all EDA tools, understand the results, challenge the false pass scenarios, and dig into the root cause of real errors. They will work with the vendors or with our internal IP teams to solve the issues.

They will be responsible for ensuring that all IP deliveries are integrable, timing-clean, and manufacturable, preventing "late-stage" SOC breaks caused by inconsistent IP views or structural violations. IPQA will cover all aspects of the design flow starting from Architecture coherence, PPA evaluation, Front-End integration, SDC, RDC, DFT, PD and PDV, Packaging, ESD, Waivers, IP-XACT; and be scalable from the technology foundations, FinFet and Gate-All-Around transistors’ properties, DK/PDK integrity and rule decks from foundries, Standard Cells, Memories, IP, Subsystems and SOC Quality.

Technical Responsibilities

• AI-Driven Automation: Architect and Lead the integration of agentic AI workflows into the IPLM and IPQA platform to automate IP Management, root-cause analysis of false pass scenarios and self-heal real issues.
• Chiplet Readiness: Verify IP compliance with high-speed and high-bandwidth interface standards for heterogeneous integration.
• Cross-View Consistency: Architect automated audits for logical-to-physical consistency across RTL, Liberty, LEF, GDSII, and CDL views, focusing on pin-naming, bus-integrity, and functionality.
• Physical & Sign-off Audits: Perform independent LVS, DRC, and Antenna signoffs using native runsets for 5nm/3nm and beyond nodes.
• Structural & DFT Verification: Validate DFT requirements, including scan-chain integrity, MBIST handshakes, and fault-coverage transparency.
• Power & Timing Integrity: Audit Power Domain (UPF/CPF) consistency and conduct deep-dive Liberty (.lib) audits to identify missing timing arcs or non-monotonic lookup tables. Audit IR-drop/EM (Electromigration) reports to ensure the IP won't cause localized power grid failures.
• Waiver Management: Develop rigorous, automated Waiver Audit Protocol to ensure that provider-cleared violations do not violate Astera Labs' internal sign-off deck requirements.
• Lessons learned from release to release, from generation to generation need to be tracked and checked. Responsible for making sure releases are complete; patches are integrated. Constraints are updated, and documentation reflects the updates including PPA impact.

Required Skills & Expertise

• IP & EDA Expert: Mastery of the full sign-off suite: PrimeTime, Fusion Compiler, Genus, Calibre, Innovus, IC Compiler, SpyGlass, Tessent, Liberate (/MX), PrimeSim. Cross-Tool Consistency expertise is a must.
• Advanced Scripting for Information Systems: Expert in Tcl for tool manipulation and Python for building AI-wrapper layers. Familiarity with SystemVerilog.
• Domain Depth: Deep understanding of FinFET/Gate-All-Around (GAA) properties, Electromigration (EM), and ESD rules. Deep knowledge of Liberty modeling and LEF/DEF physical formats.
• QA Philosophy: A "Detective" mindset with the ability to look past a "green" or “red” report to find false errors and rootcause real ones.
• Management skills: Ability to work with design teams and IP vendors to solve issues in a timely manner.

The base salary range is $175,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions

Job Description

The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• Minimum 8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).
• Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience developing embedded firmware for PCIe products.
• MQX RTOS or ThreadX Development or enablement.
• High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
• High level of proficiency in Python for automating pre-processors/post-processors and FW QC.
• Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.
• Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).
• Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces
• Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc

Preferred Experience

• Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC)
• Experience with industry forums and collaboration workgroups such as OCP and OpenBMC

The base salary range is $203,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description

We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
  required, and a Maser’s is preferred.
• ≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in US and start immediately.

Required Experience

• Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
  environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
  generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
  writing assertions, cover properties and analyzing coverage data
• Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.
• Must have prior experience on verification with firmware to control and configure the SerDes and related components.

Preferred Experience

• SW debugging for Mix-Signal based designs.
• Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.
• Experience with FPGA-based verification/emulation.

Role Overview 

Astera Labs is seeking an experienced and hands-on Principal Optical Reliability Engineer to drive reliability strategy across our cutting-edge portfolio of connectivity products, with a focus on silicon photonics and optical components. As AI infrastructure demands unprecedented bandwidth and performance, this role is critical to ensuring our products deliver exceptional reliability through end-of-life. 

You will lead reliability initiatives and serve as an internal consultant, defining and implementing methodologies across component, chiplet, photonic, and board-level products. This is a high-impact position where you'll partner closely with design, product/test engineering, quality, and manufacturing teams to embed reliability-aware principles. 

Key Responsibilities 

• Reliability Strategy & Methodology 
  • Develop and implement comprehensive design reliability methodologies for semiconductor circuits and optical systems, including pre-qualification, production release, ongoing reliability monitoring (ORM), and soft error evaluation 
  • Lead the application of advanced reliability modeling techniques to analyze trade-offs between performance and long-term product reliability 
  • Establish and refine usage models to guide design-phase reliability assessments and integrate learning from manufacturing and field return data in post-silicon validation 
• Failure Analysis & Root Cause 
  • Apply expert knowledge of semiconductor and optical reliability failure mechanisms, including Electrostatic Discharge (ESD), Latch-Up (LU), Soft Errors, Gate Oxide Time-Dependent Dielectric Breakdown (GOX TDDB), Electromigration, Device Aging, laser degradation, and photodetector wear-out 
  • Utilize a hands-on approach to comprehend silicon, photonic, and package-level failure mechanisms, collaborating seamlessly with internal and external teams to drive root cause analysis and resolution 
  • Evaluate qualification results for new product introductions and drive continuous improvement in design-for-reliability tools, processes, and organizational knowledge 
• Cross-Functional Collaboration & Vendor Management 
  • Collaborate across design, product engineering, manufacturing, and reliability teams to capture and institutionalize best practices that improve product robustness and reduce DPPM 
  • Serve as a subject matter expert helping design engineers incorporate reliability-aware design principles early in development 
  • Work closely with vendors to review and interpret component specifications, reliability data, and qualification reports, including Mean Time Between Failures (MTBF), failure-rate predictions, derating analysis, and stress test results 

Basic Qualifications 

• Master's degree in Electrical Engineering, Applied Physics, Photonics, or a related field 
• 8+ years of experience in semiconductor reliability, with direct experience in silicon photonics, optical components, or optoelectronic device reliability 
• Strong background in semiconductor physics, device modeling, and reliability verification techniques including statistical and probability techniques 
• Deep knowledge of advanced packaging technologies, including 2.5D, 3D, and chiplet architectures, as well as module and system board reliability 
• Working knowledge of electronic components/devices and their failure modes and mechanisms 
• Proven leadership in driving complex technical issues to closure across global, cross-functional teams 

Preferred Qualifications 

• PhD in Electrical Engineering, Applied Physics, or Photonics 
• Experience with silicon photonics reliability, including laser aging, photodetector degradation, and fiber coupling reliability 
• Knowledge of high-performance compute and AI cloud infrastructure, as well as switch/network interfaces 
• Experience with PCBA (printed circuit board assembly) design, fabrication, and validation testing 
• Strong experience in product reliability in the context of mechanical, thermal, and electrical stresses for modules and board assemblies 
• Excellent communication skills with the ability to articulate technical concepts clearly across all levels of the organization 
• Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

 Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

Role Overview

As a Principal Package Thermal & Mechanical Engineer at Astera Labs, you will serve as a technical leader driving the development and modeling of advanced IC packaging solutions that enable next-generation AI and high-performance connectivity systems.

In this highly visible role, you will define and execute thermal and mechanical modeling strategies across the chip–package–board system, influencing package architecture, material selection, and reliability design. You will partner closely with package design, SIPI, silicon, system, and manufacturing teams to ensure robust thermal/mechanical performance and first-pass success.

You will also drive modeling methodologies, correlation strategies, and best-known methods (BKMs), while engaging directly with customers to translate complex simulation insights into actionable system-level solutions.

Key Responsibilities

• Thermal & Mechanical Modeling Leadership
• Define and drive thermal and mechanical modeling strategies for advanced packages (FCBGA, FCCSP, multi-die, and chiplet-based architectures)
• Perform detailed thermal simulations including steady-state and transient heat transfer (conduction, convection, and interface resistances such as TIM1/TIM2)
• Develop and deploy compact thermal models (CTM), reduced-order models (ROM), and DELPHI-based models for system-level integration
• Analyze power density, hotspot behavior, and package-to-system thermal interactions across air and liquid cooling environments
• Perform thermo-mechanical stress/strain analysis including CTE mismatch, viscoelastic material behavior, and deformation
• Predict package warpage across process and use conditions (reflow, underfill cure, board attach, field operation)
• Model solder joint reliability and fatigue using industry standard models
• Package Architecture & Thermal Design Strategy
• Drive package design decisions including material selection (EMC, substrate, TIM, lid/heat spreader), thermal path optimization, and early-stage architecture definition across air and liquid cooling solutions (air, cold plate, CPO/CPC)
• Conduct DOE, sensitivity studies, and worst-case analysis to guide tradeoffs across performance, cost, reliability, and manufacturability
• System Co-Design & Automation
• Partner cross-functionally to drive chip–package–board co-design and resolve system-level thermal/mechanical challenges, including system integration constraints
• Serve as a technical interface for customers and internal teams, translating modeling results into actionable insights and leading design reviews and issue resolution
• Develop and scale modeling methodologies, workflows, and BKMs; mentor engineers and improve efficiency through automation and scripting (Python, MATLAB)

Basic Qualifications

• M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field
• 8+ years of experience in semiconductor packaging with strong focus on thermal and mechanical modeling
• Deep expertise in thermal modeling and simulation, including steady-state and transient analysis, compact thermal modeling (CTM), DELPHI methodology, and system-level thermal integration using tools such as ANSYS Icepak, Flotherm, or equivalent
• Deep expertise in thermo-mechanical modeling and FEA simulation, including stress/strain analysis, warpage prediction, and reliability modeling (BLR/CLR), using tools such as ANSYS Mechanical, or equivalent
• Proven ability to correlate simulation results with lab measurements
• Experience influencing package design and delivering solutions to production
• Strong cross-functional collaboration across package design, SIPI, system, and manufacturing teams

Preferred Qualifications

• Experience with high-power AI / HPC packages and large FCBGA (>50mm)
• Familiarity with advanced packaging technologies:2.5D / 3D integration, Chiplet, CPO/CPC
• Experience with system-level cooling solutions: Liquid cooling, cold plates, immersion cooling
• Knowledge of JEDEC standards and reliability qualification methodologies
• Experience working with OSATs and substrate vendors on thermal/mechanical design optimization
• Proficiency in scripting (Python, MATLAB) for modeling automation
• Exposure to multi-physics coupling (electrical–thermal–mechanical interactions)

 The base salary range is $185,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.

Key Responsibilities

• Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
• Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
• Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
• Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• SystemVerilog/Verilog familiarity.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Principal Power and Board Design Engineer 

Overview:
We are seeking a highly skilled and experienced Power and Board Design Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.

Key Responsibilities:

• Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.

• Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance mismatches.

• Develop and implement board-level designs, to meet electrical and mechanical requirements with a deep understanding of PCB layout rules and constraints.

• Implement thermal solutions to maintain optimal operating temperatures for components.

• Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also will be asked to do the same evaluation on overall system level design components.

• Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.

• Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.

• Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.

• Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.

Qualifications:

• Education: Bachelor’s or Master’s degree in electrical engineering or a related field.

• Experience: 8-10 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.

• Technical Skills:

  • Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.

  • Strong understanding of power integrity principles and techniques.

  • Experience with power component selection and vendor collaboration.

  • Hands-on experience with debugging power-related issues using lab equipment.

• Soft Skills:

  • Excellent problem-solving and analytical skills.

  • Strong communication and teamwork abilities.

  • Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Experience with high-speed interfaces such as PCIe, DDR, and USB.

• Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.

• Familiarity with Design for Manufacturability (DFM) considerations.

• Experience in thermal management and reliability analysis.

Why Join Us:

• Work on cutting-edge ASIC designs in a collaborative and innovative environment.

• Opportunity to influence power design strategies and contribute to product success.

• Access to state-of-the-art tools and resources to enhance your skills and career growth.

If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.

Base pay range for this role is $209,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role 

We are looking for a Principal Product Manager, Cloud Reliability and Cloud Operations to join our Product Management department. This is a hybrid role based in San Jose, CA reporting to Director, Product Management. You will be a hands-on leader responsible for driving reliability and scalability and Cloud Operations initiatives for the ZIA and ZPA cloud platforms. This is a high-visibility role where you will drive critical projects to scale our architecture to 1 trillion transactions and beyond, ensuring our Zero Trust Exchange remains the global leader in cloud security.

What you’ll do (Role Expectations)

• Implement the ZIA/ZPA RAS roadmap by defining problem statements, collecting requirements, and managing critical programs across the cloud lifecycle
• Lead pre- and post-sales customer engagements regarding cloud resilience, building trust through transparent roadmap discussions and RCA reviews
• Monitor ongoing cloud incidents and escalations to identify recurring themes and direct cross-functional teams on comprehensive improvement plans
• Serve as the primary subject matter expert for field teams, providing technical education and support for all RAS-related inquiries
• Collaborate with cloud architects and software engineers to ensure the platform balances rapid growth with extreme stability

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.
• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.
• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.
• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.
• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• 12+ years of industry experience in Cloud Engineering, SRE, DevOps, or Technical Product Management
• Bachelor’s degree in a technical field or equivalent professional experience
• Deep technical expertise in network security and protocols including proxies, firewalls, TLS, PKI, and HTTP/S
• Proven experience with cloud-native services at hyper-scalers or major SaaS providers
• Comprehensive understanding of cloud architecture and resilience patterns such as clustering, cascading failure prevention, and observability principles

What Will Make You Stand Out (Preferred Qualifications)

• Expertise in translating complex customer needs into actionable product requirements and internal conviction
• Strong data analytics skills with the ability to define hypotheses, analyze large datasets, and communicate results to stakeholders
• Direct hands-on experience with Zscaler products including ZIA, ZPA, or ZDX

#LI-Hybrid 

#LI-CM3

Archer is an aerospace company based in San Jose, California, building an all-electric vertical takeoff and landing aircraft with a mission to advance the benefits of sustainable air mobility. We are designing, manufacturing, and operating an all-electric aircraft that can carry four passengers while producing minimal noise.

Our sights are set high and our problems are hard, and we believe that diversity in the workplace is what makes us smarter, drives better insights, and will ultimately lift us all to success. We are dedicated to cultivating an equitable and inclusive environment that embraces our differences, and supports and celebrates all of our team members.

What you’ll do:

• Act as a Subject Matter Expert (SME) for all aspects of System, Software, Airborne Electronic Hardware (AEH) and Cybersecurity Design Assurance processes for Archer internal development and for Suppliers.
• Review and approve Software/AEH life-cycle data for Archer internal development and for Suppliers as company DER, if delegated.
• Execute System Design Assurance Reviews for Archer internal system development according to the established system processes and tools for compliance with ARP4754A/ARP4761 and support the Certification Authorities reviews for ARP4754A.
• Execute Supplier Oversight and Design Assurance Company Reviews as SME for Systems, Software and AEH developments according to Archer established process for compliance with ARP4754A/ARP4761, DO-178C and supplements, DO-254 and other certification regulations. 
• Support the approval of Cybersecurity processes with the Certification Authorities for Archer products.
• Support the generation and independent reviews of Archer System, Software/AEH and Cybersecurity development and verification processes, as needed.
• Contribute to the continuous improvement of the Archer System, Software and AEH processes, with focus on compliance with ARP4754A/ARP4761, DO-254 DO-178C and supplements.
• Interface with FAA DERs and Certification Authorities for coordination, execution and follow-up of systems, software and AEH compliance reviews.
• Maintain and control the issues found in all System/Software/AEH design assurance activities until resolution.

What you need:

• 15+ years of experience in System and Software/AEH Design Assurance activities for aerospace standards.
• At least a BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Experience with full lifecycle safety critical systems, software/AEH complying with design assurance standards like ARP4754A/B, ARP4761, DO-254 and DO-178C with supplements.
• SW/AEH DER authorization for Part 23 DAL B.
• Experience with multiple systems and software/AEH environments and tools.
• Excellent organizational and communication skills.
• Experience in fast-paced, demanding work environments.
• Experience with agile/lean methodologies.

Bonus qualifications

• Experience with Tool Qualification following DO-330.
• Experience with Model Based Development and Verification following DO-331.
• Experience with DO-326/DO-356 and DO-355.
• Experience with System and Software/AEH developments for an aircraft OEM.
• Experience with FAA Certification Compliance Reviews and regulations.
• Familiarity with Archer CM Tools, e.g. Polarion, Collaborator, Git/Bitbucket, TeamCity, Jira and Teamcenter.

At Archer, we aim to attract, retain, and motivate talent with the skills and leadership needed to grow our business. We drive a pay-for-performance culture and reward performance that support the Company's strategy. For this position, we are targeting a base pay range of $245,000 - $310,000. Actual compensation offered will be determined by job-related knowledge, skills, and experience.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Role

We are looking for a Principal Software Development Engineer to join our Engineering team in a hybrid capacity based in San Jose, CA, reporting to the Senior Director, Software Engineering. You will join the team that built the world’s largest cloud security platform from the ground up, enabling organizations worldwide to harness speed and agility with a cloud-first strategy. With more than 100 patents and 15 million users across 185 countries, you will bring your vision to a team of experts dedicated to enhancing our multitenant architecture and global footprint.

What you’ll do (Role Expectations)

• Designing, developing, and optimizing the system, including networking and security features, to support high-performance applications
• Ensuring federal certifications such as FIPS, FedRAMP, Common Criteria, and SOC2 compliance
• Creating design and functional specification documents while performing unit testing and automation to ensure quality
• Collaborating with cross-functional teams to identify and resolve system-related issues, optimize system performance, and innovate features
• Applying strong software design principles and deep troubleshooting expertise to deliver scalable, resilient, and impactful improvements to Zscaler’s Zero Trust Security Services

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.
• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.
• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.
• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.
• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• Bachelor's or Master's (preferred) degree in Computer Science or a related field with 10+ years of experience in system engineering for high-performance networking
• Expertise in Linux kernel-based networking (L2/L3), Stateful Firewall (IP tables / netfilter, network drivers, and protocols like VLANs, DHCP, DNS, SSL, DTLS, and Quic, IPsec
• Proficiency in Go and Python programming languages with excellent problem-solving skills for debugging complex data path issues
• Strong communication and collaboration skills to work effectively with cross-functional teams in a high-accountability environment
• Solid understanding of high-performance networking, security infrastructure, and the technical skills required for scalable systems design

What Will Make You Stand Out (Preferred Qualifications)

• Experience in technologies  such as wireguard,various tunneling protocols such as GRE, L2VPN, HA protocols such as VRRP alongside certifications like FIPS or FedRAMP
• Familiarity with cloud computing platforms like AWS or Azure and containerization technologies such as Docker and Kubernetes
• Advanced expertise in virtualization and security solutions

#LI-Hybrid

#LI-CM3

Principal Software Engineer – Capella Control Plane

Location: San Jose, California (Hybrid - in office at least 3 days/week)

Couchbase Capella is a fully managed Database-as-a-Service (DBaaS) platform that powers mission-critical applications with a modern, distributed NoSQL database. The Control Plane team builds and operates the foundational systems that deliver reliability, scalability, and seamless experiences across cloud environments.

We are seeking a Principal Software Engineer to serve as the cross-team technical authority for Capella's Control Plane — the platform that orchestrates SaaS interactions with major cloud providers (AWS, GCP, Azure). This role is central to the evolution of Capella's multi-cloud control plane and will shape the systems that provision, secure, and operate the platform at scale. You will set a durable technical direction with organization level influence, be accountable for production outcomes, and drive solutions to ambiguous, high-stakes problems through hands-on development and deep distributed systems expertise.

Key Responsibilities

• Architecture & Technical Direction: Define and evolve the control plane architecture for scalability, reliability, performance, and security.
• Hands-on Development: Develop and deliver production-quality Golang code for critical Capella platform services. Establish and enforce coding standards, CI/CD practices, and design patterns.
• Multi-Cloud Infrastructure: Architect and optimize multi-cloud deployments, networking models, VPC/VNet peering, load balancing, and secure connectivity across AWS, GCP, and Azure. Build and scale multi-tenant control plane services that orchestrate cluster lifecycle across providers.
• Reliability & Observability: Define and implement monitoring, logging, tracing, and alerting standards for operational excellence. Own accountability for production outcomes including root cause analysis and long-term remediation of critical issues.
• Platform Capabilities: Lead design and delivery of core platform capabilities such as provisioning, lifecycle management, and security controls. Tackle ambiguous distributed systems challenges involving scaling, networking, and performance.
• Cross-Team Leadership: Exercise cross-team technical authority, partnering with product, SRE, Quality Engineering, operations, and global engineering teams across geographies to align technical direction with business goals. Maintain working knowledge of web UI architecture and partner effectively with frontend engineers on end-to-end control plane workflows.
• Mentorship & Culture: Guide engineers across levels, perform code reviews, and set a high bar for engineering culture.
• Innovation: Research and evaluate cloud-native technologies, frameworks, and architectures for Capella's evolution.

Must-Have Skills & Experience

• Expertise in Golang with proven experience building distributed, cloud-native systems.
• Strong knowledge of system design, high availability, fault tolerance, and performance tuning.
• Hands-on experience with cloud infrastructure (AWS, GCP, Azure), including networking (VPCs, routing, load balancing, firewalls, private connectivity) and Kubernetes/container orchestration.
• Experience designing and building control plane and platform components for SaaS platforms at scale.
• Proven experience leading cross-team architecture and platform decisions in complex, ambiguous cloud and distributed systems environments.
• Working knowledge of web UI architecture and ability to partner effectively with frontend engineers on end-to-end control plane workflows.
• Experience mentoring engineers and driving org-level influence on engineering culture and standards.

Nice-to-Have Skills & Experience

• Experience with DBaaS platforms or large-scale database infrastructure.
• Exposure to AI/ML integrations within SaaS platforms (e.g., model serving, vector databases, AI-assisted workflows).

Education & Experience

• Bachelor's or Master's degree in Computer Science, Engineering, or a related technical field.
• 12+ years of professional software engineering experience, with at least 5+ years in cloud/distributed systems.
• Prior principal or staff engineer-level experience leading architecture and platform initiatives in cloud infrastructure or large-scale SaaS environments.

Role

We are looking for a Principal Machine Learning Engineer to join our ML/AI team. This is a hybrid role based in San Jose, CA, reporting to the VP, AI and ML within the Engineering department.

You will drive innovation within our growing ML/AI team, focusing on critical cybersecurity use cases like agentic frameworks, threat detection, and anomaly detection. Your work will enable organizations worldwide to harness speed and agility through a cloud-first strategy while solving complex security challenges at scale.

What you’ll do (Role Expectations)

• Lead the design and development of cutting edge, production ready AI/ML systems and pipelines, cybersecurity applications and provide technical guidance to junior and mid-level engineers

• Optimize existing machine learning pipelines for improved efficiency and scalability

• Explore and experiment with advanced AI techniques and architectures to solve complex cybersecurity problems while staying updated on the latest advancements in AI

• Collaborate with cross-functional teams to define project requirements and ensure alignment with business objectives

• Ensure systems and applications meet reliability, scalability and performance requirements

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.

• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.

• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.

• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.

• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• Bachelor's degree in Computer Science, or a related technical field

• 10+ years of experience as a Machine Learning Engineer or Scientist, with a proven track record of delivering successful projects in cybersecurity

• Strong proficiency in Algorithms, Game Theory and Optimization, Verification, and ML libraries and frameworks

• Extensive experience in data modeling, feature engineering, model development, and error analysis

• Excellent communication skills with the ability to translate complex technical concepts to stakeholders and peers

What Will Make You Stand Out (Preferred Qualifications)

• Proven track record of designing, building and shipping end-end applications at scale, with familiarity with multi-agent systems and orchestration frameworks

• Deep expertise with cloud infrastructure such as AWS or GCP for AI workloads

• Strong experience with agent architectures and SOTA AI frameworks, along with contributions to open-source ML projects or top-tier research publications

#LI-JM1 #LI-Hybrid

Role

We are hiring a Principal Software Development Engineer to be a founding member of our AI Security Team, offering the chance to build a high-reliability, low-latency AI security solution designed to scale for hundreds of millions of users. In this role, reporting to the Director, Software Development Engineering, you will be responsible for designing and implementing core infrastructure components and distributed systems while collaborating closely with various stakeholders throughout the development lifecycle. This is a hybrid role, reporting in to the San Jose, CA office 3 days a week.  

What you’ll do (Role Expectations)

• Architect, develop, and optimize a low-latency, high-throughput AI Security plane utilizing Rust, specifically leveraging its async/await model for highly efficient I/O and service-oriented architecture.
• Build resilient, distributed, and scalable systems, emphasizing concurrency, fault tolerance, and robust messaging protocols.
• Implement and maintain gRPC services and APIs to ensure seamless integration of the AI Security plane with control and orchestration infrastructure.
• Systematically enhance performance across the entire stack, including LLM models, by employing profiling tools for both kernel-space and user-space components.
• Contribute actively to the team through technical documentation, system design reviews, code reviews, and by mentoring junior engineering staff.Lead complex, multi-functional projects and initiatives, defining the technical roadmap and driving execution across teams.

Who You Are (Success Profile)

• Drive the mission with an owner's mindset, seamlessly bridging high-level strategy and detailed, hands-on execution.
• Actively seek challenges and find complex solutions that deliver maximum impact.
• Deeply empathize with internal and external stakeholders, anchoring every decision in addressing their real-world problems.
• Maintain strong technical curiosity, continually seeking more secure, scalable, and effective methods to accelerate transformation.
• Connect your work to the company's broader mission, designing solutions to support high-growth, global organizational needs.

What We’re Looking for (Minimum Qualifications)

• 12+ years of software engineering experience
• Deep experience in systems programming using Rust, with a focus on asynchronous frameworks such as Tokio or async-std.
• Proven ability to design and implement horizontally scalable, highly available, and observable distributed systems.
• Strong command of Linux internals, including kernel-user space interaction, networking, sockets, and namespaces.
• Skilled in performance instrumentation, containerized environments, Git workflows, and CI/CD pipelines.

What Will Make You Stand Out (Preferred Qualifications)

• Expert in systems languages such as C/C++ or Rust, with a focus on performance optimization.
• Deep understanding of Linux networking stacks, Kubernetes networking, service meshes, and LLM model optimization.
• Practical experience with gRPC, Protobufs, and L4-L7 networking protocols, including TCP/IP, TLS, QUIC, HTTP, and WebSockets (WSS).
• Direct experience in validating AI-driven products, including understanding of model performance metrics and MLOps principles.

#LI-BH1
#LI-Hybrid