Director of Strategic Partnerships (Semiconductor)

Summary:

• You will build and maintain strong relationships with leading AI platform companies, across their Automotive and Robotics organizations, in engineering, product, platform architecture, procurement, and executive leadership teams, within the key partner's organizations. This is a Hybrid-based position based in San Jose, CA.

Key Responsibilities:

• Represent Ethernovia as a trusted long-term technology partner and work closely with customer and ecosystem teams to position Ethernovia solutions within Automotive and Robotics reference designs and platform roadmaps.
• Coordinate cross-functionally with internal engineering, product, marketing, and executive teams to support strategic engagements and drive execution.
• Identify new partnership opportunities across adjacent product areas, emerging platform programs, developer ecosystems, and joint go-to-market initiatives.
• Provide structured market and competitive intelligence to Ethernovia leadership including insights into partner priorities, industry direction, and evolving trends in AI infrastructure, networking, robotics, and autonomous systems.
• Significant experience working with leading AI, semiconductor, or infrastructure companies and understand how large technical organizations operate and make decisions.
• Engage directly with semiconductor hardware architects, engineering teams, and senior business leaders and bring strong technical knowledge of Ethernet networking, high-speed interconnects, SerDes, PHY/MAC architectures, and sensor connectivity for AI or autonomous systems.
• Think strategically about ecosystems, platform adoption, and long-term market positioning rather than focusing only on transactions.

Required Experience & Skills:

• Semiconductor Industry Veteran: 12+ years of experience in strategic partnerships, business development, or technical sales within Semiconductors, AI infrastructure, networking, or HPC
• Existing relationships across the Silicon Valley AI and semiconductor ecosystem
• Strong technical understanding of Ethernet networking, high-speed interconnects, SerDes, PHY silicon or sensor networking architectures
• Experience driving silicon or platform technologies into strategic customer programs or reference designs
• Proven ability to navigate large cross-functional organizations and complex partnership cycles
• B.S. in Electrical Engineering, Computer Science, or related field required
• M.S. or MBA preferred

Nice to Have (The "Competitive Advantage"):

• Experience with ROS / ROS2, Isaac Sim, CUDA, etc
• Understanding and experience of OSI network layers 2+
• Experience of Ethernet switches and understanding of IEEE802.1 protocols
• Experience with TSN protocols
• Experience with PCIe protocols and topologies

Personal Skills:

• Excellent communication/documentation skills with ability to discuss technical or business information from Engineering to C-suite executives
• Attention to details
• Strong internal collaboration skills across product, engineering, marketing, and executive team located throughout the world 
• Highly self-directed, organized, and proactive with strong follow-through. Able to work effectively both independently and in a team
• Ability to identify organizational dynamics and key decision makers inside large companies
• Entrepreneurial mindset with willingness to travel frequently and spend significant time onsite with partners

What You Can Expect From Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $275,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, as well as eligibility for performance bonuses, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)

#LI-Hybrid

Principal Application Engineer Lead (Semiconductor HW & SW)

Summary:

• You will support Ethernovia’s field team and local customers developing next-generation Automotive, Robotics, and Physical AI platforms to help integrate Ethernovia’s high-performance Ethernet solutions into advanced hardware & software systems. This is a Hybrid-based position based in San Jose, CA.

Key Responsibilities:

• Interface between Ethernovia’s field team and engineering teams, you will bring strong technical competence and the ability to communicate effectively across our multinational teams
• Work closely with field application and business development teams around the world along with internal hardware, software and architecture teams, to support customer designs from early concept and development through validation and production.
• Hands-on role that requires strong problem-solving skills and the ability to operate across fast-moving technical programs
• Work directly with customer engineering teams and the field teams on complex system integration challenges involving high-speed networking, sensor connectivity, AI compute platforms and robotics architectures.
• Day-to-day activities include;
  • Creating design collateral
  • Close collaboration with system and engineering teams
  • Technical customer support and system bring-up
  • Debugging to support integration efforts across Automotive and Robotics applications including sensor fusion and autonomous systems and AI-driven platforms

Required Experience & Skills:

• Semiconductor Industry: 10+ years of embedded development experience with focus on both hardware and software
• Hands-on design experience with at least one of the following:
  • Ethernet PHYs
  • Ethernet switches
  • PCIe 
• Ability to diagnose and debug problems effectively
• Excellent team working abilities across global teams and confident interacting with engineers through to executive management
• Automotive experience at Tier 1, Tier 2 or OEM level
• B.S. or M.S. in Electrical Engineering

Nice to Have (The "Competitive Advantage"):

• Good understanding of embedded software drivers
• Understanding and experience of OSI network layers 2+
• Experience of Ethernet switches and understanding of IEEE802.1 protocols
• Experience with TSN protocols
• Experience with PCIe protocols and topologies
• Experience covering high speed PCB board design, layout and routing constraints
• Experience with ROS / ROS2, Isaac Sim, CUDA, etc

Personal Skills:

• Excellent communication/documentation skills
• Attention to details
• Collaboration across multidisciplinary and international teams
• Self-motivated and able to work effectively both independently and in a team

What You Can Expect From Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $180,000 - $240,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, as well as eligibility for performance bonuses, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)

#LI-Hybrid

Vice President of Operations (Semiconductor)

Summary:

• The VP of Operations will be the architect of Ethernovia’s delivery engine. Unlike purely administrative operations roles, this position requires a leader who is hands-on with semiconductor product, test, and qualification. You will bridge the gap between world-class networking chip designs and high-volume, automotive-grade silicon manufacturing. The position is based in San Jose, CA.

Key Responsibilities:

• Hands-on Product & Test Leadership: Drive the development of test hardware and software (wafer sort and final test). Oversee characterization, bench-to-ATE correlation, and limit-setting to ensure high-performance networking specs are met.
• End-to-End Semiconductor Qualification: Take direct ownership of the qualification strategy. You must have hands-on experience defining and executing stress testing, including HTOL (High-Temperature Operating Life), ESD, Latch-up, and HAST to ensure long-term silicon reliability.
• Automotive Grade Execution: Lead the transition to Automotive Qualification, ensuring all products meet rigorous reliability standards (AEC-Q100) and functional safety requirements (ISO 26262).
• Networking Silicon Manufacturing: Direct the operational lifecycle for high-speed Ethernet packet processors and PHYs, ensuring signal integrity and performance standards are maintained at scale.
• Foundry & OSAT Management: Act as the primary technical and commercial interface with Tier-1 foundries and OSAT partners; manage wafer capacity, production scheduling, and technology nodes.
• Yield & Cost Optimization: Use data-driven product engineering techniques to drive aggressive yield improvements and COGS reductions.

Required Experience & Skills:

Professional Background

• Semiconductor Operations Mastery: 15+ years of experience in fabless semiconductor operations, specifically for complex, high-performance SOCs or networking ICs.
• Hands-on Qualification Expertise: Must have direct experience managing and executing semiconductor qualification flows. You should be comfortable reviewing raw reliability data and troubleshooting failure mechanisms (FA).
• Product/Test Engineering: Proven track record of direct involvement in ATE (Automated Test Equipment) strategy, test time reduction, and product binning for high-speed communications chips.
• Automotive Tech & Quality: Experience navigating the Automotive electronics ecosystem, including IATF 16949, ISO 26262, and PPAP (Production Part Approval Process).
• Series B to Scale: Proven track record of building an operations and supply chain function from the ground up in a venture-backed startup.
• Education: Bachelor’s or Master’s degree in Electrical Engineering or a related technical field.

Technical Leadership & Skills:

• Vendor Management: Expert-level negotiation skills with Tier-1 partners (Foundries, Assembly, and Test houses).
• Networking Communications Focus: Understanding of the operational requirements for high-bandwidth data-path products (Ethernet, Switching, or high-speed SerDes).
• Systems Implementation: Experience deploying ERP systems (e.g., NetSuite, SAP) tailored for semiconductor supply chain and inventory tracking.

Nice to Have (The "Competitive Advantage"):

• TSMC Experience: Direct experience managing manufacturing flows through TSMC, including familiarity with their latest process nodes, FinFET technologies, and capacity planning.
• IPO & Public Company Readiness: Experience scaling operations for a company that successfully navigated an Initial Public Offering (IPO).
• International Expansion: Experience establishing operational hubs or quality centers in Europe or Asia to support global Tier-1 automotive OEMs.

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect From Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $220,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, as well as eligibility for performance bonuses, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)

#LI-Onsite

Vice President of Finance (Semiconductor)

Summary:

• The VP of Finance will be the primary architect of Ethernovia’s financial operations. While the CFO focuses on high-level strategy and external capital markets, you will be the "internal engine"—responsible for translating company vision into rigorous financial models, managing the day-to-day fiscal health of a fabless semiconductor business, and professionalizing our reporting for Board-level scrutiny. This is a Hybrid-based position based in San Jose, CA.

Key Responsibilities:

• Financial Architecture: Design and oversee the company’s internal financial controls, ensuring GAAP compliance and establishing a roadmap for SOX readiness.
• Operational FP&A: Lead the annual budgeting and monthly forecasting processes. Provide deep-dive analysis on R&D spend, tape-out costs, and head-count planning.
• Fabless Supply Chain Finance: Work closely with Operations to manage inventory valuation, COGS analysis, and gross margin modeling for our Ethernet packet processors.
• Series C & IPO Readiness: Partner with the executive team to prepare the "data room" for future funding rounds and lead the technical accounting efforts required for a potential public offering.
• Treasury & Tax: Manage global cash flow and tax strategies, including R&D tax credits and international transfer pricing as we expand into global markets.
• Business Partnership: Serve as a financial advisor to Department Heads (Engineering, Sales, Operations), helping them manage their P&L and ROI on hardware development.

Required Experience & Skills:

Professional Background

• Semiconductor Industry Veteran: 15+ years of finance leadership, specifically within a fabless semiconductor environment. You must understand the nuances of hardware lifecycles and foundry costs.
• Stage-Specific Growth: Proven experience in a high-growth startup environment, specifically scaling a finance function from Series B through commercialization.
• Technical Accounting: Deep mastery of US GAAP, revenue recognition for hardware/software licensing, and capitalization of R&D costs.
• Education: Bachelor’s degree in Finance, Accounting, or Economics; MBA or CPA strongly preferred.

Technical Leadership & Skills:

• Advanced Modeling: Expert-level financial modeling skills ($$$ and units) to forecast complex silicon production cycles and multi-year design-in periods.
• Systems Implementation: Experience migrating from early-stage accounting tools to robust ERP systems (e.g., NetSuite or SAP) and implementing BI tools.
• Team Builder: A track record of hiring, mentoring, and retaining high-performing accounting and finance teams in a competitive Silicon Valley market.

Nice to Have (The "Competitive Advantage"):

• IPO Execution: Experience as a Controller or Director of Finance at a company that successfully navigated an Initial Public Offering (IPO).
• Automotive Tech Experience: Familiarity with the financial implications of automotive "Design Wins" and the long-term revenue recognition cycles of Tier-1/OEM contracts.
• Audit Management: Experience leading a Big 4 audit process from start to finish.

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect From Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $220,000 - $280,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, as well as eligibility for performance bonuses, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)

#LI-Hybrid

Chief Financial Officer (Semiconductor)

Summary:

• As CFO, you will be a key member of the executive leadership team, serving as a strategic partner to the CEO and Board of Directors. You will be responsible for the company’s overall financial health, scaling our global financial infrastructure, and architecting the path toward a future public offering (IPO) or significant liquidity event. This is a Hybrid-based position based in San Jose, CA.

Key Responsibilities:

• Strategic Financial Leadership: Act as a "co-pilot" to the CEO, providing data-driven insights to influence product roadmap, geographic expansion, and go-to-market strategies.
• Capital Strategy & Fundraising: Lead future equity and debt financing rounds. Manage relationships with venture capital firms, private equity, and investment banks.
• Scaling Operations: Build and mentor a world-class finance and accounting team capable of supporting a rapidly growing fabless semiconductor business with complex supply chains and international subsidiaries.
• FP&A & Performance Management: Drive rigorous financial planning and analysis (FP&A), managing burn rates, R&D allocation, and gross margin optimization for semiconductor hardware and software stacks.
• Investor Relations: Craft and communicate the Ethernovia "story" to the investment community, translating technical milestones into financial value drivers.
• Compliance & Risk Management: Establish robust internal controls (SOX readiness), manage global tax strategies, and oversee legal/regulatory compliance for a San Jose-based technology firm.

Required Experience & Skills:

Professional Background

• Semiconductor Industry Veteran: 15+ years of progressive finance leadership, with significant experience in the fabless semiconductor or high-growth hardware technology sector.
• Startup Scaling: Proven track record of taking a company through Series B/C/D stages and scaling revenue from pre-product/early-revenue to significant commercial scale.
• Global Operations: Experience managing complex inventory, supply chain finance, and international entity structures (particularly in Asia and Europe).
• Advanced Education: MBA from a top-tier institution and/or CPA/CFA certification.

Technical Leadership & Skills:

• Capital Markets Savvy: Deep understanding of equity/debt instruments and experience navigating the due diligence process for sophisticated institutional investors.
• Business Acumen: Ability to understand the nuances of Ethernet networking, AI workloads, and automotive tier-1/OEM sales cycles.
• Systems Thinker: Experience implementing and optimizing ERP and CRM systems (e.g., NetSuite, SAP) to support high-growth environments.

Nice to Have (The "Competitive Advantage"):

• Public Market Experience: Direct experience leading a technology company through an Initial Public Offering (IPO) or serving as a high-level finance executive (VP Finance/Controller) in a public company.
• SEC Reporting: Strong familiarity with SEC reporting requirements, GAAP compliance for public entities, and Sarbanes-Oxley (SOX) implementation.
• Automotive Industry Exposure: Experience dealing with the long-term design-in cycles and rigorous quality standards (ISO 26262) of the automotive sector.

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect From Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $250,000 - $320,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, as well as eligibility for performance bonuses, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)

#LI-Hybrid

Senior ASIC Design Verification Engineer

Summary:  

• As a Senior ASIC Verification Engineer, you will be responsible for all aspects of digital SoC verification.
• You will work the architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.
• You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics.
• This position is located in: San Jose, CA

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC verification experience
• Strong understanding of ASIC verification fundamentals and industry standard methodologies
• Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
• Experience with the full verification flow, from spec to coverage analysis to gate level sim
• Debugging failures in simulation to root cause problems
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:
Experience in any of the following areas:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• Third party IP (SerDes, controllers, processors, etc.)
• Modular and Reusable Testbench architecture
• Design for re-use of pre and post silicon tests and infrastructure
• Automation of testbench creation, tests, regression, or EDA tools
• Knowledge of SystemC and/or DPI

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

Program Manager (Chip Development)

Summary:

• We're seeking an experienced and dynamic Program Manager to lead the end-to-end development lifecycle of complex integrated circuits (ICs). This role is all about defining, planning, executing, and finalizing chip development projects, making sure they're delivered on time, within budget, and to the highest quality standards, while strictly adhering to automotive industry requirements. You'll need a strong technical background in semiconductor design and manufacturing, coupled with exceptional leadership, communication, and problem-solving skills, particularly in the context of safety-critical and security-relevant systems, and a proven ability to manage customer relationships effectively.

• This position is located in: San Jose, CA

Key Responsibilities

• Program Leadership & Strategy:
• Define program scope, objectives, deliverables, and success criteria in collaboration with cross-functional teams (e.g., Architecture, Design, Verification, Physical Design, Software, Test, Product, Operations).
• Develop and maintain comprehensive program plans, schedules, and budgets, including critical path identification and risk mitigation strategies.
• Drive cross-functional alignment and accountability across all phases of the chip development lifecycle, from concept to silicon validation and mass production.
• Act as the primary point of contact for the program, providing regular updates to stakeholders, senior management, and external partners.
• Automotive Standards Compliance & Management:
• Ensure full compliance with ISO 26262 (Functional Safety) throughout the chip development lifecycle, including defining Safety Goals, ASIL decomposition, managing safety requirements, and overseeing safety analyses (e.g., FMEDA, FTA).
• Oversee adherence to ISO/SAE 21434 (Automotive Cybersecurity), managing cybersecurity risk assessments (TARA), defining cybersecurity goals, and ensuring secure design & verification practices for the IC.
• Drive implementation and adherence to Automotive SPICE (ASPICE) process requirements, ensuring robust software and hardware development processes, traceability, configuration management, and quality assurance.
• Work closely with functional safety and cybersecurity managers to integrate these standards seamlessly into the overall program plan and execution.
• Prepare for and support internal and external audits and assessments related to ISO 26262, ISO/SAE 21434, and ASPICE.
• Customer Relationship Management:
• Serve as the primary technical and program interface to key customers, understanding their needs, expectations, and ensuring their satisfaction throughout the development lifecycle.
• Effectively communicate program status, technical progress, and any potential issues or changes to customers.
• Proactively manage customer expectations and negotiate technical and schedule tradeoffs to achieve mutual success.
• Translate customer requirements into actionable internal development plans and ensure effective feedback loops.
• Execution & Monitoring:
• Lead and motivate diverse technical teams, fostering a collaborative and high-performance environment.
• Track program progress against milestones, identify deviations, and implement corrective actions.
• Proactively identify and manage program risks, dependencies, and issues, escalating as necessary.
• Facilitate effective communication and decision-making across all levels of the organization.
• Manage change requests and ensure proper impact analysis and approval processes are followed.
• Technical Acumen:
• Possess a strong understanding of the complete chip development flow, including RTL design, synthesis, place and route, timing closure, verification methodologies, DFT, analog/mixed-signal integration, packaging, and silicon bring-up.
• Collaborate with technical leads to resolve complex engineering challenges.
• Ensure adherence to design methodologies, quality standards, and industry best practices.
• Stakeholder Management:
• Build and maintain strong relationships with internal teams, external vendors (e.g., foundries, IP providers), and customers.
• Manage expectations and negotiate tradeoffs to achieve program goals.
• Prepare and deliver compelling presentations to various audiences, including executive reviews and technical forums.
• Continuous Improvement:
• Conduct post-mortems and lessons learned sessions to identify areas for process improvement.
• Implement best practices in program management and contribute to the evolution of our development methodologies.

Qualifications

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience:
• 8+ years of experience in the semiconductor industry, with at least 3-5 years in a dedicated program or project management role for chip development projects.
• Proven track record of successfully leading multiple complex ASIC/SoC development programs from concept to high-volume production.
• Demonstrable experience and strong understanding of ISO 26262, ISO/SAE 21434, and Automotive SPICE (ASPICE) requirements and implementation in semiconductor development.
• Experience with Automotive Safety Integrity Levels (ASILs) and Threat Analysis and Risk Assessment (TARA) processes.
• Strong understanding of semiconductor fabrication processes (e.g., FinFET, FD-SOI) and packaging technologies.
• Experience with various silicon technologies (e.g., CPUs, GPUs, DSPs, AI accelerators, custom ASICs) for automotive applications is a plus.
• Technical Skills:
• Familiarity with industry-standard EDA tools and design flows (e.g., Cadence, Synopsys, Siemens EDA).
• Knowledge of various verification methodologies (e.g., UVM, formal verification).
• Understanding of power management, clocking architectures, and high-speed interfaces.
• Program Management Tools & Skills:
• Proficiency and hands-on expertise with Atlassian tools, specifically Jira for issue tracking, project management, and reporting, and Confluence for documentation, knowledge sharing, and collaboration.
• Strong understanding of program management methodologies (e.g., Agile, Waterfall, Hybrid). PMP or equivalent certification is highly desirable.
• Excellent analytical, problem-solving, and decision-making abilities.

Desired Attributes

• Exceptional Communication: Outstanding verbal and written communication skills, with the ability to articulate complex technical information clearly and concisely to diverse audiences, including customers, regulatory bodies, and auditors.
• Strong Leadership: Ability to inspire, motivate, and guide cross-functional teams without direct authority.
• Results-Oriented: A drive to achieve aggressive goals and a commitment to delivering high-quality, safety-compliant, and secure products.
• Proactive & Resourceful: Ability to anticipate challenges, identify solutions, and adapt to changing priorities in a fast-paced and regulated environment.
• Collaborative: A team player who thrives in a collaborative environment and builds strong working relationships internally and externally.
• Customer-Centric: A strong focus on understanding and meeting customer needs, with a track record of building and maintaining positive customer relationships.
• Attention to Detail: Meticulous approach to planning, execution, and monitoring of program activities, with a strong emphasis on documentation for compliance.
• Business Acumen: Understanding of the automotive market, customer needs, and the financial implications of program decisions.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary will vary depending on factors such as individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $150,000 - $230,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

Summary

We are looking for a well-rounded Senior Staff / Principal level Functional Safety Engineer with 8+ years of experience in the semiconductor industry to lead and drive Automotive IC products to achieve ISO 26262 functional safety compliance at ASIL D. The ideal candidate has a solid track record of independently managing safety projects through successful certification and brings strong knowledge of ASPICE Level 3 process development.

This role will be a hands-on technical leader, ensuring safety compliance across the full IC lifecycle, conducting audits and assessments, and serving as the primary point of contact for safety-related concerns with OEMs, Tier 1 customers, and partners.

This position is located in: San Jose, CA (Hybrid)

Key Responsibilities

• Lead end-to-end functional safety activities for Automotive ICs in compliance with ISO 26262 (ASIL D).
• Define, implement, and maintain Safety Plans, Safety Concepts, FMEDA, Safety Manuals, and Safety Cases.
• Implement System Element out of context (SEooC), Assumption of Use (AoU) apprach and derive safety goals with ASIL decomposition strategies.
• Drive technical safety architecture definition for digital, analog, and mixed-signal ICs, including design and verification of safety mechanisms (ECC, lockstep CPUs, watchdogs, voltage/clock monitors).
• Perform and lead FMEA, FMEDA, and FTA analyses ensuring ASIL metrics (SPFM, LFM, PMHF) are satisfied.
• Independently conduct Functional Safety Audits, Confirmation Measures, Assessments, and Reviews.
• Collaborate with internal design, verification, and software teams to ensure freedom from interference and safe partitioning of ASIL vs. QM functions.
• Partner with OEMs, Tier 1 customers, and external assessors to address safety issues, support audits, and resolve concerns.
• Perform HW evaluation on non-compliance Ips (internal and external based)
• Support ASPICE Level 3 process development, ensuring alignment of FuSa with broader quality and process frameworks.
• Mentor junior functional safety engineers and help shape best practices across the organization.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering, Computer Eng., or related discipline.
• 8+ years of experience in Semiconductor development, specifically Automotive ICs.
• Proven record of leading functional safety projects independently through ASIL D certification.
• Strong knowledge of ISO 26262 (Part 2–11) and related standards.
• Past involvement in ASPICE Level 3 infrastructure and process development.
• Deep hands-on experience with:
• FMEA, FMEDA, FTA, DFA
• Fault injection testing and safety metrics analysis
• Safety mechanism design and verification
• Familiarity with requirements management tools (DOORS, Jama, Polarion) and safety analysis tools.
• Excellent communication skills to interface effectively with OEMs, Tier 1s, certification bodies, and cross-functional teams.

Preferred Skills

• Background in digital/analog/mixed-signal SoC design.
• HW/SW tool evaluation and classification
• Sound knowledge and background in ASPICE (up to level 3) and Cyber Security (ISO/SAE 21434).
• Strong experience in external audits and assessor engagement (e.g., TÜV, Exida and UL).
• Good understanding of Automotive relevant standards and tools i.e., IATF 16949, AEC-Q100, PPAP, APQP and five core Automotive tools.

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $170,000 - $270,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

Senior ASIC Front-End Design Engineer

Summary:

• As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
• Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
• Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
• You will be a trusted self-starter who can work with very little guidance or oversight.
• This position is located in: San Jose, CA (Hybrid)

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC RTL design and/or architecture experience
• Proven track record with the development of complex SoCs
• Strong understanding of digital design fundamentals and methodologies
• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:

Experience in any of the following areas:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• IP integration (SerDes, controllers, processors, etc.)
• Perl, TCL, C/C++, Make

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

#LI-Hybrid