The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Design and development of high performance firmware and software for cutting-edge enterprise SSD products.
• Debug, optimize, and validate SSD firmware on complex embedded multi-core architectures.
• Support customer qualification and adoption of SSD products.
• Participate in ground-breaking advanced SSD storage development and research projects.

What You Bring

• BS in Computer/Electrical Engineering or Computer Science with 3+ years of working experiences in silicon development or MS in Computer/Electrical Engineering or Computer Science with 1+ years of relevant working experience or PhD and 0+ years of relevant experience in storage firmware development is required.
• Strong programming experience and demonstrated proficiency in C/C++ for embedded systems, including development of algorithms, manipulation of complex data structures, and implementing highly optimized code, is required.
• Relevant hands on experience in embedded software or firmware development, including storage devices or other embedded platforms is required.
• Experience with one or more of the following storage related technologies: NVM Express, PCI Express, SAS, SCSI, NAND Flash/FTL, Fibre Channel, SATA, eMMC, or UFS is beneficial.
• Experience with ARM or equivalent embedded multi-core microprocessor architectures is required.
• Hands on experience with JTAG/ICE debuggers and protocol analyzers is required.
• Some scripting experience in one of Python/Perl/Javascript is desired.
• Familiarity and experience with modern agile software development methodologies and practices is preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are seeking an experienced Technical Program Manager to lead the strategy and daily operations of OCP S.A.F.E. for our Enterprise and Data Center SSDs. As a TPM, you will define and execute comprehensive plans to ensure timely delivery of OCP SAFE Evaluation, collaborate with multiple engineering teams, and drive vendor management with OCP Security Review Providers (SRPs). You will be expected to have a strong technical understanding of the subject matter and be able to grow into more complex technical leadership roles.

What You’ll Do

• Develop and execute comprehensive plans for OCP S.A.F.E. across multiple product generations, engineering teams, and SRPs.
• Manage vendor relationships with SRPs to ensure effective collaboration, issue resolution, and timely certification delivery.
• Collaborate with security engineering teams to ensure compliance with OCP S.A.F.E. specifications, cryptography implementations in storage applications.
• Track status on current certification submissions in progress, unblock engineers, and escalate blocker issues to management as needed.
• Work closely with business teams to provide visibility into certification schedules, timelines, deliverables, and dependencies.
• Drive process improvements through checklists, best practices, post-mortems to reduce QA time for certifications.
• Co-manage OCP S.A.F.E. program priorities target dates budget along with stakeholders.
• Maintain program status drive dependencies/actions across geographies.
• Provide regular updates on program status stakeholders.
• Represent security team customer meetings industry forums working groups.

What You Bring

• Bachelor's degree 10+ years relevant industry experience or Master's degree 8+ years’ experience as Technical Program Manager.
• Experience with FIPS certification process is a plus.
• Proven experience managing complex technical projects across multiple stakeholders; excellent communication skills required.
• Experience working with third party vendors.
• Good knowledge of cryptography principles is a plus, Storage Security Standards like- OCP S.A.F.E.,FIPS,NIST etc.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop black-box functional test coverage and test methodologies for NVMe SSD's.
• Debug, triage failures and work with FW Team to reproduce problems, design and run experiments.
• Analyze customer field issues and improve Functional test coverage where gaps are identified.
• Provide guidance to the Automation team and assist with test coverage integration into the existing framework.
• Must be able to work with local US and international customers and OEMs.

What You Bring

• Bachelors and 10+ yrs, Masters and 8+ yrs’ with focus in Computer Science, Computer Engineering, Electrical Engineering or equivalent.
• Strong programming experience, demonstrated proficiency in scripting languages such as Python, Bash, Linux shell scripts etc.
• Excellent verbal and written communication skills.
• Ability to work individually and in teams.
• Prior NVMe, PCIe knowledge or experience with one or more of the following storage-related technologies: NVM Express, PCI Express, NAND Flash/FTL .
• Knowledge of Enterprise storage/server systems, and proficiency in Linux.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, test execution and bug management tools.
• Relevant hands-on experience in embedded software or firmware development/testing, including storage devices or other embedded platforms.
• Familiarity and experience with agile development methodologies and practices, particularly in AI/ML-focused environments, is preferred.
• Hands-on experience with PCI protocol analyzers.
• Demonstrated ability to work as a team player, as part of a local and globally distributed team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are looking for a dynamic, self-motivated, experienced engineer to architect and lead functional test coverage and test methodologies for NVMe SSDs.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Manage Enterprise server infrastructure, execute Customer Qual tests and debug failures
• Execution of enterprise SSD qualifications in customer systems.
• Communicate with team lead to understand qualification processes and test plans. Report status of qualifications and manage customer expectations.
• Coordinate  with internal team and customer test engineers to execute qual plans as per schedule. Teams will be both local and remote.
• Triage test failures and do a first level FA. Design and execute experiments to root cause defects and verify fixes in coordination with development teams.
• Provide feedback to functional test teams on issues seen in customer quals to better functional test coverage.
• Contribute in Triaging customer field issues and provide support for timely resolution of customer issues.
• Identify automation opportunities and help Automation team to continue to improve and add to the existing framework.

What You Bring

• BS in Computer Science or related technical field with 10+ years of system level testing or development of enterprise servers and enterprise storage systems experience or MS with 8+ years preferred.
• Experience with at least storage protocol like NVMe/PCIe, SAS, SATA, Fibre Channel
• Familiar with one of protocol analyzers like LeCroy, SerialTek, or Xgig System or device level performance analysis
• Proficiency in server operating systems especially system debug tools such as system logs.
• Knowledge of enterprise storage/server system technologies.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, Test execution and bug management tools.
• Scripting experience such as in Perl, Shell or Python
• Experience with SSD or HDD testing
• NetApp/HPE/Dell/IBM System Experience
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

What You’ll Do

As a seasoned Senior Technical Project Manager (ASIC) you will lead complex silicon development projects from specification definition through tape-out, fabrication, and post-silicon validation. You will be the primary face of Samsung’s (SLSI’s) ASIC design, verification, physical design, firmware, foundry and advanced packaging teams to the customer and ensure the timely delivery of all collateral. This role requires a strong technical background in semiconductors combined with exceptional program management skills to navigate risks and drive execution excellence.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Reports to: Team leader/Head of Custom SoC Solutions Team.

Job ID: 42809

Key Responsibilities

• End-to-End Program Ownership: Work with customers from initial concept and specification stage to silicon tape-out, bring-up, and production. This includes not only technical, but also spans commercial and legal domains.
• Project Planning & Scheduling: Develop and maintain detailed project plans, milestones, and resource allocation. Proactively identify and resolve bottlenecks and critical path issues.
• Cross-Functional Coordination: Collaborate with Architecture, RTL, Verification, Physical Design (PnR), DFT, Firmware, Emulation and Packaging teams to ensure aligned deliverables. Participate in cross functional meetings and identify and eliminate bottlenecks.
• Risk Management: Proactively identify risks and develop mitigation plans to avoid tape-out delays. Hold the development teams accountable for the scheduled quality deliverables.

 What you bring

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 15+ years or a Master’s degree with 13+ years.
• Experience: 10+ years in the semiconductor industry, with at least 5+ years in technical program/project management for ASIC/SoC products.
• Technical Knowledge: Deep understanding of the full ASIC design flow (RTL, Simulation, Synthesis, STA, PnR, DFT, Tape-out).
• Methodologies: Proven experience working with advanced process nodes and high-speed design.
• Tools: Proficiency in project management tools (Jira, Confluence, MS Project) and familiarity with EDA tools (Synopsys, Cadence).
• Experience with complex packaging (2.5D/3D IC, Si interposers, TSV).
• Knowledge of automotive functional safety and other automotive industry requirements
• Experience with hardware emulation platforms (Palladium, Veloce, ZeBu).
• Leadership: Strong ability to influence cross-functional teams without direct authority.
• Problem-Solving: Ability to analyze technical problems and drive solutions in a fast-paced environment.
• Communication: Excellent verbal and written communication skills, tailoring technical information for various stakeholders.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

 What You’ll Do

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

Job ID: 42786

• NVMe or SAS SSD Firmware development
• Analyze, debug, and resolve firmware issues observed at domestic and international customer sites as well as at local and overseas development centers.
• Triage and root cause system, driver, and device interoperability issues at customer sites.
• OEM Spec gap analysis, firmware customization/feature development; collaborate with other engineering teams to analyze debug information and implement and deploy firmware patches.
• Need based business travel and stay at domestic and international customer sites as well as overseas development centers for extended periods of time (can be up to multiple weeks at a time)
• Assist customers by running or inspecting their tests at onsite locations

What You Bring

• BS in Computer/Electrical/Electronic Engineering or Computer Science, and 5 years of relevant experience in software or firmware or a MS in Computer/Electrical/Electronic Engineering or Computer Science with 3 years of relevant experience preferred. 
• Strong experience in C/C++ programming for embedded systems is required. 
• Strong experience with UART/JTAG/ICE debuggers, and protocol analyzers. 
• Familiarity with at least one of the storage protocols such as SAS / SATA / SCSI / FC / NVMe / PCIe protocols is required. 
• Hands on experience with UART/JTAG/ICE debuggers, firmware debugging and protocol analyzers. 
• Demonstrated ability to work as a team player, as part of a local and globally distributed team. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The Samsung Semiconductor Inc., Wireless Connectivity Software Engineering team is seeking highly motivated and enthusiastic Software Engineers to join our team in developing software infrastructure, framework, and protocol stack for 802.11 based WLAN chipsets. We are looking for engineers with expertise in MAC Layer concepts and firmware development. As a member of the WLAN Software team, you will be responsible for developing software modules for the data path and control path in MAC and physical layer of various WLAN chipsets.

Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy

Req: 42831

What You’ll Do

• Work with 802.11 WLAN chipsets, devices and protocols, including other networking devices
• Collaborate with wider teams to for end to end feature deliverables build and maintain production quality Firmware
• Design and develop modules in embedded firmware for Samsung’s Wireless Connectivity solutions
• Major focus will be implementing, unit testing and fixing issues various features of 802.11 MAC

What You Bring 

• Bachelor’s Degree in Engineering or Computer Science Discipline with 5+ years of relevant industry experience, or Master’s with 3+ years or PhD with 0+ years in field of wireless communication technologies.
• Excellent coding skills in C in embedded space for firmware development is critical.
• Ability to debug issues with low-level embedded software, custom/proprietary code and enhancements.
• WLAN standards, domain knowledge of Wi-Fi (IEEE 802.11) MAC protocols, WFA protocols and coexistence with other wireless technologies such as BT, UWB and cellular.
• Knowledge of OFDM, OFDMA principals, beam forming and RF concepts will be additional advantage.
• Understanding of QoS concepts and data path optimization algorithms.
• Understanding of the Linux Operating System, kernel and device driver development.
• Ability to use various debugging tools such as wireshark, testing tools such as WFA test beds, version control tools such as git.
• Knowledge of Python will be additional advantage
• Familiarity with other wireless technologies such as BT, Ultra Wide band and Cellular 4G/5G not required but preferred.
• Excellent coding skills in C programming languages.
• Strong understanding of MAC Layer concepts & physical layer (e.g., modulation analysis (OFDM, OFDMA)) Concepts.
• Experience in developing firmware for wireless communication protocols (WLAN).
• Fluency in using lab equipment such as network analyzers, WFA test beds, signal generators, power meters etc.
• Familiarity with WLAN standards & domain knowledge of Wi-Fi MAC/PHY Specifications.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

About the Role

As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.

Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams.

This position is required onsite in San Jose, CA.

Key Responsibilities

• Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms
• Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems
• Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning 
• Serve as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrations
• Interpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutions
• Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on schedule
• Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows
• Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral
• Represent the Leo team in customer technical reviews, design-in engagements, and industry forums

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
• 8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications
• Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
• Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!
• Authorized to work in the US and available to start immediately

Required Experience

• High proficiency in C for embedded firmware development in RTOS environments
• Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
• Proficiency in Python for scripting, test automation, and diagnostic tooling
• Deep hands-on knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
• Experience with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
• Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
• Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
• Experience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines

Preferred Experience

• Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
• Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
• Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
• Experience with server memory performance tuning — latency and bandwidth optimization
• Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus

Compensation

The base salary range for this role is $175,000 – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

What you’ll do:

• Design and develop fault tolerant and high power density motor controller including drivers, sensors, power stages, and embedded control interfaces
• Be responsible for all aspects of power electronics designs from components, circuits, modules and system integration 
• Passive component design and optimization in power electronics systems
• EMC and Lightning design, analysis, and testing for low voltage and high voltage electronic systems
• Lead new designs from conception into production while working with a multidisciplinary team
• Start to finish ownership of hardware – from specification to design, prototype, reliability validation and manufacturing
• Requirements capture, topology trade-study and performance modeling
• Schematic, layout and PCB assembly design and review
• Design and carry out prototype verification tests for proof of concept
• Analyze test data and reports to verify functional and performance specifications.
• Troubleshoot and execute root cause analysis on prototype and production designs.

What you need:

• Electrical Engineering Degree or equivalent experience.
• 3+ years of relevant electrical system and circuit board design experience.
• Sound knowledge and hands-on experience in traditional and modern power electronic technologies including (not limited to):
• Inverter technology for variable speed motor drive (MOSFET, rectifiers and gate driver PWM technologies).
• Passive power devices, e.g. inductors, capacitors, resistors and transformers.
• Power electronics system architecture design and hardware integration.
• Motor drive and power converters (AC-DC, DC-DC, DC-AC) control technologies.
• Motor control and commutation methods for various types of three phase motors.
• Microcontrollers and processors
• Sensor technology and implementation
• Gate drive design for wide bandgap devices (SiC and GaN)
• Experience with 1-10kW inverters at 400V-1000V
• Experience in using schematic capture and circuit simulation software (e.g. Altium Designer or Xpedition). 
• PCB layout experience
• Experience performing circuit design analyses such as worst-case circuit analysis, fault analysis, and reliability analysis
• Experience in design for test and design for high volume manufacture
• Mastery of all types of lab instruments: oscilloscope, EMC analyzers etc.
• Excellent organizational and communication skills

Bonus Qualifications: 

• Hands on experience with DO-160G testing and DO-254 development
• Masters or Ph. D. in electrical engineering 
• Embedded firmware development experience
• Passion for aviation and eVTOLs

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $120,000.00 - $150,000.00. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Archer is seeking a Staff Electrical Engineer- Actuators to lead the architecture, design, development and validation of electronics and electromechanical actuators used in flight-critical systems such as propulsion tilt, pitch control surfaces and landing gear. 

What you’ll do:

• Design and develop fault tolerant and high power density actuator controller including motor drivers, sensors, power stages, and embedded control interfaces
• Be responsible for all aspects of power electronics designs from components, circuits, modules and system integration 
• Passive component design and optimization in power electronics systems
• EMC and Lightning design, analysis, and testing for low voltage and high voltage electronic systems
• Lead new designs from conception into production while working with a multidisciplinary team
• Start to finish ownership of hardware – from specification to design, prototype, reliability validation and manufacturing
• Requirements capture, topology trade-study and performance modeling
• Schematic, layout and PCB assembly design and review
• Design and carry out prototype verification tests for proof of concept
• Analyze test data and reports to verify functional and performance specifications.
• Troubleshoot and execute root cause analysis on prototype and production designs.

What you need:

• Electrical Engineering Degree or equivalent experience.
• 3+ years of relevant electrical system and circuit board design experience.
• Sound knowledge and hands-on experience in traditional and modern power electronic technologies including (not limited to):
• Inverter technology for variable speed motor drive (MOSFET, rectifiers and gate driver PWM technologies).
• Passive power devices, e.g. inductors, capacitors, resistors and transformers.
• Power electronics system architecture design and hardware integration.
• Motor drive and power converters (AC-DC, DC-DC, DC-AC) control technologies.
• Motor control and commutation methods for various types of three phase motors.
• Microcontrollers and processors
• Sensor technology and implementation
• Gate drive design for wide bandgap devices (SiC and GaN)
• Experience with 1-10kW inverters at 400V-1000V
• Experience in using schematic capture and circuit simulation software (e.g. Altium Designer or Xpedition). 
• PCB layout experience
• Experience performing circuit design analyses such as worst-case circuit analysis, fault analysis, and reliability analysis
• Experience in design for test and design for high volume manufacturing
• Mastery of all types of lab instruments: oscilloscope, EMC analyzers etc.
• Excellent organizational and communication skills

Bonus Qualifications: 

• Hands on experience with DO-160G testing and DO-254 development
• Masters or Ph. D. in electrical engineering 
• Embedded firmware development experience
• Passion for aviation and eVTOLs

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $120,000 - $150,000. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Job Overview

As a Firmware Engineering Director/ Manager, you will lead and scale firmware development efforts for Astera Labs’ SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development.

Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs.

This role supports two leadership levels:

• Firmware Engineering Manager
• Firmware Engineering Director

Key Responsibilities

• Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps.
• Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers.
• Provide technical oversight and architectural guidance without being the primary implementer.
• Partner closely with hardware architecture, RTL design, validation, and systems teams to define HW/SW interfaces, development milestones, and integration plans.
• Drive SoC bring-up readiness, firmware validation strategy, and risk mitigation across pre-silicon and post-silicon phases.
• Establish development processes, coding standards, and quality metrics to ensure predictable and scalable execution.
• Support customer engagements as needed, including escalation handling, technical reviews, and roadmap alignment.
• Communicate status, risks, and tradeoffs clearly to executive leadership and cross-functional stakeholders.
•  Director scope: own multi-team delivery, long-term roadmap planning, hiring strategy, and cross-org alignment across multiple product lines.

Firmware Domains Under Management

Teams under this role may span one or more of the following areas:

• PCIe Firmware: PCIe switch and controller firmware (Gen3+), including link training, enumeration, error handling, and performance optimization.
• Ethernet Firmware: Embedded firmware for high-speed Ethernet systems (100G–400G+), including PHY/MAC interaction and link bring-up.
• UCIe / Chiplet Firmware: Firmware for chiplet-based SoC architectures, including die-to-die interconnect initialization and advanced packaging enablement.

Required Experience

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of experience developing or supporting firmware for SoC, silicon, or systems products in compute, networking, or storage domains.
• 5+ years of experience in a people-management role, leading firmware or low-level software teams.
• Strong understanding of bare-metal firmware, RTOS environments, and firmware development lifecycles.
• Experience managing teams working on complex SoCs and high-speed interfaces such as PCIe, Ethernet, DDR, NVMe, or similar.
• Proven ability to lead execution across ambiguous, fast-moving environments with multiple stakeholders.
• Strong communication skills, executive presence, and customer-facing professionalism.
• Authorization to work in the U.S.

Preferred Experience

• Prior experience managing firmware teams delivering PCIe or Ethernet switch products.
• Experience with UCIe, chiplet architectures, or advanced packaging ecosystems.
• Track record of scaling teams through hiring, onboarding, and mentorship.
• Experience working with or supporting customers during bring-up, deployment, or escalations.
• Participation in industry ecosystems such as OCP or OpenBMC.
• Director level: experience owning multi-program delivery, long-term technical roadmaps, and cross-functional organizational planning.

Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.

Job Description

• Seeking a strong technical leader who has delivered multiple SoC products.
• Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs.
• Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications.
• Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.
• Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.
• Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.
• Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness.
• Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions.
• The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.
• Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.
• Drive a culture of technical excellence, accountability, and continuous improvement.
• Manage resource planning, and vendor/partner relationships.

Basic Qualifications

• Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred.
• ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.
• ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• ≥5 years building high performance Engineering teams and validation methodologies.
• Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.
• Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.
• Strong background in debug methodologies, lab infrastructure, and automation frameworks.
• Excellent communication skills and ability to influence executives and cross‑functional partners.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Preferred Experience

• ≥8 years leading validation teams planning, execution and maintaining project visibility.
• ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.
• Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.

The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

Role Overview 

Astera Labs is seeking a Director, Global Talent Acquisition to lead and scale our worldwide recruiting function during a pivotal period of hypergrowth. This is a high-impact leadership role responsible for building and executing the talent acquisition strategy that will fuel our expansion across North America, APAC, EMEA, and India. 

As a key member of the People team, you will own the end-to-end recruiting lifecycle, from executing on the workforce plan and employer branding to team development and operational excellence. You'll partner closely with executive leadership to ensure we attract and hire the world-class engineering and business talent needed to maintain our position as the leader in AI infrastructure connectivity. This role requires a hands-on leader who thrives in fast-paced environments, has deep semiconductor industry expertise, and has a proven track record of building high-performing global recruiting teams from the ground up. 

Key Responsibilities 

Global Talent Acquisition Strategy & Execution 

• Develop and execute a comprehensive global talent acquisition strategy aligned with Astera Labs' aggressive growth objectives and workforce plans 
• Partner with executive leadership and hiring managers to forecast hiring needs, prioritize roles, and deliver against ambitious recruiting targets 
• Build scalable recruiting processes, systems, and metrics to support a rapidly growing organization 

Team Leadership & Development 

• Lead, mentor, and scale a global team of recruiters and recruiting coordinators across North America, APAC, EMEA, and India 
• Establish clear performance expectations, provide ongoing coaching, and foster a culture of excellence, accountability, and continuous improvement 
• Identify and develop future recruiting leaders within the organization 

Semiconductor & Technical Recruiting Excellence 

• Leverage deep semiconductor industry knowledge and networks to source and attract top-tier engineering talent in a highly competitive market 
• Drive innovative sourcing strategies to build robust pipelines for critical technical roles across hardware, firmware, and software disciplines 
• Serve as a trusted advisor to hiring managers on market trends, compensation benchmarking, and competitive intelligence 

Operational Excellence & Employer Branding 

• Implement and optimize recruiting tools, processes, and analytics to drive efficiency and improve candidate experience 
• Partner with Marketing and People teams to strengthen Astera Labs' employer brand and position the company as a destination for top talent 
• Ensure compliance with global hiring regulations and maintain consistency in recruiting practices across all regions 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, or related field 
• 10+ years of progressive talent acquisition experience, including 5+ years in a leadership role managing global recruiting teams 
• Proven experience in the semiconductor or adjacent hardware technology industry 
• Demonstrated success scaling recruiting functions and building teams from scratch in high-growth environments 
• Experience leading distributed teams across multiple geographies (North America, APAC, EMEA, India) 
• Strong understanding of technical roles and the ability to effectively partner with engineering leaders 

Preferred Qualifications 

• Experience at a pre-IPO or recently public technology company during periods of rapid scale 
• Track record of recruiting for highly specialized semiconductor roles (analog/mixed-signal, ASIC, firmware, etc.) 
• Experience implementing or optimizing applicant tracking systems and recruiting analytics platforms 
• Strong executive presence with the ability to influence and build relationships at all levels of the organization 
• Data-driven mindset with experience using metrics to drive recruiting performance and strategic decisions 

Salary range is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle. 

As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers. 

Location - San Jose, CA OR Israel 

Key Responsibilities 

• Product Technical Ownership 

• Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement 

• Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met 

• Lead development of large-scale chips (300-400mm²) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures 

• Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths 

• Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality.  

• Cross-Functional Technical Leadership 

• Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest 

• Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria 

• Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies 

• Work closely with physical design teams on timing closure, power optimization, and backend execution 

• Process Excellence & Organizational Development 

• Establish and reinforce scalable processes, documentation, and handoffs that support company growth 

• Provide structured, data-driven decision-making and maintain a crisp operational cadence across the product line 

• Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration 

• Model steady, calm leadership, particularly in high-stakes or ambiguous situations 

• Shape engineering culture and talent strategy to support Astera's rapid growth trajectory 

Basic Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 

• 15+ years of experience across architecture, silicon design, validation, systems, or related domains 

• Proven track record of developing large-scale chips (300mm²+) through successful tapeout 

• Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures 

• Strong understanding of RTL design, design verification, DFT, and physical design flows 

• Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures 

• Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership 

• Strong communication and executive presence with the ability to influence at all levels of the organization 

Preferred Qualifications 

• Master's degree in Electrical Engineering or Computer Engineering 

• Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures 

• Experience with advanced process nodes (7nm, 5nm, or below) 

• Background in power management, clocking architectures, or high-speed analog integration 

• Experience operating in fast-growing startups or hyper-scale environments 

Key Leadership Competencies 

• Systems Thinking: See the big picture while managing details 

• Emotional Intelligence: Calm under pressure, empathetic, and influential 

• Adaptability: Thrive in ambiguity and fast-changing environments 

• Execution Discipline: Deliver predictable results without sacrificing innovation 

Astera Labs’ firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems.

Job Description

• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance.
• Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic Qualifications 

• Strong academic and technical background in electrical or computer engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Required Experience 

• ≥3 Years experience leading a team in a “lead by example” manner—planning sprints, assigning tasks based on individuals’ strengths and career aspirations, providing constructive/encouraging feedback, maintaining a “dashboard” view of project status, chipping into shore up gaps in execution as needed.
• ≥5 Years hands-on experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Good understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred Experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Familiarity with PCIe compliance standards and the ability to follow and be involved in compliance and standard consortiums.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, clock recovery and SerDes link budgets.
• Experience with PAM4 SerDes is a huge bonus!

Job Description: 

As an Astera Labs Early Career Product Application Engineer, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products. 

Basic Qualifications 

• Strong academic and technical background in electrical engineering.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!  

Required Experience  

• Technical ownership of issue resolution
• Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.  
• Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences. 

Preferred experience 

• Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment. 
• Development/support for PCIe or Ethernet Switch or Retimer products. 
• PCIe compliance testing methodology and troubleshooting. 
• Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages. 
• Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc. 

The base salary range is $104k USD - $150k USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Role Overview

Join Astera Labs as a Technical Lead Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 5+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $160,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

Overview:
We are seeking a highly skilled and experienced Technical Lead Power Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.

Key Responsibilities:

• Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.
• Design high-efficiency, high-reliability power circuits including:
• Buck / boost / buck-boost converters
• Multiphase regulators
• Hot-swap, protection, and sequencing circuits
• Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance of mismatches.
• Perform power integrity, transient response, stability, and thermal analysis.
• Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also, will be asked to do the same evaluation on overall system level design components.
• Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.
• Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.
• Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.
• Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.

Basic Qualifications:

• Education: Bachelor’s or Master’s degree in electrical engineering or related field.
• Experience: 5-8 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.
• Technical Skills:
• Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.
• Strong understanding of power integrity principles and techniques.
• Experience with power component selection and vendor collaboration.
• Hands-on experience with debugging power-related issues using lab equipment.
• Proficiency with lab equipment (oscilloscopes, electronic loads, spectrum analyzers).
• Soft Skills:
• Excellent problem-solving and analytical skills.
• Strong communication and teamwork abilities.
• Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Familiarity with high-speed interfaces such as PCIe, DDR, and USB.
• Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.
• Familiarity with Design for Manufacturability (DFM) considerations.
• Experience in thermal management and reliability analysis.

Why Join Us:

• Work on cutting-edge ASIC designs in a collaborative and innovative environment.
• Opportunity to influence power design strategies and contribute to product success.
• Access to state-of-the-art tools and resources to enhance your skills and career growth.

If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.

Base pay range for this role is $170,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Overview: 

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Description:

We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic Qualifications:

• Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)
• Experience in working with RF testing and characterization
• Knowledge of spectrum analyzers, vector network analyzers (VNA), and other RF test equipment
• Have gone through at least one cycle of full product development life cycle
• Strong academic/technical background in electrical or computer engineering; bachelor’s is required; MS preferred
• Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
• Digital and analog circuit level understanding for DUT.
• Excellent team player with great communication skills
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required Experience:

• Detail-oriented monitoring of device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs
• Experience with RF calibration techniques and de-embedding methodologies
• Experience with RF parameter measurements including S-parameters, insertion loss, return loss, and signal integrity analysis
• Hands-on work with Advantest 93k ATE platform (SmartScale/ExaScale) including test program updates for wafer sort and final test solutions
• Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions
• Energetic work mindset to meet the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred Experience:

• Hands-on product/package qualification
• Partnering with Fabs on process development and yield improvement initiatives
• Collaboration with silicon validation teams to ensure device performance meets production requirements
• Firmware development in C/C++, scripting in Python, or other equivalent programming languages

Job Description:

We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic Qualifications:

• Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)
• Experience in working with PCIe Gen3 and above
• Have gone through at least one cycle of full product development life cycle
• Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred
• Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
• Digital and analog circuit level understanding for DUT.
• Excellent team player with great communication skills
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required Experience:

• Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions
• Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.
• Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs
• Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions
• Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred Experience:

• Working with silicon validation teams to ensure device performance meets production requirements.
• Firmware development in C/C++, scripting in Python, or other equivalent programming experience.
• Hands on experience in product/package qualification

As an Astera Labs Technical Lead Lab Validation Engineer, you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions.  You will:

• Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions.  Collaborate with design, validation, and system engineering teams as needed.
• Modify device firmware to test out engineering theories leading to potential fixes or production screens.
• Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems.
• Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability.
• Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports.
• Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures.
• Develop and run stress tests and margining experiments to identify weak design or process corners.
• Provide feedback on system-level integration challenges for retimers and PCIe switches (e.g., board layout, equalization tuning, firmware interactions).
• Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing.
• Document debug findings, propose design/process/test improvements, and contribute to FA methodologies.
• Participate in new product development process to ensure readiness for customer returns before products are launched. Collaborating in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts.

Basic qualifications:

• Minimum of a Bachelor’s in Electrical Engineering while a Master’s degree is preferred. 
• Minimum of 10 years relevant experience of which 5 years’ is hands-on mixed high-speed lab experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA.
• Python programming.
• Deep understanding of PCIe protocol (up through Gen6), retimer architecture, and SerDes signal integrity.
• Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing).
• Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures).
• Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity.
• Experience in post-silicon validation and bring-up of high-speed PHYs or retimers.
• Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures.
• Strong written and verbal communication skills.

Preferred experience (ideal candidate has some of this, but OJT is also possible):

• C (not C++).
• Experience with optics.
• Experience with chip-level security and RAS features.
• ATE (Automated Test Equipment) Advantest V93K.
• Understanding of system-level architecture for servers, storage, and AI/ML platforms where PCIe retimers/switches are deployed.

Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.

The base salary range is $160,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

As a Senior Software Diagnostics Engineer on the Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture of cutting-edge high-speed datacenter products.  You will be working on a project from conception to the final production stage at contract manufacturer.

The role requires a strong and broad software background and a good understanding of hardware design and manufacturing practices.  At the same time, we welcome candidates with deep experience in smaller areas and desire to learn.  Depending on your experience, you may be focusing on design/validation or automation/manufacturing.

Key Responsibilities:

• Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.
• Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product
• Bring-up newly manufactured boards and port the first level of software.
• Isolate and perform root-cause analysis of reported failures
• Support new platform software and hardware features
• Coordinate with the hardware engineering team on bring-up schedules and feature delivery
• Participate proactively in design discussions, design review and project management

Basic Qualifications

• Bachelors in Computer Science/Computer Engineering or equivalent experience.
• Knowledge of modern software development
• Proficiency in Python, C or similar
• Ability to work cross-functionally in a fast-paced, highly technical environment.

Required Experience

• 2+ years of Experience in subset of diagnostics, hardware bring-up, test or manufacturing automation
• Strong debugging skills across hardware, firmware, and system layers

Preferred Experience/Nice to Have

• Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing
• Ability to read schematic/layout
• System debug experience
• Embedded programming and good knowledge of OS internals (Linux/Unix)
• Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.
• Experience with DDR5

The base salary range is $120,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Overview

Astera Labs Inc. is seeking an experienced and self-driven Hardware Lab Engineer to join our dynamic team in developing world class connectivity products for AI infrastructure.

Job Description

This role will work closely with firmware, system validation, quality, and product engineers to support silicon bring-up, characterization, and debug activities through hands-on lab execution. The ideal candidate will have a deep understanding of circuits, hands-on experience with PCBAs and silicon test environments, and the ability to work on complex, open-ended tasks with minimal oversight.

Key Responsibilities

• Setup and maintain test environments for silicon validation and characterization. Configure and update hardware, software, firmware, and applications. Replicate BKCs.
• Conduct hands-on testing of silicon devices including PCIe Gen5/6/7, CXL, Ethernet, and other high-speed interfaces
• Install and configure servers, including FW, BIOS, OS, and network
• RMA intake/triage: inspection, electrical verification, screening (including CSAM inspection), and prioritization
• Manage logistics and communications with external labs
• Organize, track, and distribute lab equipment, hardware, and peripherals
• Ad hoc PCBA rework and soldering of fine-pitch SMD components
• Develop, document, and maintain lab procedures

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 5-12+ years of hands-on experience in lab environments supporting silicon validation or hardware development
• Proficiency with high-speed test equipment (oscilloscopes, protocol analyzers, BERTs, multimeters)
• Experience with high-speed interface testing (PCIe, CXL, DDR, Ethernet, or SerDes)
• Strong programming skills in Python for test automation
• Familiarity with Linux operating systems and command-line tools
• Demonstrated experience coordinating with third-party testing laboratories and managing logistics, including sample shipping, chain of custody, and scheduling
• Strong organizational skills for managing multiple RMA cases simultaneously and prioritizing based on severity/impact

Preferred Qualifications

• Experience with post-silicon validation of ASICs, SoCs, or Retimer/PHY products
• Knowledge of analog/mixed-signal circuit testing and debugging techniques
• Experience with JTAG, I2C, SPI, and other embedded interfaces
• Familiarity with PCB design, schematic reading, and signal integrity concepts
• Knowledge of data center systems architecture (servers, AI platforms, networking equipment)
• Understanding of ATE (Automated Test Equipment) systems and production test methodologies
• Experience with defect screening methodologies including visual inspection, electrical testing, and acoustic imaging
• Experience with complete RMA lifecycle management from intake through root cause analysis and corrective action
• Knowledge of common semiconductor failure modes and failure analysis techniques including die attach inspection, delamination detection, void analysis, and crack identification
• Experience with formal compliance testing and industry standards

The base salary range is $160,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role Overview

Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

Overview

Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
• Work closely with post-silicon teams to facilitate silicon bring-up and debug.
• Mentor junior engineers to develop their technical skills and expertise.
• Actively contribute to the development and improvement of silicon development processes.
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success.

Required Qualifications:

Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Architecture definition and micro-architecture development
• RTL coding, functional simulation, and synthesis
• Timing closure and gate-level simulation (GLS)
• Design for test (DFT) implementation
• Production experience with advanced CMOS nodes (≤7nm)

Protocols & Integration:

• Deep expertise in at least one high-speed protocol—PCIe , Ethernet, Infiniband, DDR, or similar
• Third-party IP integration and verification.
• Block-level design ownership from architecture through GDS

Tools & Methodologies:

• Proficiency with Cadence and/or Synopsys digital design flows
• Familiarity with UVM-based verification methodologies.
• Silicon bring-up, debug, and failure analysis expertise

Professional Attributes:

• Strong work ethic with the ability to balance multiple priorities in a dynamic environment
• Excellent communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements
• Customer-focused mindset with ability to translate business needs into technical excellence

Preferred Qualifications

• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality

The Role and Its Impact 

Our Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications, providing critical signal conditioning for high-speed connectivity in AI infrastructure. The firmware you develop will manage complex system and IP integration, SERDES configuration, link training sequences, and diagnostic capabilities for these devices deployed in data centers worldwide. 

As a Principal Engineer in our Signal Connectivity Engineering group, you'll contribute to firmware that directly impacts the performance and reliability of Ethernet connectivity solutions powering AI infrastructure globally. Working closely with the SoC software, transceiver module software, and system validation teams, you'll take ownership of feature development and rollout, software integration testing, and customer debug activities. Working at the intersection of embedded systems and high-speed Ethernet connectivity, you'll collaborate closely to bring these systems to production. 

We're a startup, and this role reflects that reality. You'll have responsibilities spanning firmware development, customer engagement, debug and validation support, and cross-functional coordination. We're looking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. 

This position offers strong mentorship opportunities as you work alongside experienced engineers and help bring products from development through customer deployment. 

Level is negotiable based on experience and qualifications. 

Location 

This is an on-site position based in our San Jose, CA office. 

Core Responsibilities 

Firmware Development & Debug 

• Develop and maintain embedded firmware for Ethernet retimers and gearboxes, from low-level hardware abstraction through customer-facing APIs 
• Drive Layer 1 PHY and SERDES debug activities, including link bring-up issues, signal integrity problems, and interoperability failures 
• Support complex IP integration efforts across multiple subsystems within the SoC 
• Implement and optimize link training sequences, equalization tuning, and diagnostic features 
• Assist with software quality gates and validation criteria at each development phase 

Product Rollout & Customer Integration 

• Partner with the software lead to drive product rollout activities from development through production deployment 
• Support customer integration efforts through firmware customization, debug assistance, and technical guidance 
• Investigate field-reported issues and coordinate resolution with internal teams 
• Develop and maintain SDK/API interfaces that enable customer platform integration 

Cross-Functional Collaboration 

• Work extensively with digital SoC teams to understand hardware behavior, register interfaces, and IP integration requirements 
• Collaborate with field applications engineers to support customer bring-up and resolve deployment issues 
• Partner with platform applications teams to ensure firmware meets system-level requirements 
• Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases 
• Provide regular project updates on progress, risks, dependencies, and technical challenges 

What You Bring 

Required Qualifications: 

• BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field 
• 10+ years of embedded C/C++ firmware development in resource-constrained environments 
• Deep understanding of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware design 
• Experience with Layer 1 PHY firmware, SERDES bring-up, or SDK/API development for networking devices 
• Strong proficiency with Linux development tools: gcc/clang, make, bash scripting, gdb, and git 
• Excellent verbal and written communication skills; ability to explain complex technical concepts clearly 
• Demonstrated problem-solving ability and systematic debugging approach on real hardware 
• Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment 

Highly Valued Skills: 

• Experience with PMA, FEC, or related PHY-layer subsystems beyond the PMD/SERDES 
• Familiarity with NIC or switch management software, for system test purposes 
• Exposure to SAI (Switch Abstraction Interface) or OpenBMC 
• Experience with Python for test automation, data analysis, or general scripting 
• Hands-on experience building and maintaining Jenkins CI/CD pipelines and automated test infrastructure 
• Background in retimer or gearbox firmware/API, active electrical cables, or high-speed Ethernet connectivity 
• Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, BERT, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar 
• Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin 
• Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments 
• Experience with RTOS, device drivers, or coroutines 
• Prior technical lead, mentorship, or team lead experience 

Compensation 

Salary range is $185,000 USD - $203,000 USD depending on experience, level, and business need. This role will include a discretionary bonus, competitive equity package, comprehensive health/dental/vision coverage, professional development opportunities, and a culture that values technical excellence, collaboration, and innovation.

Job Description

The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• Minimum 8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).
• Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience developing embedded firmware for PCIe products.
• MQX RTOS or ThreadX Development or enablement.
• High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
• High level of proficiency in Python for automating pre-processors/post-processors and FW QC.
• Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.
• Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).
• Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces
• Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc

Preferred Experience

• Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC)
• Experience with industry forums and collaboration workgroups such as OCP and OpenBMC

The base salary range is $203,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description

We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
  required, and a Maser’s is preferred.
• ≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in US and start immediately.

Required Experience

• Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
  environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
  generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
  writing assertions, cover properties and analyzing coverage data
• Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.
• Must have prior experience on verification with firmware to control and configure the SerDes and related components.

Preferred Experience

• SW debugging for Mix-Signal based designs.
• Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.
• Experience with FPGA-based verification/emulation.

Principal Power and Board Design Engineer 

Overview:
We are seeking a highly skilled and experienced Power and Board Design Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.

Key Responsibilities:

• Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.

• Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance mismatches.

• Develop and implement board-level designs, to meet electrical and mechanical requirements with a deep understanding of PCB layout rules and constraints.

• Implement thermal solutions to maintain optimal operating temperatures for components.

• Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also will be asked to do the same evaluation on overall system level design components.

• Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.

• Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.

• Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.

• Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.

Qualifications:

• Education: Bachelor’s or Master’s degree in electrical engineering or a related field.

• Experience: 8-10 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.

• Technical Skills:

  • Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.

  • Strong understanding of power integrity principles and techniques.

  • Experience with power component selection and vendor collaboration.

  • Hands-on experience with debugging power-related issues using lab equipment.

• Soft Skills:

  • Excellent problem-solving and analytical skills.

  • Strong communication and teamwork abilities.

  • Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Experience with high-speed interfaces such as PCIe, DDR, and USB.

• Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.

• Familiarity with Design for Manufacturability (DFM) considerations.

• Experience in thermal management and reliability analysis.

Why Join Us:

• Work on cutting-edge ASIC designs in a collaborative and innovative environment.

• Opportunity to influence power design strategies and contribute to product success.

• Access to state-of-the-art tools and resources to enhance your skills and career growth.

If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.

Base pay range for this role is $209,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role Overview

Astera Labs is seeking a Principal Product Applications Engineer to join our Aries PCIe Retimer team and serve as a critical technical bridge between our customers and engineering organization. As AI infrastructure demands explode, our Aries Smart Retimers are enabling the high-speed, low-latency PCIe connectivity that powers the world's most advanced data centers—and you'll be at the center of that growth.

In this high-impact role, you'll work directly with hyperscalers, OEMs, and system builders to drive successful adoption of our Aries PCIe products. You'll combine deep technical expertise with customer-facing skills to solve complex system-level challenges, create compelling technical documentation, and influence product direction based on real-world customer needs. This is an opportunity to shape how next-generation AI and cloud infrastructure connects and scales.

You'll collaborate cross-functionally with design engineering, validation, sales, and marketing teams while building strong relationships with customers who are defining the future of computing. If you thrive at the intersection of cutting-edge silicon and customer success, this role offers exceptional visibility and impact.

Key Responsibilities

Customer Technical Engagement

• Serve as the primary technical resource for customers during pre-sales evaluation and post-sales deployment of Aries PCIe retimers
• Deliver technical presentations, product training, and demonstrations to customer engineering teams
• Build trusted advisor relationships with key accounts and drive product adoption

System-Level Debug & Validation Support

• Lead root cause analysis and debugging of complex PCIe signal integrity and protocol issues in customer systems
• Support customer lab bring-up, characterization, and validation activities
• Develop and execute test plans to reproduce and resolve customer-reported issues

Technical Documentation & Enablement

• Create application notes, reference designs, and best practices guides for PCIe system implementation
• Develop collateral that accelerates customer time-to-deployment
• Contribute to product documentation including datasheets and user guides

Cross-Functional Collaboration

• Partner with product management and engineering to translate customer feedback into product requirements
• Support sales teams with technical expertise during customer engagements
• Represent the voice of the customer in internal roadmap and feature discussions

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in applications engineering, technical support, or system engineering roles
• Strong understanding of PCIe architecture, protocol, and electrical specifications (Gen4/Gen5/Gen6)
• Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BERT tools
• Experience debugging high-speed serial interfaces at both the physical and protocol layers
• Excellent written and verbal communication skills with ability to explain complex technical concepts
• Develop and modify firmware using C to implement features, optimize performance, and resolve technical issues
• Travel to customer sites worldwide to provide on-site technical support, conduct system integration, and drive issue resolution

Preferred Qualifications

• Experience with PCIe retimers, redrivers, or similar connectivity components
• Familiarity with server, storage, or GPU system architectures
• Background in signal integrity analysis and simulation tools
• Scripting proficiency (Python, TCL) for test automation and data analysis
• Prior experience working directly with hyperscale or enterprise data center customers
• Track record of creating high-quality technical documentation and application notes

Salary range is $158,400 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Overview
Join our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
• Scripting and automation for ASIC methodology improvement.
• Accountable for quality and overall design success with the support of senior engineers.

Required Qualifications
Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent
• 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
• Track record of delivering high quality digital designs from definition to production.
• Experience with functional and formal verification at block and chip level. 
• Understanding of clocking, CDC and RDC
• Experience with CMOS nodes (≤7nm)

Protocols & Integration:

• Familiarity with high-speed protocols—PCIe, Ethernet, DDR, or similar
• Experience with IP development and integration

Tools & Methodologies:

• Proven SystemVerilog and Python expertise in a production environment
• Familiarity with Synopsys and/or Cadence digital design flows
• Basic understanding of UVM-based verification methodologies

Professional Attributes:

• Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment
• Good communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who adapts quickly to changing requirements
• Customer-focused mindset with the ability to prioritize and work independently to deliver high quality designs.

Preferred Qualifications

• Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus
• Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus

Role Overview
Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.

Key Responsibilities

• Architecture & Technical Leadership
• Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines
• Establish architectural standards and best practices that scale across the design organization
• Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area
• Design Execution & Ownership
• Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up
• Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies
• Own accountability for design quality, schedule, and successful production delivery
• Cross-Functional Collaboration
• Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues
• Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up
• Work with firmware and software teams to optimize hardware-software interfaces
• Mentorship & Process Excellence
• Mentor and develop junior and senior engineers, elevating team technical capabilities
• Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure
• Contribute to organizational knowledge sharing and technical reviews

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure
• Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows
• Track record of delivering multiple high-performance designs to production

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)
• Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems
• Proven contributions to design methodology, CAD automation, or infrastructure improvements
• Experience leading technical teams or driving cross-functional initiatives in data center environments

Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Role Overview

Astera Labs is looking for a Senior Principal Engineering Program Manager to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale.

Key Responsibilities

• Program Ownership & Execution

  • Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM
  • Serve as the single point of ownership for assigned ASIC programs
  • Drive program planning, schedules, budgets, resources, and risk management

• Cross-Functional Leadership & Issue Resolution

  • Lead cross-functional teams across design, validation, product, test, firmware, software, and operations
  • Resolve complex pre-silicon and post-silicon issues through strong technical judgment

• Stakeholder Management & Alignment

  • Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders
  • Champion program execution while aligning engineering delivery with business and customer goals

Basic Qualifications

• BS or MS in Electrical, Electronics, or Computer Engineering
• 10+ years of ASIC product development experience in a semiconductor environment
• Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical Design
• Experience delivering ASICs in advanced nodes (<10nm)
• Proven ability to lead in a matrixed, high-pressure environment
• Strong program management skills; familiarity with MS Project, Jira, Atlassian tools, Scrum/WBS

Preferred Qualifications

• 5 or more years of experience as an ASIC Program Manager
• Experience with PCIe, memory, or high-speed data communication ASICs

Salary range is $205,000 to $250,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.

Overview: 

As a Senior Principal Validation Engineer, you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets.

You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction.

This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives before production.

Key Responsibilities:

• Design, develop, and execute validation plans. Own end‑to‑end post‑silicon characterization and validation strategies, translating product requirements into measurable test objectives, pass/fail criteria, and schedules.
• Drive design reviews and specification alignment. Participate in architecture and design‑spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.
• Lead hands‑on test execution and bring‑up. Perform silicon bring‑up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time‑to‑data.
• Build and maintain automation frameworks. Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed‑signal test benches.
• Debug and optimize system performance. Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs.
• Root‑cause cross‑domain failures. Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system‑level tests; coordinate with design, package, and firmware teams to implement fixes.
• Collaborate with cross‑functional teams. Work closely with mixed‑signal design, firmware, system engineering, and manufacturing to deliver detailed results, root‑cause analyses, optimization recommendations, and formal validation/compliance reports.
• Document findings and improve methodologies. Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base.
• Develop test software and platform integrations. Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites.
• Measure and communicate impact. Define key validation metrics, track coverage and defect trends, and present data‑driven conclusions to stakeholders to influence product direction and release decisions.

Basic Qualifications

• Education — Bachelor of Science in Electrical Engineering required; Master’s degree preferred to demonstrate advanced technical depth and specialization.
• Experience — At least ten years of hands‑on experience in mixed‑signal, high‑speed lab environments, executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real‑time oscilloscopes, sampling scopes, TDRs, and VNAs.
• Software Skills — Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.
• Retimer Expertise — Practical experience bringing up and debugging retimers, including equalization tuning, pass‑through operation, clocking strategies, and reset and link sequencing.
• High‑Speed Signaling Knowledge — Deep understanding of NRZ and PAM4 architectures and the ability to investigate jitter sources, CDR and PLL behavior, equalization techniques such as DFE, CTLE, and FFE, as well as crosstalk and power integrity issues.
• Post‑Silicon Validation — Proven track record in post‑silicon validation and bring‑up of high‑speed PHYs or retimers, with experience developing characterization flows and validating silicon against specifications.
• Circuit Block Familiarity — Solid working knowledge of key high‑speed building blocks including PLLs, CTLE, DFE, transmitter equalization, and PAM4 signaling fundamentals.
• Analytical Problem Solving — Exceptional troubleshooting skills with the ability to isolate and narrow complex, multi‑layer failures across analog, digital, firmware, and package domains.
• Communication — Excellent written and verbal communication skills for clear documentation of findings, presentation of root cause analyses, and collaboration with cross‑functional teams.

Preferred Experience:

• Mixed‑signal system testing and validation — Demonstrated experience in end‑to‑end mixed‑signal system testing, characterization, validation, and compliance activities, including developing test plans, executing characterization flows, and producing formal compliance reports.
• Signal integrity instrumentation and techniques — Hands‑on proficiency with signal integrity test equipment and methodologies, including BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, and advanced probing techniques for channel and package analysis.
• Ethernet standards familiarity — Working knowledge of IEEE 802.3 family standards and practical experience validating Ethernet PHYs, link training, autonegotiation, and compliance testing across relevant speeds and media types.
• Serial protocol expertise — Practical understanding of common serial interfaces such as I2C, I3C, SPI, UART, and other control/status buses used for device bring‑up, firmware interaction, and system integration.
• Cross‑discipline collaboration — Proven ability to translate SI/PI simulation results into testable lab plans, collaborate with design and firmware teams to close the loop on issues, and document findings that drive design or process improvements.

Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.

The base salary range is USD 205,00 - USD 255,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Role Overview

Astera Labs is seeking a Contract Recruiter to join our Talent Acquisition team in San Jose, California. As we continue to scale rapidly to meet the explosive demand for AI infrastructure connectivity solutions, this role will be instrumental in identifying and attracting top-tier talent across the organization.

In this fast-paced, high-impact role, you will partner closely with hiring managers to understand their talent needs and execute full-cycle recruiting strategies. You'll play a critical role in building the teams that are shaping the future of data center connectivity, working on requisitions spanning engineering, operations, and corporate functions. This is an exciting opportunity to join a hyper-growth company at the forefront of the AI revolution.

Key Responsibilities

• Full-Cycle Recruiting
  • Manage end-to-end recruitment process from intake to offer acceptance across multiple requisitions
  • Source, screen, and assess candidates using creative sourcing strategies and multiple channels
  • Deliver an exceptional candidate experience that reflects Astera Labs' culture and values
• Stakeholder Partnership
  • Partner with hiring managers to understand role requirements, team dynamics, and hiring priorities
  • Provide market insights, compensation benchmarking guidance, and talent landscape intelligence
  • Drive weekly hiring syncs and maintain clear communication on pipeline progress
• Process & Operations
  • Maintain accurate and up-to-date candidate records in Greenhouse ATS
  • Ensure compliance with all hiring policies and procedures
  • Contribute to process improvements and recruiting best practices

Basic Qualifications

• Bachelor's degree or equivalent experience
• 3+ years of full-cycle recruiting experience, preferably in the technology or semiconductor industry
• Experience with applicant tracking systems (Greenhouse preferred)
• Strong sourcing skills using LinkedIn Recruiter, Boolean search, and other channels
• Excellent communication and interpersonal skills
• Ability to manage multiple requisitions in a fast-paced environment

Preferred Qualifications

• Experience recruiting for engineering and technical roles in hardware, firmware, or semiconductor companies
• Background in high-growth startup or scale-up environments
• Familiarity with AI infrastructure, data center, or connectivity technologies
• Strong organizational skills and attention to detail
• Proven ability to build relationships with hiring managers and candidates alike

Salary range is $50 to $75/hour depending on experience, level, and business need.

About Astera Labs

Astera Labs is a rapidly growing semiconductor company redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions—built on PCIe®, CXL™, Ethernet, and custom fabrics—enable seamless data movement across compute, memory, and storage. As part of our team, you'll help validate the silicon that powers the world's most advanced AI platforms.

Role Overview

As an Entry-Level System Validation Engineer on the Taurus team, you will validate Astera Labs' Taurus Ethernet Smart Cable Modules and Taurus ASICs. You'll work on chip bring-up, system-level debug, and interoperability testing across real-world AI server and networking platforms, collaborating closely with electrical validation, firmware, and product applications teams.

Key Responsibilities

• Execute system validation test plans for Taurus Ethernet Smart Cable Modules.
• Perform chip bring-up and debug for Taurus ASICs in lab environments using oscilloscopes, protocol analyzers, BERTs, and network switches
• Validate high-speed interconnects and AI fabrics in custom silicon, including signal integrity, link training, FEC stats, and protocol compliance
• Collaborate with electrical validation, firmware, and product applications teams to root-cause issues and drive resolution
• Document validation results, debug findings, and contribute to bring-up notes and test reports

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• Strong academic foundation in circuit analysis, signals and systems, electromagnetics, or high‑speed digital design through coursework and labs
• Familiarity with PCIe®, CXL™, or Ethernet standards
• Familiarity with fundamental signal‑integrity concepts such as eye diagrams, jitter, noise, impedance, and transmission lines
• Exposure to electrical lab equipment (e.g., oscilloscopes, logic analyzers, network analyzers)
• Experience using scripting or programming languages such as Python, MATLAB, TCL, or C/C++
• Comfortable working with lab tools and debugging hardware
• Strong analytical and communication skills

Preferred Skills

• Exposure to post-silicon validation or bring-up of connectivity IP blocks
• Knowledge of signal integrity analysis and eye diagram interpretation
• Familiarity with Linux systems, shell scripting, and version control (Git)
• Understanding of AI workloads and how interconnect bandwidth impacts performance

Figure is an AI Robotics company developing a general purpose humanoid. Our Humanoid is designed for corporate tasks targeting labor shortages and jobs that are undesirable or unsafe. We are based in San Jose, CA and require 5 days/week in-office collaboration. 

We are seeking a Robotics Integration Engineer to drive system-level integration and validation across hardware, firmware, controls, AI, perception, and software. You will plan, execute, and oversee subsystem integration and full-system bring-up, ensuring reliable performance and consistency across the entire robot ecosystem. This is a highly technical, hands-on role focused on debugging, root cause analysis, and validating system functionality to make humanoid robots perform reliably in the real world.

Responsibilities: 

• Integrate and validate system-level changes across hardware, controls, behavior, AI, and perception subsystems.
• Architect and execute bring-up, validation, and end-of-line (EOL) test processes for humanoid robots.
• Develop test tools and automation scripts in C++ and Python to streamline integration and data analysis.
• Design and run validation plans that stress full-robot functionality across real-world use cases.
• Debug and triage cross-disciplinary issues spanning mechanical, electrical, firmware, and software systems.
• Collaborate with design, controls, behaviors and software teams to define testable behaviors and verify subsystem performance.
• Instrument robots using diagnostic tools (oscilloscopes, logic analyzers, telemetry logs) to characterize performance and identify failure modes.
• Build dashboards, metrics, and reports to track system performance and fleet health over time.
• Document integration workflows, test results, and lessons learned to improve future build efficiency.
• Contribute to the automation of regression testing and continuous validation across the robot fleet.

Requirements: 

• Bachelor’s or Master’s degree in Robotics, Electrical Engineering, Mechanical Engineering, Computer Science, or a related field.
• 3–5+ years of experience working with complex robotic or electromechanical systems.
• Proficiency in C++ and Python for software development, scripting, and debugging.
• Strong system-level understanding across hardware, firmware, and software layers.
• Experience with Linux, Git, and standard diagnostic tools (oscilloscope, multimeter, log analyzers).
• Hands-on experience validating real-time control systems, behaviors, or perception pipelines.
• Ability to thrive in a fast-paced, lab-focused R&D and production environment.

Bonus Qualifications: 

• Experience with humanoid or legged robots.
• Familiarity with ROS2, behavior trees, or motion planning frameworks.
• Background in hardware bring-up, calibration systems, or production-level validation.
• Exposure to high-reliability or safety-critical robotic systems.

The US base salary range for this full-time position is between $170,000 - $250,000 annually.

The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended. 

We are looking for a Lead RTL Design Engineer to own microarchitecture definition and RTL implementation across the dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and standard peripheral IP (RiscV, NVM, I2S, I2C) integration. You will work from architecture spec through synthesis-ready RTL, collaborating with architects, microarchitects, DV leads, physical design, and firmware teams to tape out an industry leading power-efficient SoC.

This is a unique opportunity to be a part of a newly formed HW engineering org and have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities 

• Microarchitecture definition (core focus): Own the design and definition of processor and compute-unit microarchitecture, including dataflow pipelines, execution units, and interfaces. Set performance, power, and area targets, and guide the team toward achieving them.
• On-chip interconnects and system integration: Define and drive the design of on-chip networks and data movement across the fabric, balancing performance, scalability, and implementation constraints in collaboration with physical design.
• Memory subsystem & system architecture: Define the interface to the memory subsystem, including data movement, ordering, and synchronization behavior, ensuring a clean and scalable model for software and future system expansion.
• Reconfiguration and execution model: Lead the architecture of configuration, scheduling, and execution of workloads on the fabric, including multi-kernel support and interaction with host systems.
• Power management and low-power design: Drive power architecture across the design, including clocking, reset, power domains, and low-power strategies to meet aggressive energy and efficiency goals.
• HW/SW co-design: Collaborate closely with compiler and software teams to define the hardware execution model, ensuring efficient mapping of workloads onto the architecture.

Specifications, Documentations and Reviews: Author and own uArch specification documents for assigned blocks; drive design reviews with architecture, compiler, DV, and physical design stakeholders.

• Mentoring and process improvement: Mentor senior and junior RTL engineers; review RTL, flag microarchitecture risks, and enforce coding style and lint-clean standards across the team.
• Driving PPA Metrics: Participate in PPA analysis loops: synthesize blocks regularly, review area/timing/power reports, and make data-driven tradeoffs against performance and feature requirements.
• DV Collaboration: Collaborate with DV leads to define/review verification plans; provide directed test scenarios for graph execution corner cases, back-pressure conditions, and power state transitions.
• Silicon Bring-up: Support silicon bring-up: contribute scan/ATPG guidelines, review DFT insertion, and provide RTL-level debug assistance during lab validation.

Required Qualifications & Experience

• 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems  or peripheral integration on a processor or accelerator SoC.
• Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware; able to design complex state machines, arbiters, token flow controllers, and datapath logic from scratch.
• Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures; familiarity with the hardware challenges of token-based firing-rule evaluation and producer-consumer synchronization.
• Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces.
• Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic.
• Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level.
• Experience taking RTL through synthesis and timing closure; ability to read and act on SDC constraints, STA reports, and synthesis QoR summaries.
• Strong written communication skills; able to produce uArch specs and design review material independently.
• Experience with memory compiler toolchains

Desired Qualifications & Experience Requirements 

• Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture with explicit producer-consumer token management.
• Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations.
• Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases.
• Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and the RTL design choices they necessitate.
• Familiarity with functional safety standards (ISO 26262, IEC 61508) as applied to execution fabric error detection and power domain isolation.
• Exposure to AI framework graph formats (ONNX, TFLite) and understanding of how graph compilation maps to hardware execution primitives.
• Tape-out credits on an edge-AI, IoT, or wearable SoC at 12nm or below.
• Experience with formal verification of flow-control logic, deadlock freedom, or bus protocol compliance.

We offer a competitive salary for this role, generally ranging from $160,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Figure is an AI robotics company developing autonomous general-purpose humanoid robots. The goal of the company is to ship humanoid robots with human level intelligence. Its robots are engineered to perform a variety of tasks in the home and commercial markets. Figure is headquartered in San Jose, CA.

We are looking for an Firmware Engineer Intern for Summer 2026 to support the implementation and test of key aspects of our Humanoid software.

Responsibilities:

• Deliver high quality C/C++ code in a real-time embedded environment.
• Bring up, debug, and validate firmware on the Humanoid hardware platform, such as actuators, sensors, power distribution system.
• Optimize performance of firmware to meet product requirements.
• Develop test scripts in Python to support test automation or robot calibration.
• Work cross functionally with System Integration, Software Test, and Embedded Software teams to successfully and autonomously ship new features.
• Contribute to the integration of projects into the Continuous Integration and Continuous Deployment (CI/CD) infrastructure.
• Support hardware/software integration in the lab.

Requirements:

• Graduate student, senior student, or recent graduate in Computer Engineering or related field.
• Minimum 10 weeks internship, 1 to 2 terms preferred.
• Ability to showcase extra-academic activities working on hardware/software projects.
• Fluent with C/C++ and Python.
• Good knowledge of computer architecture and real-time operating systems
• Familiar with communication buses and protocols like CAN, SPI, I2C, UART etc.
• Comfortable using lab instruments (Oscilloscopes, logic analyzers…) and debugging tools.

Bonus Qualifications:

• Experience with low level communication protocol driver development, Ethernet and CAN preferred.
• Demonstrated taking features or products from cradle to grave with high levels of ownership.
• Experience with motor control systems.
• Experience with the Bazel build system.
• Experience with Docker containers.

About the role

Muon seeks a Senior Technical Program Manager to lead Muon Space’s Programs efforts, responsible for successfully delivering solutions, products, and technology while managing cost and schedule baselines contracts with the U.S. Government and Commercial Organizations. The Program Manager will be a key member of the Mission Engineering team and collaborate closely with Muon Space’s engineering, business, legal, finance, and operations departments. You will also support the portfolio's growth by fostering organic growth on existing contracts and supporting captures of new contracts. 

As a Technical Program Manager at Muon Space, you delight our customers and users with high-quality products and solutions delivered on time and on budget, meeting our contractual obligations. You are cognizant of how all the pieces need to come together for successful program execution and can turn that into well-organized roadmaps, schedules, and budgets that you then track throughout the program lifecycle. You will be responsible for monitoring and ensuring successful execution of Muon’s contracts that you manage. You will support business development through proposals, RFI responses, customer engagement, and organic growth.

This role is based in San Jose with a hybrid schedule (3 days per week in-office).

Responsibilities

• Lead a multidisciplinary aerospace development effort, driving day-to-day execution of the program
• Engage with internal and external stakeholders to plan and coordinate the resources necessary to execute the program
• Synchronize a diverse technical team by establishing tools, practices, and process
• Participate in technical discussions, ask probing questions, and work with the team to pull together scoping, schedules, and solutions to issues
• Track and report program metrics on schedule, resource, cost, risk, and technical performance
• Serve as the face of the company to customers, subcontractors and suppliers

Qualifications

• 5+ years relevant experience in program management
• B.S. in an engineering discipline, M.S. or Ph.D. preferred
• Track record of successfully delivering complete systems (hardware, firmware, software, algorithms) on time, to scope, with high quality.
• Experience in development and/or program management of satellite based systems. Ability to instantiate and manage integrated master schedules.
• Expertise in modern, cloud-based productivity tools
• Excellent analytical and interpersonal skills, with ability to work successfully across all engineering disciplines.
• Experience in vendor and contract management

Nice-to-have Skills

• System engineering and experience with inter-discipline technical trade study
• Experience working with scripting languages (e.g. Python, Julia) and database queries (e..g SQL, BigQuery)  for data integration, analysis, and dashboarding.
• Experience in a fast-paced, startup environment
• Experience managing and growing teams

Salary

The salary range for this role is $175,000 - $208,000 plus a competitive equity grant and comprehensive benefits package. Final compensation will be based on skills, qualifications, experience, and geographic location as assessed during the interview process.

San Jose, CA  

We are developing the technologies and aircraft to power the future of advanced aviation. We plan to provide customers with advanced aircraft and. related technologies and services in the United States and internationally in both the commercial and defense sectors. We unveiled our first planned production aircraft, an electric vertical take-off and landing (“eVTOL”) air taxi, called Midnight, in November 2022. In December 2024, we launched Archer Defense, to develop a next-generation aircraft for both defense and civilian applications. We are first and foremost working to commercialize our Midnight air taxi in and around major cities around the world.  

Our strategy has been and continues to be to hire top talent across various disciplines to build the best products and deliver the best services possible. We believe we have assembled a world-class team with extensive experience across the key disciplines. We embrace collaboration and creativity and encourage the iteration of ideas to address the complex challenges our industry faces. We believe our team and culture differentiates us versus our competitors and will be a key driver of our long-term success. Furthermore, we are committed to making safety a part of everything we do. Our approach to safety is a part of every aspect of our company, from design and engineering to our manufacturing, flight test, and aircraft operations.

What you’ll do:  

• ​Embedded development and verification of safety critical software components for the aircraft Charge Control Unit
• Design and implement charge control systems with a focus on interfacing embedded software with high-voltage electrical components and analog/digital circuitry
• ​Collaborate with systems engineers to decompose item requirements into high-level and low-level software requirements in compliance with DO-178C  
• Work with a multi-disciplinary team to develop, integrate, verify and certify complex hardware/software systems 
• Develop and implement fault detection and diagnostic algorithms in software to identify and respond to hardware-level events such as short circuits, and sensor failures.
• Analyze hardware schematics and perform signal integrity and power distribution network design to inform embedded software development
• Participate in the definition and documentation of streamlined software development and verification processes supporting the certification of safety critical software to comply with DO-178C 
• Foster team collaboration to promote and support personal development 
• Excellent verbal and written interpersonal communication  
• Excellent Organizational skills  
• Collaborative mindset  
• Passion for learning and problem solving  

What you need:  

• 6+ years of experience in a related field  
• At least a BS in Electrical Engineering, Computer Engineering, Computer Science, or related degree
• Proficiency in C/C++ for developing firmware that controls and monitors electrical subsystems, including voltage regulation, fault detection, and sensor data acquisition
• Hands-on experience with ISO 15118-2/-3/-30, SAE J1772, HomePlug AV Specification Standards, or related industry standards.
• Familiarity with safety critical software development standards (DO-178C, ISO 26262, ASIL) to high criticality levels (DAL-A/B or ASIL C/D) 
• Hands-on experience through the Full Software Development Life Cycle (development through verification and or certification/production) 
• Hands-on understanding of low-level communication standards and protocols (RS-422/485, CAN, ARINC-429, AFDX, Ethernet, TCP/IP, SPI, I2C etc…) and their hardware implementation
• Working knowledge of sensor technologies and measurement techniques for high-voltage systems (e.g., current sensing, voltage monitoring, temperature measurement)  
• Familiarity with diverse tools and technologies used for the development, testing and analysis  Experience working on Charge Control systems  
• Excellent organizational and communication skills  

Bonus qualifications  

• Experience with MATLAB/Simulink and circuit simulation tools such as SPICE, LTspice, or PLECS
• Experience with modeling tools/certification (DO-331)  
• Familiarity with modeling tools like UML or SysML  
• Working with Real Time Operating Systems (RTOS)  
• Demonstrated experience with initial board bring-up, hardware debugging, and using lab equipment (oscilloscopes, logic analyzers, power supplies).  
• Experience with the HW in the Loop, SW in the Loop or MIL 2 

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications  

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $140,000 - $180,000. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience. 

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

What you’ll do:

1. Lead the hardware and software integration and development tests for the high performance aerospace power electronics (DC-DC, DC-AC, AC-DC) products
2. Responsible to specify, design, and perform testing of electrical aspects of product modules and boards implemented in airborne power conversion and distribution systems
3. Clearly define test plans and procedures, perform test cases and generate test reports for board/module bring-up, design verification and system integration, and support other tests including end-of-line, environmental / electrical stress and safety-of-flight
4. Lead tester designs from conception into production while working with cross-functional teams. Start to finish ownership of tester hardware to characterize / validate features, functions and performance of complex high voltage converters – from specification to design, build, manufacturing, and operation
1. Create development test cases for modules and boards
2. Tester design, covering both hardware and software needs
3. Test station build, bring-up, troubleshoot, operation and maintenance
4. Test station data consolidation, visualization, review and analysis
5. Conduct failure analysis of the modules / boards to understand the root cause and lead the cross-functional team effort to identify the resolutions
6. Support flight test data review and analysis for airborne power electronics products
7. Drive continuous design and performance improvement of power electronics products, and provide constructive and accurate feedbacks to the teams

What you need:

• BS Degree in Electrical Engineering with 3+ years or MS with 1+ years of experience in related fields
• Sound knowledge and hands-on experience in integration and testing of high voltage power electronics converters, mixed signal boards, and power / gate drive boards
• Good understanding of power electronics components and modules, including power semiconductors, gate drivers, magnetic components (transformers, inductors), passive components, connectors, device characterization, converter topologies (DC-DC, DC-AC, AC-DC), mechanical packaging, thermal management, modulation techniques, and control methods
• Experience converting requirements and schematics into test plans with pass / fail criteria
• Familiarity with automated test station hardware and software tools (e.g. NI, Labview)
• Master of all types of lab instruments: power supplies, oscilloscope, signal generators, network analyzer, electronic loads, CAN tools, etc.
• Experience performing the design and build of test stations
• Experience managing vendors that are performing the design and build of test stations
• Experience performing power electronics board and module bring-up and design verification test
• Experience on root cause analysis of power converter module / board failures
• Exceptional analytical problem solving skills for complex hardware / software and attention to details
• Excellent organizational and communication skills

Bonus Qualifications: 

• Hands on experience with DO-160G testing
• Embedded firmware development experience
• Experience with Python, C, C++, Matlab
• Experience in using circuit simulation software, schematic capture, and PCB layout software (e.g. Spice, Altium Designer)
• Passion for aviation and eVTOLs

At Archer, we aim to attract, retain, and motivate talent with the skills and leadership needed to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s strategy. For this position, we are targeting a base pay range of $105,600 - $145,200. Actual compensation offered will be determined by job-related knowledge, skills, and experience.        
   

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

What You’ll Do

• Perform Worst Case Circuit Analysis (WCCA) and margin analysis on control and measurement circuits, including microcontrollers, resolver interfaces, PMICs, power trees, voltage/current sensors, and digital communications (CAN, SPI, etc).
• Conduct circuit simulations using SPICE and MATLAB to validate designs across component tolerances, temperature extremes, and voltage variations.
• Lead Design Failure Mode and Effects Analysis (DFMEA) for control and sensor boards, working cross-functionally with Safety and Reliability teams to identify and mitigate risks.
• Analyze effects of single-event upsets and latch-ups on critical system functionality.
• Perform electrical stress analysis and component derating analysis. 
• Support the design team with analytical validation of power management architectures, sensor interfaces, and MCU-based control circuits.
• Collaborate with hardware, controls, firmware, safety, and reliability teams to ensure designs meet aerospace performance and certification requirements.
• Generate analysis reports and technical documentation to support design reviews and DO-254/DO-160 compliance.

What You Need

• Bachelor's or Master's degree in Electrical Engineering or related field
• 4+ years of experience in circuit analysis and simulation for mixed-signal control systems
• Proven expertise conducting WCCA, DFMEA, and margin analysis on MCU-based boards, sensor interfaces, or power management systems
• Proficiency with SPICE simulation tools (PSpice, LTSpice, HSPICE) and MATLAB/Simulink
• Strong understanding of MCU control circuits, analog sensor interfaces (resolvers, voltage/current sensors), PMICs, power sequencing, and component derating principles
• Experience working cross-functionally with Safety and Reliability teams on risk assessment
• Understanding of DO-254, DO-160, or similar aerospace/automotive safety standards
• Excellent analytical and communication skills in multidisciplinary environments

Bonus Qualifications

• Experience with aerospace or automotive electrical systems analysis
• Hands-on experience with DO-254 development and DO-160G testing
• Experience with high-voltage power electronics for battery, motor, or inverter systems
• Proficiency with analysis automation (Python, MATLAB scripting)
• Passion for aviation and eVTOLs

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $134,000.00 - $188,00.00. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Senior Incident Response Engineer

Job Overview

Archer is building the future of urban air mobility. Our intellectual property and safety-critical systems are high-value targets for nation-state actors and ransomware groups. A single incident could impact aircraft certification or delay FAA approvals. You are the first line of defense when preventive controls fail. Your work ensures our security maturity is "audit-ready" for investors, government agencies, and the DoD.

Archer is seeking a Senior Incident Response Engineer to lead our detection and remediation efforts across enterprise and aviation technology environments. In this high-visibility role, you will serve as the primary technical liaison between Archer’s internal security team and our Managed Security Service Provider (MSSP). You will be responsible for translating security alerts into actionable threat intelligence and coordinated response actions while ensuring strict compliance with NIST SP 800-171, CMMC Level 2, and SOX ITGC requirements.

This is a highly technical, hands-on position. You will lead investigations from initial detection through recovery, produce forensic reports for legal and regulatory stakeholders, and design automated response playbooks. Because Archer operates in a regulated aerospace environment, you must balance rapid response with meticulous evidence preservation.

Key Responsibilities

• MSSP Liaison & Alert Management: Serve as the internal SIEM engineer and MSSP relationship owner. Validate alerts by independently querying SIEM data using YARA-L, SPL, or KQL.
• Incident Response & Forensics: Lead technical response for breaches, malware, and insider threats. Execute containment (isolating endpoints, blocking IPs) and conduct deep-dive forensics including memory analysis and disk imaging.
• Threat Hunting: Execute proactive hunts using EDR telemetry and the MITRE ATT&CK framework to identify lateral movement or persistence mechanisms that evade automated detections.
• Detection Engineering & SOAR: Develop and tune custom detection rules. Design SOAR workflows to automate evidence collection and remediation, reducing MTTD and MTTR.
• Compliance & Audit Support: Design log retention policies to satisfy NIST 800-171 AU and CMMC IR practices. Facilitate external audits by providing evidence of root cause analysis and post-incident reviews.
• Continuous Improvement: Facilitate tabletop exercises for leadership and engineering teams. Lead post-incident reviews to document lessons learned and drive strategic program improvements.

Required Qualifications

• Experience: 5+ years of direct experience in Incident Response or SOC roles, with proven experience managing MSSP SLAs and performance.
• OS Internals: Demonstrated expertise in Windows, Mac, and Linux internals (process behavior, registry analysis, and log sources).
• Scripting: Proficiency in Python, PowerShell, or Bash to automate analysis workflows and evidence collection.
• SIEM/SOAR Mastery: Hands-on experience with platforms like Google SecOps (Chronicle), Splunk, or Microsoft Sentinel, and SOAR tools (Cortex XSOAR or Phantom).
• Threat Intelligence: Knowledge of CTI standards (STIX/TAXII) and the ability to translate actor TTPs into actionable detection logic.
• Communication: Ability to produce clear, concise written reports for Legal, HR, and regulatory stakeholders that translate technical findings into business risk.

Preferred Qualifications

• Advanced Malware Analysis: Experience with static/dynamic analysis and reverse engineering using IDA Pro, Ghidra, or REMnux.
• Aerospace/Regulated Industry: Familiarity with ITAR compliance, CUI handling, or aviation-specific threats (avionics tampering, firmware security).
• Cloud IR: Experience conducting forensic analysis within AWS, Azure, or GCP environments.
• Certifications: GCIH, GCFA, GCIA, GNFA, or equivalent advanced forensic certifications.

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $144,000.00 - $180,00.00. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is proud to be an Equal Opportunity employer committed to diversity and inclusivity in the workplace. All aspects of employment are decided on the basis of merit, qualifications, and business needs. We do not discriminate based upon race, color, religion, sex, sexual orientation, age, national origin, disability status, protected veteran status, gender identity or any other characteristic protected by federal, state or local laws.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

The Propulsion Electronics Team at Archer is seeking a Staff Electrical Engineer to lead the architecture and design of mission-critical controller boards for our electric engines and generators.

What You’ll Do

• Own the technical roadmap and architecture for engine and generator controller boards from concept through flight certification.
• Drive microcontroller selection, processing architecture, and memory management to meet real-time performance and safety requirements.
• Design low-voltage power distribution trees, precision analog signal conditioning circuits, and sensor interfaces for temperature, current, voltage, position, and vibration sensing in harsh environments.
• Architect and validate multi-protocol communication systems including CAN, Ethernet, SPI, I2C, and UART for integration with aircraft subsystems.
• Develop fault detection, isolation, and recovery logic in hardware to ensure fail-safe operation and meet functional safety requirements.
• Serve as technical authority for controller design, leading design reviews, mentoring engineers, and ensuring best practices for reliability and manufacturability.
• Collaborate with firmware, power electronics, mechanical, systems, and safety teams to integrate controllers into the propulsion system.
• Develop and execute validation plans using simulation and testing to meet performance, EMC, and certification requirements.

What You Need

• Electrical Engineering Degree or equivalent experience.
• 8+ years experience in complex electronics and control system design.
• Proven expertise in architecting microcontroller-based control systems from concept to production.
• Deep knowledge of low-voltage power design, analog signal conditioning, and communication protocols including CAN and Ethernet.
• Experience designing fault-tolerant, redundant electronics for safety-critical applications.
• Strong understanding of PCBA design for EMC/EMI mitigation, signal integrity, and thermal management.
• Demonstrated technical leadership and ability to mentor engineering teams.

Bonus Qualifications

• Experience designing electrical systems for aerospace or automotive requirements
• Experience in embedded programming
• Experience designing PCBAs for high power and high voltage power converters and/or inverters
• Hands on experience with aviation DO-160G testing and DO-254 development
• Passion for aviation and eVTOLs

At Archer, we aim to attract, retain, and motivate talent with the skills and leadership needed to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s strategy. For this position, we are targeting a base pay range of $170,800 - $225,600. Actual compensation offered will be determined by job-related knowledge, skills, and experience.        

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Efficient is looking for a seasoned Design Verification & Emulation Manager to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers.

This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond! 

Key Responsibilities 

• Define end-to-end verification strategy from block-level through full-chip simulation to emulation and prototyping
• Own UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoption
• Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling
• Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising
• Deliver pre-silicon platforms for early software development in partnership with firmware and software teams
• Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments
• Own functional coverage models and sign-off criteria, driving closure across simulation and emulation combined
• Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution
• Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership
• Build, mentor, and scale a high-performing team of verification and emulation engineers
• Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness
• Represent verification and emulation in tapeout readiness reviews and program-level decision forums
• Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams
• Manage emulation lab infrastructure, including hardware resources, licensing, and vendor relationships
• Evaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques.
• Define right DV  mix for in-house  vs outsourcing to 3rd party vendors. Coordinate 3rd party vendor resources towards achieving project goals.

Required Qualifications & Experience 

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
• Experience: 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
• Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.
• Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
• Languages & Tools: Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
• SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
• Leadership: Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.
• Execution: Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).

Preferred Qualification

• Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.
• Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.
• Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).

We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

About the role

Muon seeks a Staff Software Engineer to join our flight software team. The ideal candidate is an expert software developer with significant previous experience architecting and building robust bare-metal / RTOS embedded devices or appliances. In this role, you will both set architectural direction for, and lead design, development, integration, and testing of much of the software and firmware that runs on our orbiting satellites. This position is based at our San Jose, CA office.

Responsibilities

• Leading member of the team defining and building Muon’s satellite bus platform
• Define and architect design and execution against the basic concepts and requirements of our missions to get the right software and firmware on orbit
• Design, bring up, and support the embedded software environment that runs in our satellite flight systems and peripherals using ARM Cortex-M CPUs.
• Guide evaluation and selection of technologies for our software foundation
• Write application, platform, and driver functionality in our flight software environment and set the standards for how others use it
• Build the architectural patterns, shared libraries, services and technical strategy documents that enable high-quality and high-velocity development of flight software
• Integrate compute and peripheral subsystems in both software and hardware
• Collaborate with hardware team members on the design and bring up of Muon hardware
• Align team roadmaps with product requirements and mission needs
• Define metrics aligned with critical company goals and enable the team to achieve aggressive goals
• Ensure effective software and hardware-in-the-loop test strategies
• Mentor senior engineers

Qualifications 

• B.S., M.S., or Ph.D. in computer science, electrical engineering, or related field
• 10+ years experience as a software engineer in a team environment
• Strong C/C++ programming, with practical familiarity of other languages
• Great embedded systems fundamentals: distributed system architecture, resource-efficient design, low-level drivers, bit manipulation, responsive software and IRQ handling, RTOS frameworks, I/O and communication buses.
• Integration and control of external hardware devices
• Read and understand hardware data sheets
• Excellent communication and presentation skills

Nice-to-have Skills

• Experience working in flight software or some closely related domain
• Rust and Python experience
• Knowledge of industry-standard data formats and schemas (ProtoBuf, YAML, JSON, etc)
• Familiarity with a Linux-based development environment
• Experience with one or more of: embedded linux, FPGA, HW design, RF communication systems, cloud/server infrastructure, network architecture.
• End-to-end development from product concept to delivery to customer/market.

Salary

The salary range for this role is $210,000 - $234,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process. 

Figure is an AI robotics company developing autonomous general-purpose humanoid robots. The goal of the company is to ship humanoid robots with human level intelligence. Its robots are engineered to perform a variety of tasks in the home and commercial markets. Figure is headquartered in San Jose, CA.

We’re seeking an Embedded Systems Integration Engineer to build the backend infrastructure that validates the interaction between our hardware, firmware, and software. You will be the connective tissue across disciplines: owning how changes to firmware or software are tested against real hardware. Your work ensures we ship reliable, integrated systems that just work.

This is a hands-on role where you will design and implement automated test frameworks, bring-up flows, and validation pipelines for embedded subsystems. You'll be responsible for catching regressions early, enabling fast iteration, and giving clear system-level pass/fail signals across the stack.

Key Responsibilities

• Architect test infrastructure that exercises end-to-end functionality of embedded systems across hardware, firmware, and software boundaries.
• Develop backend systems (Python, CLI tools, internal APIs) to run tests, log results, and determine pass/fail conditions.
• Bring up and validate  subsystem and system level changes, tracking changes in behavior and performance across releases.
• Automate testing pipelines for regression detection and continuous integration.
• Debug and triage failures across layers—hardware faults, firmware bugs, or software integration issues.
• Collaborate with firmware, software, and hardware teams to define interface contracts and testable behaviors.
• Instrument devices under test using scopes, logic analyzers, and custom harnesses to characterize system response.

Minimum Qualifications

• Bachelor’s in EE, CE, CS, or a related field.
• 3+ years of experience working with embedded systems.
• Strong understanding of how firmware interacts with hardware peripherals (I2C, Ethernet, SPI, CAN, UART, ADCs, GPIO, etc.).
• Proficiency in Python or similar scripting language for test automation.
• Experience bringing up custom embedded boards and working across firmware/software stacks.
• Familiarity with Linux-based development environments.

Preferred Qualifications

• Experience with CI/CD tools (e.g., GitHub Actions, Jenkins, TeamCity).
• Knowledge of test automation frameworks (e.g., PyTest, Robot Framework).
• Exposure to hardware-in-the-loop (HIL) systems.
• Familiarity with board-level validation, power-on sequencing, or sensor verification.
• Prior experience in robotics, automotive, aerospace, or other complex embedded systems.
• Comfort working hands-on at the bench with test equipment.

The US base salary range for this full-time position is between $140,000 and $180,000 annually.

The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended. 

About the role

Muon seeks a Flight Software Engineer to join our satellite flight software team. The ideal candidate is a self-motivated versatile software developer with significant previous experience developing robust bare-metal / RTOS embedded devices or appliances. In this role, you will design, develop, integrate, and test the software and firmware that runs on our orbiting satellites. This position is based at our San Jose, CA office.

Responsibilities

• Integral member of the team defining and building Muon’s satellite bus platform
• Translate concepts and requirements into design and working implementations, supporting through to on-orbit operations
• Design, bring up, and support the embedded software environment that runs in our satellite flight systems and peripherals using ARM Cortex-M CPUs.
• Participate in evaluating and selecting technologies for our software foundation
• Write application, platform, and driver functionality in our flight software environment and teach others how to use it
• Integrate compute and peripheral subsystems in both software and hardware
• Collaborate with hardware team members on the design and bring up of Muon hardware
• Collaborate with software team members to set flight software architecture, select infrastructure and tools, and communicate with cloud backends.
• Participate in developing software and hardware-in-the-loop test strategies

Qualifications 

• B.S., M.S., or Ph.D. in computer science, electrical engineering, or related field
• 5+ years experience as a software engineer in a team environment
• Strong C/C++ programming, with some practical familiarity of other languages
• Great embedded systems fundamentals: resource-efficient design, low-level drivers, bit manipulation, responsive software and IRQ handling, RTOS frameworks, I/O and communication buses.
• Integration and control of external hardware devices
• Read and understand hardware data sheets
• Excellent communication and presentation skills

Nice-to-have Skills

• Knowledge of industry-standard data formats and schemas (ProtoBuf, YAML, JSON, etc)
• Familiarity with a Linux-based development environment
• Experience with one or more of: embedded linux, FPGA, HW design, RF communication systems, cloud/server infrastructure, network architecture.
• End-to-end development from product concept to delivery to customer/market.

Salary

The salary range for this role is $156,000 - $186,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process.