Senior, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab is  seeking Senior CPU Architecture & Performance Engineer to contribute to performance analysis and microarchitectural optimization of current and next-generation CPU (RISC-V) cores. This role emphasizes hands-on analysis, modeling, and close collaboration with architects and design teams to improve performance across real-world workloads.

You will focus on executing well-defined performance studies, identifying bottlenecks, and helping translate architectural ideas into measurable performance gains

 Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42851

• Perform performance analysis for CPU microarchitectural features under guidance from Staff and Principal engineers.
• Run architectural simulations and analyze results (IPC, CPI stacks, latency and throughput metrics).
• Identify performance bottlenecks in frontend, execution engine, or memory subsystems.
• Assist in evaluating design trade-offs using trace-driven or cycle-accurate models.
• Characterize workloads and benchmarks (SPEC, server, client, internal traces).
• Develop scripts and tools to automate performance analysis.
• Work leading to patents and publication.

What You Bring

• Master’s, or PhD in Computer Engineering, Computer Science, or related field.
• 2+ years of experience in CPU microarchitecture and/or performance engineering.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Experience analyzing large performance datasets and traces.
• Familiarity with compiler optimizations and hardware/software co-design.

Preferred Qualifications

• Experience with RISC-V, ARM or X86 architectures.
• Background in power/performance/area (PPA) trade-off analysis.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Prior tapeout / patent / publication experience. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Principal, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab is seeking Principal CPU Architecture & Performance Engineer to lead the definition, analysis, and optimization of next-generation CPU microarchitectures (RISC-V core). This role is focused on end-to-end performance: from architectural trade-offs and workload characterization to micro-architectural modeling, simulation, and silicon bring-up correlation.

You will work closely with architecture, design, compiler, and system teams to drive performance and efficiency across a broad set of real-world workloads

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42918

• Define and evaluate CPU micro-architectural features for future cores (frontend, execution engine, memory hierarchy, interconnect).
• Lead performance analysis using simulators, RTL.
• Help develop and validate performance models (cycle-accurate, trace-driven, statistical).
• Characterize workloads (SPEC, server, client, AI/ML, cloud, internal traces) and translate findings into architectural requirements.
• Identify performance bottlenecks and propose data-driven optimizations.
• Drive architecture-to-implementation alignment with design team.
• Collaborate with compiler, OS, and system architects on cross-stack performance issues.
• Mentor senior and staff engineers; provide technical leadership across projects.
• Work leading to patents and publication

What You Bring

• Master’s with 18+ years of experience in Computer Engineering, Computer Science, or related field.
•  or PhD with 15+ years of experience preferred.
• 10+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC-V, ARM or X86 architectures.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Familiarity with compiler optimizations and hardware/software co-design.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Experience analyzing large performance datasets and traces.
• Proven ability (Tapeout / Patents /Publications) to influence architecture / micro architectural decisions through quantitative analysis.

Preferred Qualifications

• Background in power/performance/area (PPA) trade-off analysis.
• Experience with SIMD/Vectors.
• Experience with compiler optimizations and hardware/software co-design.
• Prior technical leadership at Senior Staff or Principal level. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are looking for a dynamic, self-motivated, experienced engineer to architect and lead functional test coverage and test methodologies for NVMe SSDs.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Manage Enterprise server infrastructure, execute Customer Qual tests and debug failures
• Execution of enterprise SSD qualifications in customer systems.
• Communicate with team lead to understand qualification processes and test plans. Report status of qualifications and manage customer expectations.
• Coordinate  with internal team and customer test engineers to execute qual plans as per schedule. Teams will be both local and remote.
• Triage test failures and do a first level FA. Design and execute experiments to root cause defects and verify fixes in coordination with development teams.
• Provide feedback to functional test teams on issues seen in customer quals to better functional test coverage.
• Contribute in Triaging customer field issues and provide support for timely resolution of customer issues.
• Identify automation opportunities and help Automation team to continue to improve and add to the existing framework.

What You Bring

• BS in Computer Science or related technical field with 10+ years of system level testing or development of enterprise servers and enterprise storage systems experience or MS with 8+ years preferred.
• Experience with at least storage protocol like NVMe/PCIe, SAS, SATA, Fibre Channel
• Familiar with one of protocol analyzers like LeCroy, SerialTek, or Xgig System or device level performance analysis
• Proficiency in server operating systems especially system debug tools such as system logs.
• Knowledge of enterprise storage/server system technologies.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, Test execution and bug management tools.
• Scripting experience such as in Perl, Shell or Python
• Experience with SSD or HDD testing
• NetApp/HPE/Dell/IBM System Experience
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop black-box functional test coverage and test methodologies for NVMe SSD's.
• Debug, triage failures and work with FW Team to reproduce problems, design and run experiments.
• Analyze customer field issues and improve Functional test coverage where gaps are identified.
• Provide guidance to the Automation team and assist with test coverage integration into the existing framework.
• Must be able to work with local US and international customers and OEMs.

What You Bring

• Bachelors and 10+ yrs, Masters and 8+ yrs’ with focus in Computer Science, Computer Engineering, Electrical Engineering or equivalent.
• Strong programming experience, demonstrated proficiency in scripting languages such as Python, Bash, Linux shell scripts etc.
• Excellent verbal and written communication skills.
• Ability to work individually and in teams.
• Prior NVMe, PCIe knowledge or experience with one or more of the following storage-related technologies: NVM Express, PCI Express, NAND Flash/FTL .
• Knowledge of Enterprise storage/server systems, and proficiency in Linux.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, test execution and bug management tools.
• Relevant hands-on experience in embedded software or firmware development/testing, including storage devices or other embedded platforms.
• Familiarity and experience with agile development methodologies and practices, particularly in AI/ML-focused environments, is preferred.
• Hands-on experience with PCI protocol analyzers.
• Demonstrated ability to work as a team player, as part of a local and globally distributed team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

Staff, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab  is looking for  Staff CPU Architecture & Performance Engineer to drive detailed performance analysis and architectural optimization for current and next-generation CPU (RISC-V) cores. This role focuses on deep ownership of performance-critical micro-architectural domains, workload analysis, and data-driven recommendations that influence core architecture decisions.

You will work closely with architects, design, compiler, and system teams to evaluate trade-offs, identify bottlenecks, and improve performance across real-world workloads

 Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42850

• Own performance analysis for one or more CPU microarchitectural domains (e.g., frontend, execution engine, memory subsystem).
• Build, extend, and validate architectural performance models and simulators.
• Perform CPI/IPC breakdowns and root-cause performance bottlenecks.
• Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models.
• Characterize workloads and benchmarks (SPEC, server, client, AI/ML, internal traces).
• Translate performance data into clear architectural recommendations.
• Work leading to patents and publication.

What You Bring

• Master’s in Computer Engineering, Computer Science or related filed with 8+ years of experience or PhD in Computer Engineering, Computer Science, or related field with 5+ years of experience.
• 5+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC-V, ARM or X86 architectures.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Experience analyzing large performance datasets and traces.
• Familiarity with compiler optimizations and hardware/software co-design..
• Proven ability - prior tapeout experience.

Preferred Qualifications

• Background in power/performance/area (PPA) trade-off analysis.
• Experience / Familiarity with SIMD / Vectors / VME for AI inference workloads..
• Prior  leadership guiding junior engineers.
• Prior patent / publication experience. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Samsung Semiconductor is hiring now for a Staff Engineer, Memory Systems Architecture.  The conventional DRAM failure analysis was physical electrical FA and physical FA. But, in the era of Data center, it is easier to track the field failure information. With this data set, Fault management team’s role is finding DRAM failure mode, abnormality and failure rate projection.

You will be part of an incubation team working on in-field telemetry intended to transform the Customer Quality Experience for Samsung memory products. Fault Management is the future of quality to minimize system downtime within AI/ML hardware deployments and workloads of the future. We analyze trends and patterns from enormous memory fleet telemetry to bucketize failures and perform virtual root-cause analysis. Telemetry analysis helps us design solutions to proactively avoid system downtime. We conduct research and develop both in-house and collaboratively in the industry with the opportunity to publish our findings through whitepapers and conferences. We are looking for innovative and passionate thinkers who can work in a start-up environment and are excited to shape the future of data centers around the world. Join us in our mission!

What You'll Do

• Based on the knowledge of SOC controller and memory operation including RAS feature, find and recommends better solution to mitigate the field DRAM failure rate.
• Needs to communicate better ECC scheme to customers based on Samsung DRAM failure mode(DQ and burst)
• Interface with customers to establish the value add of enabling in-field fault management architecture
• Contribute to the standardization of DRAM/HBM failure logging in the OCP.
• Propose and develop platform RAS (Reliability Availability Serviceability) algorithms for memory fault management such as page offlining, hPPR and conduct POC with known failure DIMMs in the real server and application.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Job ID: 42886

 What You Bring

• Bachelor’s degree with 10+ years of relevant industry experience, or Master’s with 8+ years or PhD with 5+ years hardware fault management, reliability, data center fleet management experience or related technical field preferred. (Must)
• Knowledge of platform memory subsystem, platform RAS (Reliability Availability Serviceability) such as ECC, page offlining, hPPR and hardware sparing.
• ECC design and verification and reverse engineering experience.
• Understanding on the address mapping between CPU and memory.
• Memory controller register modification.
• Linux kernel commit experience.
• DRAM and HBM failure mode understanding.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

About the Role

As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.

Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams.

This position is required onsite in San Jose, CA.

Key Responsibilities

• Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms
• Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems
• Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning 
• Serve as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrations
• Interpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutions
• Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on schedule
• Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows
• Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral
• Represent the Leo team in customer technical reviews, design-in engagements, and industry forums

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
• 8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications
• Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
• Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!
• Authorized to work in the US and available to start immediately

Required Experience

• High proficiency in C for embedded firmware development in RTOS environments
• Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
• Proficiency in Python for scripting, test automation, and diagnostic tooling
• Deep hands-on knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
• Experience with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
• Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
• Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
• Experience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines

Preferred Experience

• Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
• Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
• Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
• Experience with server memory performance tuning — latency and bandwidth optimization
• Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus

Compensation

The base salary range for this role is $175,000 – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

The Trade Desk is a global technology company with a mission to create a better, more open internet for everyone through principled, intelligent advertising. Handling over 1 trillion queries per day, our platform operates at an unprecedented scale. We have also built something even stronger and more valuable: an award-winning culture based on trust, ownership, empathy, and collaboration. We value the unique experiences and perspectives that each person brings to The Trade Desk, and we are committed to fostering inclusive spaces where everyone can bring their authentic selves to work every day.

Do you have a passion for solving hard problems at scale? Are you eager to join a dynamic, globally- connected team where your contributions will make a meaningful difference in building a better media ecosystem? Come and see why Fortune magazine consistently ranks The Trade Desk among the best small- to medium-sized workplaces globally.

The Team: Marketplace Quality Engineering:

Every second, our bidder evaluates millions of ad opportunities across thousands of publishers and supply paths. Not all of that supply is created equal — some of it is duplicated, some is structurally inaccessible, and some degrades advertiser outcomes. The Marketplace Quality Engineering team exists to make sure our platform is buying the right impressions, not just more impressions.

We own the systems that assess, measure, and optimize supply quality across the programmatic ecosystem. Our work spans deduplication, supply path analysis, quality modeling, and the tooling that turns those signals into decisions at bid time. The problems are technically deep — think identity resolution across fragmented supply chains, statistical modeling to separate signal from noise, and real-time decisioning at platform scale — and they have direct, measurable impact on both advertiser outcomes and platform economics.

This is not theoretical work. When we ship a model update, spend distribution across the platform shifts. Our engineering decisions translate directly into tens of millions of dollars of measurable business impact. If you want to build systems where what you ship visibly matters, this is the team.

You will work with C# / .NET as a core strength, alongside Python and SQL where data and automation need it, and partner closely with product, data, and platform teams across time zones.

Who you are:

Our culture runs deeper than having fun together (though we do that well, too). We take pride in our engineers being trust-builders, generous givers, scrappy problem solvers, and gritty pursuers of excellence. You do not need to meet every requirement below, but people who meet most of them tend to thrive in this role:

- You are comfortable working on an agile, distributed team across time zones and continents.

- You communicate effectively with both technical and non-technical audiences.

- You have a solid grasp of computer science and engineering fundamentals.

- You have strong experience with distributed systems and data-heavy backend work (services, pipelines, or both).

- You are proficient in C# / .NET.

- You are productive with modern development tools: Visual Studio, Visual Studio Code, Rider, and Git.

- You bring 7+ years of software development or engineering experience.

Nice to have (not required): GraphQL or REST API design, large-scale data processing frameworks (e.g. Apache Spark), workflow orchestration tools (e.g. Apache Airflow), schema-based data serialization, Kubernetes, Kafka, database engines (Microsoft SQL Server, PostgreSQL, Aerospike, Vertica, Redis), microservices, Python for data work or automation, and experience working across large codebases with multiple teams.

A wide range of technical opportunities is one of the best parts of engineering at The Trade Desk, which is why we do not expect you to know every technology we use on day one. What matters is that you learn quickly and solve complex problems with the right tools. What you know today matters less than how well you learn, adapt, and innovate. We are not looking for people who already have all the answers — we want engineers who can invent answers no one has thought of yet and frame the questions we have not yet asked.

We are looking for 0 to 1 Software Engineers to join an elite team that is building out Archer’s Airline Operations Software Ecosystem. Engineers who have built and shipped multiple products across disciplines and languages are encouraged to apply. Experience with backend development combined with AI-focused front-end development is especially valued. 

This role is 10-days a month in-person at our HQ in San Jose, CA.

What You'll Do:

• Build Great Software: Take product requirements and turn them into beautiful, reliable, and high quality web and mobile applications
• Create and manage backend infrastructure including building database schemas, API architecture, orchestration services, and refining architecture
• Product Development: Lead end-to-end technical execution and receive full ownership of the software development lifecycle
• System Architecture: Design and implement the architecture and tech stack that will serve as the backbone for our platform while balancing scalability, speed, and reliability
  Contribute to the Roadmap: Ideate, plan, and prototype technical tools for aircraft performance and dispatch settings
• Work Cross-Functionally: Work with design, data science, and technical aviation experts to supercharge the features and products you are working on
• Knowledge of Code-Generation: Use the latest code-generation technologies to streamline your workflow and achieve breakthrough productivity
• AI-Native Product Building: Implement and productize novel machine learning and deep learning algorithms developed by our AI/ML research team 

What You Need:

• Minimum of 5 Years of Post-College Work or Entrepreneurial Experience 
• 4-Year College Degree in an Engineering Discipline (or multiple pieces of evidence of outstanding individual technical achievement)
• Evidence of End-End Product Ownership: Experience building all parts of software from front-end to back-end to cloud deployment
• Personal Projects: Rich Github history with examples of personal projects that can be shared with the hiring team and/or open-source contributions
• Technologies: Next.JS, Java Script, React, React Native, Python, Fast API, PostGres
• Design: Ability to create intuitive, clean, and professional products without a dedicated designer or design system
• AI: Strong understanding of how to implement and train AI systems into SaaS products and willingness to learn and adapt to building voice agent
• Infrastructure: Familiarity with building server-less & micro-service in popular cloud hyperscalers and managing production grade CI/CD pipelines
• Adaptability: Quickly and iteratively respond to needs of customers and turn product changes around on tight timelines

Bonus Qualifications:

• Infrastructure experience: k8s, S3, RDS, SQS, Lambda, Datadock, Docker, and Temporal Orchestration Service
• Strong passion for aviation and/or UAM
• Willingness and ability to transition between mobile and web development

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $170,000.00 - $195,000.00  Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Astera Labs’ firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems.

Job Description

• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance.
• Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic Qualifications 

• Strong academic and technical background in electrical or computer engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Required Experience 

• ≥3 Years experience leading a team in a “lead by example” manner—planning sprints, assigning tasks based on individuals’ strengths and career aspirations, providing constructive/encouraging feedback, maintaining a “dashboard” view of project status, chipping into shore up gaps in execution as needed.
• ≥5 Years hands-on experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Good understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred Experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Familiarity with PCIe compliance standards and the ability to follow and be involved in compliance and standard consortiums.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, clock recovery and SerDes link budgets.
• Experience with PAM4 SerDes is a huge bonus!

Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.

Job Description

• Seeking a strong technical leader who has delivered multiple SoC products.
• Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs.
• Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications.
• Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.
• Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.
• Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.
• Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness.
• Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions.
• The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.
• Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.
• Drive a culture of technical excellence, accountability, and continuous improvement.
• Manage resource planning, and vendor/partner relationships.

Basic Qualifications

• Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred.
• ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.
• ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• ≥5 years building high performance Engineering teams and validation methodologies.
• Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.
• Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.
• Strong background in debug methodologies, lab infrastructure, and automation frameworks.
• Excellent communication skills and ability to influence executives and cross‑functional partners.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Preferred Experience

• ≥8 years leading validation teams planning, execution and maintaining project visibility.
• ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.
• Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.

The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

About the Role

A Team Leader is expected to bring a high level of technical knowledge of both third-party and Veeam products, communicate effectively, collaborate efficiently with other team members to improve team knowledge, and maintain a high level of customer satisfaction while maintaining morale and other major components of the workforce. A Team Leader is expected to perform periodic quality assurance checks of team workflow, provide necessary coaching to correct deficiencies, help address customer concerns directly, and arbitrate between technical levels and Product teams to ensure customers are receiving the best assistance available. 

What You’ll Do 

• Manage and direct a group of Technical Support Engineers to ensure successful customer experiences with issues or errors regarding product implementation, usage, and application or customer infrastructure, as outlined in the Veeam Support Policy. 

• Provide in-depth, expert technical support and troubleshooting for Veeam Software clients via telephone, email, and web conferencing. 

• Assist in escalation cases via internal and external distribution lists. 

• Analyze, diagnose, and provide solutions and or workarounds for virtualization software, operating systems, networks, and applications in relation to Veeam software product problems or questions. 

• Monitor ticket queues for SLA compliance, including updates to and work on assigned cases in a timely manner. 

• Maintain strong customer rapport and excellent, timely communication. 

• Communicate effectively with Sales Representatives and other internal teams. 

• Be a point of contact with on-call responsibilities for high-priority, highly complex issues. 

• Manage and reduce ambiguity. 

• Operate in an environment with frequent changes, including stressful situations. 

• Routinely train and mentor less experienced engineers. 

• Perform other duties as assigned. 

What You’ll Bring 

• Demonstrable strong technical knowledge and systematic problem-solving skills, sharing insights to elevate team and customer outcomes. 

• Ability to engage empathetically and communicate clearly with customers and colleagues, ensuring all interactions and documentation are professional, concise, customer-centric, and actionable. 

• Previous business-to-business (B2B) technical support experience with high-tech products or services is required, including virtualization, Windows infrastructure, and cloud-based storage or deployments. 

• Strong networking background required. 

• Three to five years of server administration and troubleshooting experience. 

• Five years of client or customer support experience at Level II or Level III with demonstrated problem resolution skills. 

• Exceptional communication skills, both verbal and written. 

Bonus Skills 

• Project management certifications or experience with productivity tools used at Veeam, such as Jira and Confluence. 

• Administration certifications for Amazon Web Services, Azure, or other similar cloud offerings. 

• Security certifications or equivalent work history involving management of certificate stores and cloud platform credential management. 

What You’ll Get 

• Two weeks of paid vacation, 12 statutory holidays, plus four extra global VeeaMe Days for self-care and 24 paid volunteer hours annually through Veeam Cares. 

• Paid parental leave: eight days for fathers, 122 days for birthing parents, and 92 days for adoptive parents. 

• Medical, dental, and vision coverage fully funded through INS Premium for employees and dependents. 

• Mental health support, therapy sessions, and virtual care through the Employee Assistance Program. 

• Retirement and social security contributions through Costa Rica’s statutory programs. 

• Life insurance equal to 24 times monthly salary, plus disability and funeral coverage. 

• Daily cafeteria subsidy. 

• Fertility, adoption, and surrogacy support, plus 24 paid volunteer hours through Veeam Cares. 

• Opportunities to learn and grow through on-demand libraries such as LinkedIn Learning and O’Reilly, mentoring, workshops, and learning events like the annual Global Day of Learning. 

Please note: The position is based in San Jose, Costa Rica. If the applicant is permanently located outside of Costa Rica, Veeam reserves the right to decline the application. All applications must be submitted in English.

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Overview
Join our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
• Scripting and automation for ASIC methodology improvement.
• Accountable for quality and overall design success with the support of senior engineers.

Required Qualifications
Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent
• 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
• Track record of delivering high quality digital designs from definition to production.
• Experience with functional and formal verification at block and chip level. 
• Understanding of clocking, CDC and RDC
• Experience with CMOS nodes (≤7nm)

Protocols & Integration:

• Familiarity with high-speed protocols—PCIe, Ethernet, DDR, or similar
• Experience with IP development and integration

Tools & Methodologies:

• Proven SystemVerilog and Python expertise in a production environment
• Familiarity with Synopsys and/or Cadence digital design flows
• Basic understanding of UVM-based verification methodologies

Professional Attributes:

• Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment
• Good communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who adapts quickly to changing requirements
• Customer-focused mindset with the ability to prioritize and work independently to deliver high quality designs.

Preferred Qualifications

• Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus
• Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus

Role Overview
Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.

Key Responsibilities

• Architecture & Technical Leadership
• Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines
• Establish architectural standards and best practices that scale across the design organization
• Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area
• Design Execution & Ownership
• Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up
• Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies
• Own accountability for design quality, schedule, and successful production delivery
• Cross-Functional Collaboration
• Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues
• Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up
• Work with firmware and software teams to optimize hardware-software interfaces
• Mentorship & Process Excellence
• Mentor and develop junior and senior engineers, elevating team technical capabilities
• Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure
• Contribute to organizational knowledge sharing and technical reviews

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure
• Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows
• Track record of delivering multiple high-performance designs to production

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)
• Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems
• Proven contributions to design methodology, CAD automation, or infrastructure improvements
• Experience leading technical teams or driving cross-functional initiatives in data center environments

Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion.
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic qualifications 

• Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Required experience 

• Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget. Experience with PAM4 SerDes is a huge bonus!
• Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
• Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.

The base salary range is $205,000.00 USD – $255,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

Overview

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Senior Silicon Validation Engineer to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. 

Basic Qualifications 

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred. 
• ≥3 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. 
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision. 
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind! 
• Proven track record solving problems independently. 

Required Experience 

• Familiarity with DDR4/5 memory standards and DIMM configuration, experience in system testing, characterization, margin analysis and optimization 
• Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ 
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration 
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis. 
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope/high-speed probe, and VNA 

Preferred Experience 

• Hands-on experience with signal integrity, especially as it relates to multi-rank DDR and DDR termination schemes 
• Working knowledge of C or C++ for embedded FW 
• Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops 
• Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working with internal SoC HW/FW teams to improve memory calibration and tuning sequences 
• Working knowledge of common serial data specifications such as I3C, I2C, SPI, etc 
• Knowledge of memory subsystem compliance and RAS is a plus. 
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc. 
• Knowledge of simulation tools such as MATLAB, Keysight ADS, PLTS for data analysis and modeling of signal integrity issues. 

Job Description:
At Astera Labs, we are looking for motivated Senior / Tech Lead Post-Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥3 years’ experience testing, supporting or developing complex SoC/silicon products and high-speed IO/SerDes electrical interface for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead.

Required Experience:

• Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3x Ethernet.
• Strong problem-solving skills, ability to solve problems independently.
• Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, and both NRZ and PAM4 signaling.
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
• Familiarity with PCIe or Ethernet especially Electrical Compliance sections
• Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
•  Working knowledge of C or C++ for embedded FW
•  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
•  Working knowledge of common serial data specifications such as I2C, SPI, etc
•  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $148,500 USD - $165,000 USD for Senior level, and $175,000 USD - $195,000 USD for Staff level.

About Astera Labs

Astera Labs is a rapidly growing semiconductor company redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions—built on PCIe®, CXL™, Ethernet, and custom fabrics—enable seamless data movement across compute, memory, and storage. As part of our team, you'll help validate the silicon that powers the world's most advanced AI platforms.

Role Overview

As an Entry-Level System Validation Engineer on the Taurus team, you will validate Astera Labs' Taurus Ethernet Smart Cable Modules and Taurus ASICs. You'll work on chip bring-up, system-level debug, and interoperability testing across real-world AI server and networking platforms, collaborating closely with electrical validation, firmware, and product applications teams.

Key Responsibilities

• Execute system validation test plans for Taurus Ethernet Smart Cable Modules.
• Perform chip bring-up and debug for Taurus ASICs in lab environments using oscilloscopes, protocol analyzers, BERTs, and network switches
• Validate high-speed interconnects and AI fabrics in custom silicon, including signal integrity, link training, FEC stats, and protocol compliance
• Collaborate with electrical validation, firmware, and product applications teams to root-cause issues and drive resolution
• Document validation results, debug findings, and contribute to bring-up notes and test reports

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• Strong academic foundation in circuit analysis, signals and systems, electromagnetics, or high‑speed digital design through coursework and labs
• Familiarity with PCIe®, CXL™, or Ethernet standards
• Familiarity with fundamental signal‑integrity concepts such as eye diagrams, jitter, noise, impedance, and transmission lines
• Exposure to electrical lab equipment (e.g., oscilloscopes, logic analyzers, network analyzers)
• Experience using scripting or programming languages such as Python, MATLAB, TCL, or C/C++
• Comfortable working with lab tools and debugging hardware
• Strong analytical and communication skills

Preferred Skills

• Exposure to post-silicon validation or bring-up of connectivity IP blocks
• Knowledge of signal integrity analysis and eye diagram interpretation
• Familiarity with Linux systems, shell scripting, and version control (Git)
• Understanding of AI workloads and how interconnect bandwidth impacts performance

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role Overview

Join Astera Labs as a Technical Lead Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 5+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $160,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
• ≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. 
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in tcl, python or Perl.

Preferred Experience:

• Knowledge of design for test (DFT)
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.

Key Responsibilities

• As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
• Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
• Architect and recommend flow improvements and enhance existing methodology for high performance design.
• Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
• Work with cross function teams to define requirements and specifications to achieve best PPA
• Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity
• Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• 2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Knowledge of agentic AI solutions is a plus.
• Experience working with EDA/IP vendors for both RTL and hard-macro integration.
• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.

Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.

Key Responsibilities

• Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
• Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
• Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
• Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
• Work with RTL designers to troubleshoot and resolve design issues.
• Drive verification strategy and methodology for SoCs in server and networking applications.

Required Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred).
• 8+ years of experience in SoC verification, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
• Familiarity with verification of switching architectures, including packet processing and forwarding engines.
• Excellent communication skills and ability to work independently with minimal supervision.

Preferred Qualifications

• Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
• Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
• Knowledge of Ethernet/PCIe switching and central buffer architectures.
• Experience with emulation platforms and hardware-software co-verification

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Role Overview

Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.

Key Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits

Overview

Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
• Work closely with post-silicon teams to facilitate silicon bring-up and debug.
• Mentor junior engineers to develop their technical skills and expertise.
• Actively contribute to the development and improvement of silicon development processes.
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success.

Required Qualifications:

Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Architecture definition and micro-architecture development
• RTL coding, functional simulation, and synthesis
• Timing closure and gate-level simulation (GLS)
• Design for test (DFT) implementation
• Production experience with advanced CMOS nodes (≤7nm)

Protocols & Integration:

• Deep expertise in at least one high-speed protocol—PCIe , Ethernet, Infiniband, DDR, or similar
• Third-party IP integration and verification.
• Block-level design ownership from architecture through GDS

Tools & Methodologies:

• Proficiency with Cadence and/or Synopsys digital design flows
• Familiarity with UVM-based verification methodologies.
• Silicon bring-up, debug, and failure analysis expertise

Professional Attributes:

• Strong work ethic with the ability to balance multiple priorities in a dynamic environment
• Excellent communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements
• Customer-focused mindset with ability to translate business needs into technical excellence

Preferred Qualifications

• Track record of delivering multiple high-performance designs to production in data-center environments
• Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
• Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
• Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality

We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation.  The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues.  The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.

Basic qualifications:

• Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.
• Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required experience:

• Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols.
• High level of proficiency in System Verilog and verification environments.
• Experience understanding software and hardware co-simulation limitations and debug methods.
• Experience in programming and scripting languages (like perl/python/C).
• Currently based locally or open to relocation.

Preferred experience:

• Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.
• Experience in modeling for emulation and prototyping, and/or non-UVM environments

Job Description

The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• Minimum 8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).
• Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience developing embedded firmware for PCIe products.
• MQX RTOS or ThreadX Development or enablement.
• High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
• High level of proficiency in Python for automating pre-processors/post-processors and FW QC.
• Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.
• Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).
• Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces
• Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc

Preferred Experience

• Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC)
• Experience with industry forums and collaboration workgroups such as OCP and OpenBMC

The base salary range is $203,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description

We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
  required, and a Maser’s is preferred.
• ≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in US and start immediately.

Required Experience

• Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
  environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
  generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
  writing assertions, cover properties and analyzing coverage data
• Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.
• Must have prior experience on verification with firmware to control and configure the SerDes and related components.

Preferred Experience

• SW debugging for Mix-Signal based designs.
• Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.
• Experience with FPGA-based verification/emulation.

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.

Key Responsibilities

• Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
• Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
• Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
• Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• SystemVerilog/Verilog familiarity.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role Overview

Astera Labs is seeking a Principal Product Applications Engineer to join our Aries PCIe Retimer team and serve as a critical technical bridge between our customers and engineering organization. As AI infrastructure demands explode, our Aries Smart Retimers are enabling the high-speed, low-latency PCIe connectivity that powers the world's most advanced data centers—and you'll be at the center of that growth.

In this high-impact role, you'll work directly with hyperscalers, OEMs, and system builders to drive successful adoption of our Aries PCIe products. You'll combine deep technical expertise with customer-facing skills to solve complex system-level challenges, create compelling technical documentation, and influence product direction based on real-world customer needs. This is an opportunity to shape how next-generation AI and cloud infrastructure connects and scales.

You'll collaborate cross-functionally with design engineering, validation, sales, and marketing teams while building strong relationships with customers who are defining the future of computing. If you thrive at the intersection of cutting-edge silicon and customer success, this role offers exceptional visibility and impact.

Key Responsibilities

Customer Technical Engagement

• Serve as the primary technical resource for customers during pre-sales evaluation and post-sales deployment of Aries PCIe retimers
• Deliver technical presentations, product training, and demonstrations to customer engineering teams
• Build trusted advisor relationships with key accounts and drive product adoption

System-Level Debug & Validation Support

• Lead root cause analysis and debugging of complex PCIe signal integrity and protocol issues in customer systems
• Support customer lab bring-up, characterization, and validation activities
• Develop and execute test plans to reproduce and resolve customer-reported issues

Technical Documentation & Enablement

• Create application notes, reference designs, and best practices guides for PCIe system implementation
• Develop collateral that accelerates customer time-to-deployment
• Contribute to product documentation including datasheets and user guides

Cross-Functional Collaboration

• Partner with product management and engineering to translate customer feedback into product requirements
• Support sales teams with technical expertise during customer engagements
• Represent the voice of the customer in internal roadmap and feature discussions

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in applications engineering, technical support, or system engineering roles
• Strong understanding of PCIe architecture, protocol, and electrical specifications (Gen4/Gen5/Gen6)
• Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BERT tools
• Experience debugging high-speed serial interfaces at both the physical and protocol layers
• Excellent written and verbal communication skills with ability to explain complex technical concepts
• Develop and modify firmware using C to implement features, optimize performance, and resolve technical issues
• Travel to customer sites worldwide to provide on-site technical support, conduct system integration, and drive issue resolution

Preferred Qualifications

• Experience with PCIe retimers, redrivers, or similar connectivity components
• Familiarity with server, storage, or GPU system architectures
• Background in signal integrity analysis and simulation tools
• Scripting proficiency (Python, TCL) for test automation and data analysis
• Prior experience working directly with hyperscale or enterprise data center customers
• Track record of creating high-quality technical documentation and application notes

Salary range is $158,400 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite.

Basic Qualifications

• Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.
• 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
• Have a proven track record with defining hardware system constraints and high-speed technology roadmaps.
• Cross-functional design mentality with the electrical design community to develop systems.
• Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.
• Proven track record solving problems independently, preferably as a tech lead.
• Entrepreneurial, open-minded behavior, and can-do attitude.
• Authorized to work in the US and start immediately.

Required Experience

• Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects
• 2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets
• EM modeling of BGA and connector structures
• High-speed SERDES channel simulation, and equalization
• PI simulations with Ansys/Cadence toolsets
• Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
• Working knowledge of PCB fabrication limits and trade-offs
• Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections.
• Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome.

Overview: 

The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance.

Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs.

Basic Qualifications:

•  Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
•  ≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
•  Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead
• Required experience
• Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet
• Strong problem-solving skills, ability to solve problems independently
• Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

•  Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
•  Familiarity with PCIe or Ethernet especially Electrical Compliance sections
•  Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
•  Working knowledge of C or C++ for embedded FW
•  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
•  Working knowledge of common serial data specifications such as I2C, SPI, etc
•  Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
•  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is USD 203,00 - USD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Overview

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 10 + years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, executing validation plans for complex SoC designs. 

Required Experience:

• Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet.
• Familiarity with Electrical Compliance section of PCIe Base Spec and CEM Spec
• Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ, CDR, etc and concepts such as PAM4
• Experience in PRBS testing and optimization of high-speed PCIe data links over short, med, and long channels
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops
• Hands-on experience with signal integrity, especially as it relates to PCIe testing, Channel Loss budgeting, and de-embedding
• Working knowledge of C or C++ for embedded FW, experience using git-based version control such as github
• Familiarity with PCIe standards and both NRZ and PAM-4 signaling
• Working knowledge of common serial data specifications such as I2C, SPI, etc
• Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is $185,000 USD - $230,000 USD. Your base salary will be determined based on your experience and the pay of employees in similar positions. 

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Education and Experience Requirements

• Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 8-12 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Desired Qualifications

• Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
• Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
• Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
• Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
• Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
• Experience with PAM4 SerDes validation (200G/100G/50G)
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
• Knowledge of Signal Integrity simulation tools
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

As a Senior DevOps Engineer, you will be a key contributor to our infrastructure strategy, focusing on automation, stability, and performance across both cloud and on-premise environments. You will drive best practices in CI/CD, configuration management, and monitoring, with a specific focus on optimizing the deployment and operation of large language models (LLMs) and related technologies.

Responsibilities

• Design, deploy, and manage highly available, scalable infrastructure using Kubernetes and Docker across public cloud (e.g., AWS, GCP, Azure) and on-premise data centers.
• Develop and maintain robust Configuration Management solutions (e.g., Ansible, Terraform) for consistent environment provisioning and management.
• Implement and manage CI/CD pipelines to facilitate rapid, reliable, and automated software releases.
• Administer and troubleshoot operating systems, encompassing both Linux and Windows environments.
• Implement and optimize observability practices using monitoring tools like Datadog for logging, tracing, and alerting.
• Spearhead the operational deployment, scaling, and maintenance of LLM infrastructure, leveraging tools like LiteLLM, OpenRouter, or similar LLM orchestration/gateway technologies.
• Automate repetitive tasks and system operations using scripting languages, primarily Bash and Python.
• Collaborate closely with development, MLOps, and security teams to ensure infrastructure supports product requirements and compliance standards.
• Participate in an on-call rotation to ensure service reliability and responsiveness to incidents.

Qualifications

Required Skills

• 5+ years of professional experience in a DevOps, SRE, or infrastructure engineering role.
• Deep expertise in containerization and orchestration, specifically Kubernetes (design, deployment, and troubleshooting) and Docker.
• Strong proficiency in managing infrastructure in both Cloud (e.g., AWS, GCP, Azure) and On-Premise environments.
• Expert-level administration skills in Linux and strong working knowledge of Windows Server environments.
• Proven experience with Infrastructure as Code (IaC) and Configuration Management tools (e.g., Terraform, Ansible).
• High proficiency in scripting and automation using Python and Bash.
• Extensive experience with monitoring and observability platforms, especially Datadog (or comparable tools like Prometheus/Grafana, New Relic).
• Hands-on experience deploying and managing technologies related to Large Language Models (LLMs), such as utilizing LiteLLM, OpenRouter, or setting up and managing LLM serving endpoints.

Nice-to-Have Skills

• Experience with specific Kubernetes distributions (e.g., K3s, Rancher, OpenShift).
• Familiarity with network configuration, firewalls, and security best practices for hybrid environments.
• Experience in MLOps workflows and related tools (e.g., MLflow, Kubeflow).
• Certifications such as CKA, CKAD, or relevant cloud provider certifications.

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $133,400 - $200,000. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is proud to be an Equal Opportunity employer committed to diversity and inclusivity in the workplace. All aspects of employment are decided on the basis of merit, qualifications, and business needs. We do not discriminate based upon race, color, religion, sex, sexual orientation, age, national origin, disability status, protected veteran status, gender identity or any other characteristic protected by federal, state or local laws. Successful candidates must be able to demonstrate U.S. citizenship, permanent residency, or status as a protected individual to satisfy ITAR, contractual, and/or regulatory requirements.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Our Software Engineers are end-to-end owners who have the opportunity to participate in many aspects of designing, building, and delivering data-focused products for our stakeholders. 
At The Trade Desk, we believe that each opportunity to engage with consumers is unique. User experience can make or break our business. This means our users must have all the flexibility to harness our system’s growing power and present meaningful insight from the petabytes of data streaming through our platform with unparalleled ease. 

 
Our system performs every day, 24/7, serving global traffic. We deliver features to improve our clients' abilities to make real-time decisions and troubleshoot campaigns with simple-to-use interfaces and high-performance data interactions. To improve our users’ day-to-day lives, we collaborate closely with user experience and product management organizations to ensure consistent, modern designs as well as the right balance of requirements. Our frontend developers work up and down the stack (client to server) to deliver these world-class experiences. 

What you’ll do:
Some of the work that you will be doing to help us deliver on our mission is:

• Design, build, deliver, and own full lifecycle development software from inception to production 

• Demonstrate a firm grasp of the entire software development lifecycle 

• Drive complex changes involving multiple components 

• Deliver quality changes, including automated tests, metrics, and monitoring  

• Collaborate with team members to deliver features 

• Guide and review changes to product features in line with product roadmaps  

• Implement and maintain product features 

• Build components and processes that are regularly used by others 

• Build execution plans incorporating user data, observations, and market insight 

• Validate changes to ensure high quality product releases 

• Work in a distributed system environment 

• Understand the business objectives behind the code 

• Understand system architecture fundamentals through self-directed learning 

• Participate in and lead projects with a high level of technical ambiguity 

• Contribute to development of comprehensive success criteria

• Lead others through example, mentorship, teaching

• Participate in hiring activities

• Use data to analyze and communicate the impact of your work on operational efficiency 

We are a global team with different backgrounds, experiences, and perspectives. To complement this team, you will welcome ideas that are different from your own and be well-versed in building from common ground to value, seek out, and foster invisible and visible dimensions of diversity.
Who you are:
Our culture is much deeper than just having fun together (though we do that well, too). We take pride in our engineers being trust-builders, generous givers, scrappy problem solvers, and gritty pursuers of excellence. You do not have to meet all the requirements below, but we believe that people who meet most of them will have a higher likelihood of succeeding in this role:

• You are comfortable working on an agile, distributed team spanning multiple time zones and continents. 

• You are able to communicate effectively across both technical and non-technical audiences. 

• You have a solid understanding of computer science and engineering fundamentals. 

• You are passionate about building beautiful and seamless user interfaces. 

• You have love for, and desire to advance, the state of the art of technology. 

• You are proficient in JavaScript/TypeScript. 

• You have experience building enterprise level services. 

• You have 7+ years of software development engineering experience.

• You have a Bachelor’s/Master’s level degree in computer science or relevant engineering-related field or equivalent experience. Not everyone has the same level of access to opportunities. What is most important to us is what and how you can contribute, which is why our consideration is not limited by the level of education you have.

• You have additional nice-to-have experience in the following areas: languages/technology on the server-side (C#, Java, NodeJS, SQL), knowledge of front-end frameworks (React/Redux). 

A variety of technical opportunities is one of the best things about working at The Trade Desk as a software engineer, which is why we do not expect you to know every technology we use when you start. What we care about is that you can learn quickly and find solutions to complex problems using the optimum tools for the job. What you know is less important than how well you learn and innovate. We are not seeking engineers who know all the answers; we need engineers who can invent answers no one has thought of yet and find answers to the questions yet to be asked.

Role

We are looking for a Staff Data Center Operations Engineer to join our Cloud Ops Build and Infrastructure Team. This role is on-site in Fremont, CA, reporting directly to the Datacenter Deployment Manager. In this position, you will play a critical role in expanding Zscaler’s global cloud by utilizing automation to provision hardware that will be deployed to our data centers.

What you’ll do (Role Expectations)

• Provision new hardware and network devices in a staging environment that will be deployed globally to expand and supplement the Zscaler network
• Troubleshoot issues within our build environment and repair or replace server and network components and infrastructure
• Collaborate with the maintenance, network, install and platform engineering teams, execute and validate build activities, and engage and assist in optimizing processes

Who You Are (Success Profile)

• You are a positive force. You approach hard problems with constructive energy and a 'can-do' spirit that is contagious, inspiring your team to stay focused on the solution.
• You operate with urgency. You understand that in a high-growth environment, speed and quality are not mutually exclusive. You have a relentless focus on execution and a bias for action, delivering high-impact results quickly to win for the customer and the team.
• You are driven by innovation. You have a deep curiosity for how things work and are energized by solving complex technical challenges. You believe in the power of technology to accelerate transformation and are always looking for a better, more secure, and scalable way.
• You champion simplicity. You are skilled at distilling complex problems, user needs, and technical concepts into clear, simple, and actionable plans. You are a precise communicator who brings clarity and focus to every interaction.
• You are resilient and adaptable. You view change as an opportunity and setbacks as temporary. You maintain composure and focus in high-pressure situations, guiding yourself and your team through complexity with a steady, positive hand.

What We’re Looking for (Minimum Qualifications)

• USA Citizenship (required due to the nature of assigned customers)
• 5+ years experience working in Data Center or hardware build and development environments
• Experience with the LINUX/UNIX command-line, BIOS, OOB management (ILO, SAA, iDRAC, IPMI, etc)
• Deep understanding of various types of servers, network devices and configurations, and physical connectivity
• Ability to occasionally lift and carry 50 lbs

What Will Make You Stand Out (Preferred Qualifications)

• Basic scripting capabilities (e.g., BASH, Python, etc.)
• Familiarity with build automation technologies such as Ansible or PXE boot
• Familiarity with JIRA, Confluence, or other ticketing and documentation tools

#LI-KM9 #LI-Hybrid

Efficient is seeking a  RTL-DV CAD Lead Engineer to own and advance the EDA flow infrastructure that powers our RTL design and  design verification (DV) teams. In this role you will define methodology, build automation, and provide hands-on flow support across the entire pre-silicon development cycle — from RTL synthesis and lint to UVM testbench execution. You will work at the intersection of EDA tool expertise, scripting/infrastructure engineering.

If you enjoy making engineers wildly productive, love root-causing weird build failures, and don’t mind occasionally wrestling with a vendor license server at 2am then this role is for you. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Help develop CAD flows in close collaboration with  RTL designers for RTL design: lint (Spyglass/Jasper), CDC/RDC analysis, synthesis (Design Compiler/Genus), equivalence checking (Formality/Conformal), and static timing analysis.
• Develop and maintain simulation flows in collaboration with the DV team  for functional verification using leading simulators (VCS, Xcelium, Questa); manage compile, elaborate, and regression infrastructure.
• Define (in collaboration with the RTL/DV leads) RTL coding guidelines, lint rule policies, and waiver management processes.
• Design and implement build/regression automation frameworks using Python, Makefile, Tcl, and shell scripting; integrate with LSF/SLURM job schedulers for farm-efficient execution.
• Build and maintain CI/CD pipelines (Jenkins/GitLab CI) that gate RTL checkins on lint, CDC, and smoke-regression results.
• Help develop coverage collection and closure infrastructure: merge/analyze per-block and SoC-level coverage databases (VCS CM, Xcelium IMC) and publish dashboards to support sign-off decisions.
• Provide scripted infrastructure for test-list management, seed sweeps, and regression triage; reduce manual overhead through automation.
• Establish process for Soft-IP and Hard-IP downloads and versioning with the RTL/PD team,  VIP integration and BFM bring-up in partnership with DV lead.
• Ensure we have the latest tool versions for the complete RTL/DV EDA tool suite. Establish relationships with EDA vendors to stay on top of licenses and ensure we have the appropriate license features and count available at any given time.
• Mentor junior CAD and DV engineers on flow best practices, scripting techniques, and EDA tool usage.

Required Qualifications

• 8+ years of hands-on CAD or DV infrastructure engineering experience in a semiconductor design environment.
• Proven ownership of simulation, lint, CDC  for complex RTL blocks or SoC-level designs.
• Strong scripting proficiency in Python and Tcl; experience with Makefile-based or equivalent build systems..
• Experience with at least two major commercial simulators (VCS, Xcelium, Questa) and/or formal tools (JasperGold, VC Formal, Conformal).
• Familiarity with job schedulers (LSF, SLURM) and version control systems (Git).
• Strong communication skills; ability to translate complex flow issues into actionable guidance for design engineers.

Desired Qualifications & Experience Requirements

• Exposure to power-aware simulation (UPF/CPF) and low-power flow integration.
• Experience with coverage-driven verification (CDV) at the SoC level.
• Prior work with CI/CD systems (Jenkins, GitLab CI) applied to hardware design flows.
• Contributions to internal tool or flow documentation that enabled team-wide adoption.

We offer a competitive salary for this role, generally ranging from $180,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

About the role

Muon seeks a Staff Software Engineer to join our flight software team. The ideal candidate is an expert software developer with significant previous experience architecting and building robust bare-metal / RTOS embedded devices or appliances. In this role, you will both set architectural direction for, and lead design, development, integration, and testing of much of the software and firmware that runs on our orbiting satellites. This position is based at our San Jose, CA office.

Responsibilities

• Leading member of the team defining and building Muon’s satellite bus platform
• Define and architect design and execution against the basic concepts and requirements of our missions to get the right software and firmware on orbit
• Design, bring up, and support the embedded software environment that runs in our satellite flight systems and peripherals using ARM Cortex-M CPUs.
• Guide evaluation and selection of technologies for our software foundation
• Write application, platform, and driver functionality in our flight software environment and set the standards for how others use it
• Build the architectural patterns, shared libraries, services and technical strategy documents that enable high-quality and high-velocity development of flight software
• Integrate compute and peripheral subsystems in both software and hardware
• Collaborate with hardware team members on the design and bring up of Muon hardware
• Align team roadmaps with product requirements and mission needs
• Define metrics aligned with critical company goals and enable the team to achieve aggressive goals
• Ensure effective software and hardware-in-the-loop test strategies
• Mentor senior engineers

Qualifications 

• B.S., M.S., or Ph.D. in computer science, electrical engineering, or related field
• 10+ years experience as a software engineer in a team environment
• Strong C/C++ programming, with practical familiarity of other languages
• Great embedded systems fundamentals: distributed system architecture, resource-efficient design, low-level drivers, bit manipulation, responsive software and IRQ handling, RTOS frameworks, I/O and communication buses.
• Integration and control of external hardware devices
• Read and understand hardware data sheets
• Excellent communication and presentation skills

Nice-to-have Skills

• Experience working in flight software or some closely related domain
• Rust and Python experience
• Knowledge of industry-standard data formats and schemas (ProtoBuf, YAML, JSON, etc)
• Familiarity with a Linux-based development environment
• Experience with one or more of: embedded linux, FPGA, HW design, RF communication systems, cloud/server infrastructure, network architecture.
• End-to-end development from product concept to delivery to customer/market.

Salary

The salary range for this role is $210,000 - $234,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process. 

About the role

Muon seeks a Flight Software Engineer to join our satellite flight software team. The ideal candidate is a self-motivated versatile software developer with significant previous experience developing robust bare-metal / RTOS embedded devices or appliances. In this role, you will design, develop, integrate, and test the software and firmware that runs on our orbiting satellites. This position is based at our San Jose, CA office.

Responsibilities

• Integral member of the team defining and building Muon’s satellite bus platform
• Translate concepts and requirements into design and working implementations, supporting through to on-orbit operations
• Design, bring up, and support the embedded software environment that runs in our satellite flight systems and peripherals using ARM Cortex-M CPUs.
• Participate in evaluating and selecting technologies for our software foundation
• Write application, platform, and driver functionality in our flight software environment and teach others how to use it
• Integrate compute and peripheral subsystems in both software and hardware
• Collaborate with hardware team members on the design and bring up of Muon hardware
• Collaborate with software team members to set flight software architecture, select infrastructure and tools, and communicate with cloud backends.
• Participate in developing software and hardware-in-the-loop test strategies

Qualifications 

• B.S., M.S., or Ph.D. in computer science, electrical engineering, or related field
• 5+ years experience as a software engineer in a team environment
• Strong C/C++ programming, with some practical familiarity of other languages
• Great embedded systems fundamentals: resource-efficient design, low-level drivers, bit manipulation, responsive software and IRQ handling, RTOS frameworks, I/O and communication buses.
• Integration and control of external hardware devices
• Read and understand hardware data sheets
• Excellent communication and presentation skills

Nice-to-have Skills

• Knowledge of industry-standard data formats and schemas (ProtoBuf, YAML, JSON, etc)
• Familiarity with a Linux-based development environment
• Experience with one or more of: embedded linux, FPGA, HW design, RF communication systems, cloud/server infrastructure, network architecture.
• End-to-end development from product concept to delivery to customer/market.

Salary

The salary range for this role is $156,000 - $186,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process. 

About the role

Muon seeks a Flight Software Engineer to join our satellite flight software team. The ideal candidate is a self-motivated versatile software developer with significant previous experience developing robust bare-metal / RTOS embedded devices or appliances. In this role, you will design, develop, integrate, and test the software and firmware that runs on our orbiting satellites. This position is based at our San Jose, CA office.

Responsibilities

• Integral member of the team defining and building Muon’s satellite bus platform
• Translate concepts and requirements into design and working implementations, supporting through to on-orbit operations
• Design, bring up, and support the embedded software environment that runs in our satellite flight systems and peripherals using ARM Cortex-M CPUs.
• Participate in evaluating and selecting technologies for our software foundation
• Write application, platform, and driver functionality in our flight software environment and teach others how to use it
• Integrate compute and peripheral subsystems in both software and hardware
• Collaborate with hardware team members on the design and bring up of Muon hardware
• Collaborate with software team members to set flight software architecture, select infrastructure and tools, and communicate with cloud backends.
• Participate in developing software and hardware-in-the-loop test strategies

Qualifications 

• B.S., M.S., or Ph.D. in computer science, electrical engineering, or related field
• 8+ years experience as a software engineer in a team environment
• Strong C/C++ programming, with some practical familiarity of other languages
• Great embedded systems fundamentals: resource-efficient design, low-level drivers, bit manipulation, responsive software and IRQ handling, RTOS frameworks, I/O and communication buses.
• Integration and control of external hardware devices
• Read and understand hardware data sheets
• Excellent communication and presentation skills

Nice-to-have Skills

• Knowledge of industry-standard data formats and schemas (ProtoBuf, YAML, JSON, etc)
• Familiarity with a Linux-based development environment
• Experience with one or more of: embedded linux, FPGA, HW design, RF communication systems, cloud/server infrastructure, network architecture.
• End-to-end development from product concept to delivery to customer/market.

Salary

The salary range for this role is $184,000 - $208,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process. 

About the Role

We are seeking an experienced, highly motivated Senior Full-Stack Engineer to join our growing team. The ideal candidate will be a strong collaborator with deep expertise in modern application development technologies and practices. The focus of this role is on building and maintaining robust, scalable, and high-performance applications across the full stack using TypeScript and some Python. Some experience with React and/or Angular would be helpful.

This role requires not only technical proficiency but also a forward-thinking perspective on the role of Artificial Intelligence (AI) in modern software development. Candidates must demonstrate an active engagement with AI tools, understanding their practical use, current limitations, and the strategic opportunities they present for the engineering discipline.

Mainly remote work: seeking candidates in the greater Los Angeles area to mainly work remotely with some on-site work required at times.

Key Responsibilities

• Lead the design, development, and deployment of complex features across both the frontend and backend of our clients’ products.
• Write clean, maintainable, and well-tested code using TypeScript for type safety and scalability on both the client and server.
• Collaborate with product managers, designers, and other engineers to translate business requirements into technical solutions.
• Collaborate with other team members to set technical standards, establish best practices, and make architecture decisions.
• Actively research and evaluate new technologies, tools, and methodologies to improve the engineering process.
• Demonstrate and articulate a practical understanding of AI tools (e.g., planning, code generation, intelligent testing frameworks) in daily engineering tasks, including their effective application and inherent limitations.

Qualifications

• 5+ years of experience in full-stack software development.
• Expert-level proficiency with TypeScript, including complex type definitions and advanced language features.
• Strong experience with server-side development, including building and consuming RESTful APIs or GraphQL services (proficiency with Hono Framework is a plus).
• Proficiency with relational and non-relational databases
• Familiarity with modern CI/CD pipelines, containerization (Docker), and cloud platforms (primarily AWS, with experience in GCP and/or Azure a plus).
• Preferred, but not required: Proficiency with React and its ecosystem (e.g., Hooks, Context API, Next.js, or similar frameworks). Experience with Angular (any version) in a professional capacity is a plus.

AI and the Evolution of Software Engineering & Ops

All candidates must be prepared to discuss and demonstrate the following during the interview process:

• Practical AI Tool Usage: Specific examples of AI tools used in professional or personal projects to enhance productivity, solve complex problems, or accelerate development. If you have a preferred agentic tool setup, please share!
• Understanding of AI Limitations: A clear understanding and articulation of the current technical, ethical, and accuracy limitations of modern AI tools in the engineering context.
• Strategic AI Opportunity: A viewpoint on how AI tools create new opportunities for software engineering, such as shifting focus from boilerplate code to complex problem-solving or architectural design.
• Evolution of the Engineering Role: A well-articulated point of view on how your role has already changed (e.g., new workflows, skills, ways of collaborating) due to the introduction of AI and how you expect the role to evolve in the coming years based on your assessment of coming advancements in AI tools and technologies.

Salary Range $135,000 - $175,000

Application Process

A cover letter is required. Your cover letter should be informed by the “AI and Forward-Looking Requirements” section above.

The hiring process includes:

• Initial Screening Call
• A Technical Assessment sent by email and returned by email
• A Panel Interview