About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About The Role

You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions.

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Minimum Qualifications

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience: 6+ years of hands-on experience in ASIC/SoC design.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.
• Experience with Lint, CDC, synthesis, power analysis and DV coverage tool.

Preferred Qualifications

• Advanced Education: Master’s or PhD in Electrical Engineering with working experiences.
• Domain Knowledge: NAND Flash, memory controller, datapath design, NVMe, PCIe, UCIe, DDR, CPU subsystem, Network Interconnect, AMBA, error correction code.
• Proficiency in AI tool to generate synthesizable and functional RTL code.
• Knowledge of design verification approaches to enhance verification coverage.

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

Principal Engineer, SOC Design

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Job ID:  42866

Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy

• Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
• Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
• Reviews 3^rd party IPs including ARM cores, DDR controller, and UCIe PHY 
• Responsible for integrating the third part IPs and sub system at top level
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

What You Bring

• Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
• Highly motivated with good verbal and written communication skills.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
• Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
• Good understanding of PPA (performance, power, and area) trade-offs.
• Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
• Experience in interfacing 3^rd party service companies for DFT/PI/PD.
• Good knowledge and experience in AMBA bus fabric, ARM cores.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

What You’ll Do

As a seasoned Senior Technical Project Manager (ASIC) you will lead complex silicon development projects from specification definition through tape-out, fabrication, and post-silicon validation. You will be the primary face of Samsung’s (SLSI’s) ASIC design, verification, physical design, firmware, foundry and advanced packaging teams to the customer and ensure the timely delivery of all collateral. This role requires a strong technical background in semiconductors combined with exceptional program management skills to navigate risks and drive execution excellence.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Reports to: Team leader/Head of Custom SoC Solutions Team.

Job ID: 42809

Key Responsibilities

• End-to-End Program Ownership: Work with customers from initial concept and specification stage to silicon tape-out, bring-up, and production. This includes not only technical, but also spans commercial and legal domains.
• Project Planning & Scheduling: Develop and maintain detailed project plans, milestones, and resource allocation. Proactively identify and resolve bottlenecks and critical path issues.
• Cross-Functional Coordination: Collaborate with Architecture, RTL, Verification, Physical Design (PnR), DFT, Firmware, Emulation and Packaging teams to ensure aligned deliverables. Participate in cross functional meetings and identify and eliminate bottlenecks.
• Risk Management: Proactively identify risks and develop mitigation plans to avoid tape-out delays. Hold the development teams accountable for the scheduled quality deliverables.

 What you bring

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 15+ years or a Master’s degree with 13+ years.
• Experience: 10+ years in the semiconductor industry, with at least 5+ years in technical program/project management for ASIC/SoC products.
• Technical Knowledge: Deep understanding of the full ASIC design flow (RTL, Simulation, Synthesis, STA, PnR, DFT, Tape-out).
• Methodologies: Proven experience working with advanced process nodes and high-speed design.
• Tools: Proficiency in project management tools (Jira, Confluence, MS Project) and familiarity with EDA tools (Synopsys, Cadence).
• Experience with complex packaging (2.5D/3D IC, Si interposers, TSV).
• Knowledge of automotive functional safety and other automotive industry requirements
• Experience with hardware emulation platforms (Palladium, Veloce, ZeBu).
• Leadership: Strong ability to influence cross-functional teams without direct authority.
• Problem-Solving: Ability to analyze technical problems and drive solutions in a fast-paced environment.
• Communication: Excellent verbal and written communication skills, tailoring technical information for various stakeholders.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

We are seeking a Technical Marketing Senior Manager to join our System LSI - Custom SoC Sales and Business Development Team in San Jose, CA.  In this role, you will be responsible for identifying new opportunities for custom SoC (ASIC) business, conducting pre-shaping activities including technical requirements review and commercial discussions with potential customers, and building relationships with customers across the US market. This customer-facing role is highly cross-functional, where you will also manage day-to-day account management activities on both the technical and business sides with internal and external teams. We are seeking a high- energy professional with strong communication skills towards internal stakeholders and customers, as well as the ability to lead and develop new processes and ideas.  The successful candidate will thrive in a fast-paced, dynamic environment and be able to develop strategic relationships with customer teams. 

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy

Job ID: 42912

What You’ll Do

• Support the design-in activities and business operations by working with cross-functional teams across Engineering, Sales and Marketing teams to secure customer engagements.
• Act as local support interface for US customers for existing accounts and ongoing programs.
• Engage in engineering & commercial discussions with customers.
• Market survey and developing new customers and applications.
• Act as local POC for engineering/commercial VOC collecting and leading issue resolving by circling back internally with right internal POC.
• On-going and future projects reporting to both US and Korea Executives.
• Build relationships with internal stakeholder teams such as Marketing, Sales, Product Planning and development teams to know and understand S.LSI’s differentiated offerings and strategies.
• Work with customer teams to map their requirements to S.LSI offerings, identify potential gaps, and champion their cause by driving internal development teams to address their needs and deliver technical solutions.
• Develop and build relationships with customers’ teams to understand their technology needs, application requirements and jointly define the best silicon/platform solutions to enable customer’s products.

What You Bring

• Highly Technical Background with deep business acumen and the ability to synthesize technical and business information into clear, compelling executive-level presentations that influence internal and external stakeholders.
• Bachelor’s Degree in Engineering, Business, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• Technical sales and/or Marketing experience, management experience, technical/customer program management, or field applications engineering experience.
• Both Pre and Post Sales Customer Support.
• Good understanding of Semiconductor Industry, especially in SoC (System on Chip).
• Understanding or past experience with ASIC design and manufacturing flow, including advanced packaging is a Plus.
• Ability to analyze customer’s problem and needs from the component to system and application level based on customer’s requirements and purpose the solution that maps out to Samsung LSI’s offering.
• Frequent work and meetings are required with Korea.
• Korean language proficiency is a plus but not required.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role

As a Staff Security Firmware Test Developer, you’ll be the technical owner of security validation for enterprise SSD firmware — designing, building, and executing test strategies that ensure our drives meet the highest standards for data protection, compliance, and interoperability.

You’ll work at the intersection of firmware, hardware, and security protocols — validating features like Secure Boot, TCG OPAL, SPDM Firmware Attestation, Caliptra 2.1, and OCP NVMe Security Requirements across FPGA and ASIC platforms.

You’ll lead test automation, debug complex failures, and drive quality from design to production — ensuring our firmware is not just functional, but secure by design.

Responsibilities

• Lead end-to-end security validation for enterprise NVMe SSD firmware — from architecture review to production sign-off — ensuring compliance with Secure Boot, TCG OPAL, SPDM Firmware Attestation, Caliptra 2.1, and OCP NVMe Security Requirements.
• Design, build, and maintain automated test frameworks that validate security features across FPGA and ASIC platforms, enabling rapid regression and continuous integration.
• Debug and root-cause complex security failures — working closely with firmware, hardware, and security architects to resolve issues at the protocol or implementation level.
• Define and execute test strategies that prove “secure by design” — not just functional correctness, but cryptographic integrity, attestation, and tamper resistance.
• Own test coverage and quality gates for security-critical features — ensuring no release ships without passing validation against defined security specs.
• Stay ahead of evolving standards — actively track and implement upcoming TCG Storage Spec Requirements and other industry security mandates.
• Collaborate cross-functionally with firmware, hardware, and security teams — translating specs into testable requirements and driving alignment on security validation outcomes.

Minimum Qualifications

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field — or equivalent practical experience in firmware or embedded security.
• 5+ years of hands-on experience validating security features in firmware or embedded systems — specifically in NVMe SSDs, storage controllers, or similar hardware platforms.
• Proven experience validating at least 3 of the following:
• Secure Boot (UEFI/TPM/Bootloader)
• TCG OPAL (Self-Encrypting Drive)
• SPDM (Firmware Attestation)
• Caliptra 2.1 (or equivalent hardware root of trust)
• OCP NVMe Security Requirements
• TCG Storage Spec Requirements (upcoming or current)
• Strong experience building and maintaining automated test frameworks for firmware or hardware validation — with scripting (Python,Java, Bash, C) and CI/CD integration.
• Experience debugging low-level firmware/hardware issues — using tools like JTAG, logic analyzers, or firmware logs — with ability to trace failures across protocol layers.
• Working knowledge of NVMe protocol, PCIe, and storage security standards — with ability to read and implement test cases from specs.
• Experience working with FPGA or ASIC platforms — validating firmware behavior in pre-silicon or post-silicon environments.
• Strong ownership mindset — able to define test strategy, drive quality gates, and ensure security validation is not an afterthought, but built into the design.

Preferred Qualifications

• Experience with formal security certification processes (e.g., FIPS 140-3, Common Criteria, ISO 27001, or similar).
• Hands-on experience with Caliptra 2.1 or similar RISC-V-based hardware root of trust architectures.
• Experience with SPDM or similar attestation protocols in production firmware.
• Contributions to open-source security test frameworks or industry standards (e.g., TCG, OCP, NVM Express).
• Experience with security validation in cloud-scale storage environments (e.g., hyperscale data centers, enterprise storage arrays).
• Strong communication skills — able to present technical findings to engineering leadership and security compliance teams.

COMPENSATION: $110,000-$160,000

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness

Role Overview 

Astera Labs is seeking a Director, Global Talent Acquisition to lead and scale our worldwide recruiting function during a pivotal period of hypergrowth. This is a high-impact leadership role responsible for building and executing the talent acquisition strategy that will fuel our expansion across North America, APAC, EMEA, and India. 

As a key member of the People team, you will own the end-to-end recruiting lifecycle, from executing on the workforce plan and employer branding to team development and operational excellence. You'll partner closely with executive leadership to ensure we attract and hire the world-class engineering and business talent needed to maintain our position as the leader in AI infrastructure connectivity. This role requires a hands-on leader who thrives in fast-paced environments, has deep semiconductor industry expertise, and has a proven track record of building high-performing global recruiting teams from the ground up. 

Key Responsibilities 

Global Talent Acquisition Strategy & Execution 

• Develop and execute a comprehensive global talent acquisition strategy aligned with Astera Labs' aggressive growth objectives and workforce plans 
• Partner with executive leadership and hiring managers to forecast hiring needs, prioritize roles, and deliver against ambitious recruiting targets 
• Build scalable recruiting processes, systems, and metrics to support a rapidly growing organization 

Team Leadership & Development 

• Lead, mentor, and scale a global team of recruiters and recruiting coordinators across North America, APAC, EMEA, and India 
• Establish clear performance expectations, provide ongoing coaching, and foster a culture of excellence, accountability, and continuous improvement 
• Identify and develop future recruiting leaders within the organization 

Semiconductor & Technical Recruiting Excellence 

• Leverage deep semiconductor industry knowledge and networks to source and attract top-tier engineering talent in a highly competitive market 
• Drive innovative sourcing strategies to build robust pipelines for critical technical roles across hardware, firmware, and software disciplines 
• Serve as a trusted advisor to hiring managers on market trends, compensation benchmarking, and competitive intelligence 

Operational Excellence & Employer Branding 

• Implement and optimize recruiting tools, processes, and analytics to drive efficiency and improve candidate experience 
• Partner with Marketing and People teams to strengthen Astera Labs' employer brand and position the company as a destination for top talent 
• Ensure compliance with global hiring regulations and maintain consistency in recruiting practices across all regions 

Basic Qualifications 

• Bachelor's degree in Human Resources, Business Administration, or related field 
• 10+ years of progressive talent acquisition experience, including 5+ years in a leadership role managing global recruiting teams 
• Proven experience in the semiconductor or adjacent hardware technology industry 
• Demonstrated success scaling recruiting functions and building teams from scratch in high-growth environments 
• Experience leading distributed teams across multiple geographies (North America, APAC, EMEA, India) 
• Strong understanding of technical roles and the ability to effectively partner with engineering leaders 

Preferred Qualifications 

• Experience at a pre-IPO or recently public technology company during periods of rapid scale 
• Track record of recruiting for highly specialized semiconductor roles (analog/mixed-signal, ASIC, firmware, etc.) 
• Experience implementing or optimizing applicant tracking systems and recruiting analytics platforms 
• Strong executive presence with the ability to influence and build relationships at all levels of the organization 
• Data-driven mindset with experience using metrics to drive recruiting performance and strategic decisions 

Salary range is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

As a Senior/Staff Electronics Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. 

Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products.

Key Responsibilities

• Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.
• Develop comprehensive hardware electrical validation plans using correct test methods and processes.
• Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.
• Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.   
• Rework components on the PCBAs to unblock debugging activities.
• Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.
• Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.
• Support the new designs using knowledge of existing products to de-risk new features and requirements.
• Self-informed of new industry test standards and equipment to introduce modern testing methodologies.
• Specify test equipment, develop test fixtures, help improve hardware lab functions.

Required Skills

• Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug
• Bachelor degree in EE with 3+ years of experience in hardware test or design
• Expert understanding of design and test for power regulators, PDNs, Bode, clock generators
• Ability to produce test description from a schematic design, and execute and document results
• Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM
• Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.
• Automating lab equipment to optimize test processes, Python preferred

Preferred Skills

• Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.
• EMI/EMC compliance
• Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.
• PLM, Arena or equivalent
• Understanding of the ASIC/silicon product development process

Role Summary
We are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose.

Responsibilities — What You Will Own

1) Chief of Staff to Head of Engineering

•    Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs. 
•    Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate. 
•    Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes.
•    Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions.
•    Support org design, headcount planning, and hiring prioritization for engineering teams.
•    Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes
•    Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety.
•    Support the head of engineering with administrative and org related activities

2) Lead ASIC Tape out Management  (Silicon Programs)

•    Status management — collect and track status across functions contributing to ASIC tapeouts.
•    Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence.
•    IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops.
•    Quality & documentation — monitor quality KPIs, ensure engineering documentation completeness.
•    Requirements tracking — ensure PRDs/features are captured, tracked, baselined.
•    Resource monitoring — track compute, hardware, storage consumption and thresholds.
•    Internal reporting — generate status reporting for Silicon Engineering leadership.

3) Influence Without Authority

•    Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy.
•    Create order in ambiguous spaces; shape scope where it is undefined.

Qualifications

•    10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).
•    Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role.  
•    Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.
•    Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).
•    Proven ability to organize complex workflows and drive consistent follow-through.
•    High EQ and organizational awareness; can navigate tension and align diverse viewpoints. 
•    Exceptional written/verbal communication, structured thinking, and execution discipline.
•    Prior experience in leading RTL2GDSII chip design is a huge plus.

What Success Looks Like

•    Engineering leadership spends more time on strategic and technical decisions, less on coordination.
•    Milestones hit with fewer escalations and clearer accountability.
•    Status, risks, and decisions are crisp — never ad hoc or late.
•    Teams feel supported, not policed — trust increases, friction decreases without compromising on accountability  .
•    Ambiguity decreases over time as clarity and execution rhythm scale with the org.

Salary range is $216,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Overview:
We are seeking a highly skilled and experienced Technical Lead Power Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.

Key Responsibilities:

• Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.
• Design high-efficiency, high-reliability power circuits including:
• Buck / boost / buck-boost converters
• Multiphase regulators
• Hot-swap, protection, and sequencing circuits
• Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance of mismatches.
• Perform power integrity, transient response, stability, and thermal analysis.
• Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also, will be asked to do the same evaluation on overall system level design components.
• Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.
• Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.
• Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.
• Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.

Basic Qualifications:

• Education: Bachelor’s or Master’s degree in electrical engineering or related field.
• Experience: 5-8 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.
• Technical Skills:
• Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.
• Strong understanding of power integrity principles and techniques.
• Experience with power component selection and vendor collaboration.
• Hands-on experience with debugging power-related issues using lab equipment.
• Proficiency with lab equipment (oscilloscopes, electronic loads, spectrum analyzers).
• Soft Skills:
• Excellent problem-solving and analytical skills.
• Strong communication and teamwork abilities.
• Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Familiarity with high-speed interfaces such as PCIe, DDR, and USB.
• Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.
• Familiarity with Design for Manufacturability (DFM) considerations.
• Experience in thermal management and reliability analysis.

Why Join Us:

• Work on cutting-edge ASIC designs in a collaborative and innovative environment.
• Opportunity to influence power design strategies and contribute to product success.
• Access to state-of-the-art tools and resources to enhance your skills and career growth.

If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.

Base pay range for this role is $170,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Role Overview

Astera Labs is looking for a Senior Principal Engineering Program Manager to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale.

Key Responsibilities

• Program Ownership & Execution

  • Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM
  • Serve as the single point of ownership for assigned ASIC programs
  • Drive program planning, schedules, budgets, resources, and risk management

• Cross-Functional Leadership & Issue Resolution

  • Lead cross-functional teams across design, validation, product, test, firmware, software, and operations
  • Resolve complex pre-silicon and post-silicon issues through strong technical judgment

• Stakeholder Management & Alignment

  • Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders
  • Champion program execution while aligning engineering delivery with business and customer goals

Basic Qualifications

• BS or MS in Electrical, Electronics, or Computer Engineering
• 10+ years of ASIC product development experience in a semiconductor environment
• Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical Design
• Experience delivering ASICs in advanced nodes (<10nm)
• Proven ability to lead in a matrixed, high-pressure environment
• Strong program management skills; familiarity with MS Project, Jira, Atlassian tools, Scrum/WBS

Preferred Qualifications

• 5 or more years of experience as an ASIC Program Manager
• Experience with PCIe, memory, or high-speed data communication ASICs

Salary range is $205,000 to $250,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.

Principal Power and Board Design Engineer 

Overview:
We are seeking a highly skilled and experienced Power and Board Design Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.

Key Responsibilities:

• Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.

• Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance mismatches.

• Develop and implement board-level designs, to meet electrical and mechanical requirements with a deep understanding of PCB layout rules and constraints.

• Implement thermal solutions to maintain optimal operating temperatures for components.

• Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also will be asked to do the same evaluation on overall system level design components.

• Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.

• Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.

• Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.

• Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.

Qualifications:

• Education: Bachelor’s or Master’s degree in electrical engineering or a related field.

• Experience: 8-10 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.

• Technical Skills:

  • Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.

  • Strong understanding of power integrity principles and techniques.

  • Experience with power component selection and vendor collaboration.

  • Hands-on experience with debugging power-related issues using lab equipment.

• Soft Skills:

  • Excellent problem-solving and analytical skills.

  • Strong communication and teamwork abilities.

  • Ability to work in a fast-paced, collaborative environment.

Preferred Qualifications:

• Experience with high-speed interfaces such as PCIe, DDR, and USB.

• Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.

• Familiarity with Design for Manufacturability (DFM) considerations.

• Experience in thermal management and reliability analysis.

Why Join Us:

• Work on cutting-edge ASIC designs in a collaborative and innovative environment.

• Opportunity to influence power design strategies and contribute to product success.

• Access to state-of-the-art tools and resources to enhance your skills and career growth.

If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.

Base pay range for this role is $209,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

As a Principal Electronics Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. 

Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products.

Key Responsibilities:

• Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.
• Develop comprehensive hardware electrical validation plans using correct test methods and processes.
• Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.
• Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.   
• Rework components on the PCBAs to unblock debugging activities.
• Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.
• Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.
• Support the new designs using knowledge of existing products to de-risk new features and requirements.
• Self-informed of new industry test standards and equipment to introduce modern testing methodologies.
• Specify test equipment, develop test fixtures, help improve hardware lab functions.

Required Skills:

• Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug
• Bachelor degree in EE with 10+ years of experience in hardware test or design
• Define/refine hardware test methodologies and identify appropriate test equipment
• Expert understanding of design and test for power regulators, PDNs, Bode, clock gens
• Ability to produce test description from a schematic design, and execute and document results
• Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM
• Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.
• Automating lab equipment to optimize test processes, Python preferred

Preferred Skills:

• Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.
• EMI/EMC compliance
• Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.
• PLM, Arena or equivalent
• Understanding of the ASIC/silicon product development process

Base salary range is $185,000 USD-$230,000 USD, and will be determined based on the candidate's capabilities and employees in similar positions.

Overview
Join our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

Key Responsibilities

• Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
• Scripting and automation for ASIC methodology improvement.
• Accountable for quality and overall design success with the support of senior engineers.

Required Qualifications
Education & Experience:

• Bachelor’s degree in electrical engineering or equivalent
• 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

• Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
• Track record of delivering high quality digital designs from definition to production.
• Experience with functional and formal verification at block and chip level. 
• Understanding of clocking, CDC and RDC
• Experience with CMOS nodes (≤7nm)

Protocols & Integration:

• Familiarity with high-speed protocols—PCIe, Ethernet, DDR, or similar
• Experience with IP development and integration

Tools & Methodologies:

• Proven SystemVerilog and Python expertise in a production environment
• Familiarity with Synopsys and/or Cadence digital design flows
• Basic understanding of UVM-based verification methodologies

Professional Attributes:

• Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment
• Good communication and collaboration skills; comfortable working cross-functionally with global teams
• Self-directed learner who adapts quickly to changing requirements
• Customer-focused mindset with the ability to prioritize and work independently to deliver high quality designs.

Preferred Qualifications

• Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus
• Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Job Description

We are looking for a hands-on, experienced, self-motivated, and team oriented Senior Hardware Development Manager to drive development, validation and testing of existing and next generation Solid State Memory Drives. As a Senior Hardware Engineering Manager, you will lead a team of professional hardware engineers, interface with local cross-functional teams (Software/Firmware, Chip/SoC development and validation/quality) and collaborate with parent company (Korea) design teams to create top in class HW products. This role is based on-site full-time in San Jose, CA. Please note that candidates must be bilingual in English and Korean to be considered.

Responsibilities:

• Hiring, mentoring, and managing performance of hardware engineers.
• Play a major role in the HW architecture design, validation and test of each program.
• Managing schedules, resources, and budgets for all HW programs.
• Leading hardware design (PCB, SI/PI, mechanical/thermal, test and validation) through the entire lifecycle.
• Partnering with firmware, ASIC/SoC development, Test/Validation and  Korean development teams to ensure seamless product development and validation. 
• Lead and mentor hardware engineers to develop and enhance career paths for all team member.

Minimum Qualifications

• Must be bilingual in English and Korean.
• 8–12+ years of relevant work experience.
• 5 years in a managerial or people-leadership role.
• Experience in PCB layout, circuit design, simulation, and debugging tools. 

Preferred Qualifications:

• Experience working with remote sites for development and customer interactions
• Strong understanding of electro-mechanical and thermal system design.
• Proficiency in Signal Integrity (SI) and Power Integrity (PI) design and tools.
• Hands-on experience with high-speed design, including DDR4/5 and PCIe Gen 5/6.
• Working closely with product office/management to plan, prioritize and deliver constantly evolving customers product roadmap.
• Experience working with Contract Manufacturers (CM) and 3^rd party suppliers (Case design, compliance testing).
• Proven track record of taking products from initial concept to full production.
• Excellent communication of technical requirements, critical paths, and project schedules.
• Experience leading cross-functional teams to execute designs on time and within budget.
• Contributions to customer escalations / field problems including trouble shooting, containment actions, failure analysis report & corrective actions.
• Ability to develop and communicate priorities across multiple projects to meet goals.
• Exposure and working knowledge of PLM systems, product structures, and configurations.
• Knowledge of Engineering Change Management Process, Project Management tools, and Value Engineering concepts.
• Proven ability to make sound decisions and solve complex problems, even when faced with incomplete or ambiguous data.
• Technical design experience for product development process that includes: Planning phase, Requirements phase, Specifications, Design Reviews, Implementation, Prototype Release, Testing and Troubleshooting.
• Ability to communicate succinctly and in-depth in both verbal and written and ability to influence, interact effectively with peers and senior management personnel.

Education

• BS or MS Electrical or Mechanical Engineering or equivalent

COMPENSATION: $180,000/yr - $260,000/yr

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Team

You will join the System on Chip (SoC) Design Team at SK Hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions. As a Staff Engineer, you will own critical High speed interface IP, drive methodology improvements (such as AI-assisted design flows), and mentor engineers to ensure first-pass silicon success.

Responsibilities

• Design and verification of the high speed interface for next generation storage subsystem for NVME or Chiplet.
• Drive team efforts with multi-function teams from RTL development through silicon bring-up.

Minimum Qualifications

• 8 years of experience in ASIC design and deep knowledge in the design and integration of PCle logic.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
• Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

Preferred Qualifications

• Experience in PCle(Gen4/5/6) architecture in TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
• Proven experience with Link training, power state(L0/L0P/L1/L2), error handling (AER).
• Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
• Good plus to have experience in AI Assist design flow.

Education

•  Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
  

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

About the Team

We are seeking a highly skilled and experienced ASIC Design Engineer to join our ASIC design team. The role spans from RTL design through timing closure and tapeout readiness, with increasing responsibility based on seniority level (Sr., Staff, Sr. Staff). You will own critical modules or subsystems, drive design methodology improvements, and mentor junior engineers. Ideal candidates have 3+ years of industrial ASIC experience and a proven track record of successful tapeouts.

Key Responsibilities

All Levels:

• Design, simulate, and verify RTL modules using Verilog/SystemVerilog.
• Participate in design reviews, linting, CDC, and power analysis.
• Debug and resolve functional/timing issues across design stages.
• Collaborate with verification, DFT, physical design, and architecture teams.
• Contribute to design automation (Tcl/Python/Perl scripts) and methodology enhancements.

Staff / Sr. Staff Level Additions:

• Own complex IP blocks or subsystems end-to-end (from spec to tapeout).
• Lead design reviews, drive design signoff, and ensure quality across the team.
• Mentor junior engineers and set best practices for RTL coding, linting, CDC, etc.
• Interface with cross-functional teams (verification, physical design, packaging, test) to resolve critical issues.
• Contribute to architecture discussions and micro-architecture trade-offs.

Required Qualifications

• 3+ years of industrial experience in ASIC design.
• Strong proficiency in RTL design using Verilog/SystemVerilog; familiarity with UVM is a plus.
• Familiarity with standard interfaces (AXI, AHB, APB, SMBus, UART, etc.).
• Proficiency in Tcl/Python/Perl/Shell for automation and flow customization.
• Strong communication, problem-solving, and teamwork skills.

Preferred Qualifications

• Successful tapeout(s) in advanced nodes.
• Experience with ARM/RISC-V-based SoCs or custom accelerators.
• Experience with UVM-based testbenches.
• Knowledge of UPF/CPF, power gating, clock gating.
• Understanding of floorplanning, placement, routing impact on timing.
• For Staff/Sr. Staff roles — demonstrated ability to lead design efforts or mentor

What We Offer

• Comprehensive health, dental, vision, and 401(k) matching, onsite gym and breakfast, lunch and dinner
• Collaborative, innovation-driven engineering culture
• Opportunity to work on cutting-edge enterprise SSD controller for AI and data center applications

Efficient is looking for a seasoned Design Verification & Emulation Manager to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers.

This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond! 

Key Responsibilities 

• Define end-to-end verification strategy from block-level through full-chip simulation to emulation and prototyping
• Own UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoption
• Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling
• Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising
• Deliver pre-silicon platforms for early software development in partnership with firmware and software teams
• Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments
• Own functional coverage models and sign-off criteria, driving closure across simulation and emulation combined
• Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution
• Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership
• Build, mentor, and scale a high-performing team of verification and emulation engineers
• Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness
• Represent verification and emulation in tapeout readiness reviews and program-level decision forums
• Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams
• Manage emulation lab infrastructure, including hardware resources, licensing, and vendor relationships
• Evaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques.
• Define right DV  mix for in-house  vs outsourcing to 3rd party vendors. Coordinate 3rd party vendor resources towards achieving project goals.

Required Qualifications & Experience 

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
• Experience: 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
• Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.
• Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
• Languages & Tools: Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
• SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
• Leadership: Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.
• Execution: Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).

Preferred Qualification

• Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.
• Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.
• Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).

We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Efficient is seeking a Lead STA Engineer to join our growing team. The Timing Lead will work on timing convergence and methodology hands on for the world’s most energy-efficient, general-purpose processor. This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies. The role is cross functional and we are a integrated highly interdisciplinary team of world class engineers.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Drive and develop Timing flows, methodology for state of the art finfet and multi patterning  based technologies from scratch in Cadence Tempus or Synopsys Primetime.
• Own and drive timing convergence of IP, Subsystem and SOC blocks.
• Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation.
• Develop slew rate, glitch noise checks to ensure robust design quality.
• Develop custom timing checks as pertains to Efficients proprietary Ultra low power architecture.
• Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints.
• Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design.
• Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective.
• Work with 3rd party vendor resources and coordinate their work in the timing domain.
• Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes.

Required Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies.
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques
• Hands-on experience in  timing convergence of high-frequency and low power designs.
• Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining.
• Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs.
• Excellent scripting skills in TCL, shell and python.

Desired Qualifications 

• Knowledge of computer architecture
• Knowledge of physical design and ASIC implementation
• Experience in full chip sign-off budgeting
• Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
• Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
• Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
• Experience in integrating analog or mixed-signal macro on top-level design.

We offer a competitive salary for this role, generally ranging from $200,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Senior ASIC Front-End Design Engineer

Summary:

• As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
• Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
• Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
• You will be a trusted self-starter who can work with very little guidance or oversight.
• This position is located in: San Jose, CA (Hybrid)

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC RTL design and/or architecture experience
• Proven track record with the development of complex SoCs
• Strong understanding of digital design fundamentals and methodologies
• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:

Experience in any of the following areas:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• IP integration (SerDes, controllers, processors, etc.)
• Perl, TCL, C/C++, Make

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

#LI-Hybrid

Senior ASIC Design Verification Engineer

Summary:  

• As a Senior ASIC Verification Engineer, you will be responsible for all aspects of digital SoC verification.
• You will work the architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.
• You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics.
• This position is located in: San Jose, CA

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC verification experience
• Strong understanding of ASIC verification fundamentals and industry standard methodologies
• Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
• Experience with the full verification flow, from spec to coverage analysis to gate level sim
• Debugging failures in simulation to root cause problems
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:
Experience in any of the following areas:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• Third party IP (SerDes, controllers, processors, etc.)
• Modular and Reusable Testbench architecture
• Design for re-use of pre and post silicon tests and infrastructure
• Automation of testbench creation, tests, regression, or EDA tools
• Knowledge of SystemC and/or DPI

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

Program Manager (Chip Development)

Summary:

• We're seeking an experienced and dynamic Program Manager to lead the end-to-end development lifecycle of complex integrated circuits (ICs). This role is all about defining, planning, executing, and finalizing chip development projects, making sure they're delivered on time, within budget, and to the highest quality standards, while strictly adhering to automotive industry requirements. You'll need a strong technical background in semiconductor design and manufacturing, coupled with exceptional leadership, communication, and problem-solving skills, particularly in the context of safety-critical and security-relevant systems, and a proven ability to manage customer relationships effectively.

• This position is located in: San Jose, CA

Key Responsibilities

• Program Leadership & Strategy:
• Define program scope, objectives, deliverables, and success criteria in collaboration with cross-functional teams (e.g., Architecture, Design, Verification, Physical Design, Software, Test, Product, Operations).
• Develop and maintain comprehensive program plans, schedules, and budgets, including critical path identification and risk mitigation strategies.
• Drive cross-functional alignment and accountability across all phases of the chip development lifecycle, from concept to silicon validation and mass production.
• Act as the primary point of contact for the program, providing regular updates to stakeholders, senior management, and external partners.
• Automotive Standards Compliance & Management:
• Ensure full compliance with ISO 26262 (Functional Safety) throughout the chip development lifecycle, including defining Safety Goals, ASIL decomposition, managing safety requirements, and overseeing safety analyses (e.g., FMEDA, FTA).
• Oversee adherence to ISO/SAE 21434 (Automotive Cybersecurity), managing cybersecurity risk assessments (TARA), defining cybersecurity goals, and ensuring secure design & verification practices for the IC.
• Drive implementation and adherence to Automotive SPICE (ASPICE) process requirements, ensuring robust software and hardware development processes, traceability, configuration management, and quality assurance.
• Work closely with functional safety and cybersecurity managers to integrate these standards seamlessly into the overall program plan and execution.
• Prepare for and support internal and external audits and assessments related to ISO 26262, ISO/SAE 21434, and ASPICE.
• Customer Relationship Management:
• Serve as the primary technical and program interface to key customers, understanding their needs, expectations, and ensuring their satisfaction throughout the development lifecycle.
• Effectively communicate program status, technical progress, and any potential issues or changes to customers.
• Proactively manage customer expectations and negotiate technical and schedule tradeoffs to achieve mutual success.
• Translate customer requirements into actionable internal development plans and ensure effective feedback loops.
• Execution & Monitoring:
• Lead and motivate diverse technical teams, fostering a collaborative and high-performance environment.
• Track program progress against milestones, identify deviations, and implement corrective actions.
• Proactively identify and manage program risks, dependencies, and issues, escalating as necessary.
• Facilitate effective communication and decision-making across all levels of the organization.
• Manage change requests and ensure proper impact analysis and approval processes are followed.
• Technical Acumen:
• Possess a strong understanding of the complete chip development flow, including RTL design, synthesis, place and route, timing closure, verification methodologies, DFT, analog/mixed-signal integration, packaging, and silicon bring-up.
• Collaborate with technical leads to resolve complex engineering challenges.
• Ensure adherence to design methodologies, quality standards, and industry best practices.
• Stakeholder Management:
• Build and maintain strong relationships with internal teams, external vendors (e.g., foundries, IP providers), and customers.
• Manage expectations and negotiate tradeoffs to achieve program goals.
• Prepare and deliver compelling presentations to various audiences, including executive reviews and technical forums.
• Continuous Improvement:
• Conduct post-mortems and lessons learned sessions to identify areas for process improvement.
• Implement best practices in program management and contribute to the evolution of our development methodologies.

Qualifications

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience:
• 8+ years of experience in the semiconductor industry, with at least 3-5 years in a dedicated program or project management role for chip development projects.
• Proven track record of successfully leading multiple complex ASIC/SoC development programs from concept to high-volume production.
• Demonstrable experience and strong understanding of ISO 26262, ISO/SAE 21434, and Automotive SPICE (ASPICE) requirements and implementation in semiconductor development.
• Experience with Automotive Safety Integrity Levels (ASILs) and Threat Analysis and Risk Assessment (TARA) processes.
• Strong understanding of semiconductor fabrication processes (e.g., FinFET, FD-SOI) and packaging technologies.
• Experience with various silicon technologies (e.g., CPUs, GPUs, DSPs, AI accelerators, custom ASICs) for automotive applications is a plus.
• Technical Skills:
• Familiarity with industry-standard EDA tools and design flows (e.g., Cadence, Synopsys, Siemens EDA).
• Knowledge of various verification methodologies (e.g., UVM, formal verification).
• Understanding of power management, clocking architectures, and high-speed interfaces.
• Program Management Tools & Skills:
• Proficiency and hands-on expertise with Atlassian tools, specifically Jira for issue tracking, project management, and reporting, and Confluence for documentation, knowledge sharing, and collaboration.
• Strong understanding of program management methodologies (e.g., Agile, Waterfall, Hybrid). PMP or equivalent certification is highly desirable.
• Excellent analytical, problem-solving, and decision-making abilities.

Desired Attributes

• Exceptional Communication: Outstanding verbal and written communication skills, with the ability to articulate complex technical information clearly and concisely to diverse audiences, including customers, regulatory bodies, and auditors.
• Strong Leadership: Ability to inspire, motivate, and guide cross-functional teams without direct authority.
• Results-Oriented: A drive to achieve aggressive goals and a commitment to delivering high-quality, safety-compliant, and secure products.
• Proactive & Resourceful: Ability to anticipate challenges, identify solutions, and adapt to changing priorities in a fast-paced and regulated environment.
• Collaborative: A team player who thrives in a collaborative environment and builds strong working relationships internally and externally.
• Customer-Centric: A strong focus on understanding and meeting customer needs, with a track record of building and maintaining positive customer relationships.
• Attention to Detail: Meticulous approach to planning, execution, and monitoring of program activities, with a strong emphasis on documentation for compliance.
• Business Acumen: Understanding of the automotive market, customer needs, and the financial implications of program decisions.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary will vary depending on factors such as individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $150,000 - $230,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedul.e The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency.

This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities 

• Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones
• Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria
• Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors
• Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases
• Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning
• Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs
• Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions
• Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams
• Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases
• Own the bug lifecycle — triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects
• Manage the regression framework — defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines
• Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments
• Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams
• Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews
• Represent verification readiness in tapeout sign-off reviews and program-level decisions

• Support running gate-level simulations as part of design signoff.
• Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.

Required Qualifications & Experience 

• Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.
• UVM Mastery: Deep expertise in UVM-based testbench architecture and constrained-random verification methodology — not just usage, but architectural decision-making and optimization.
• SystemVerilog: Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages.
• Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
• Debug Skills: Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels.
• SoC Architecture: Strong understanding of modern SoC building blocks — processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
• Scripting & Automation: Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development.
• Communication: Clear and effective communication of verification status, risk, and trade-offs to technical peers and program leadership.

We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.