Efficient is seeking a Lead STA Engineer to join our growing team. The Timing Lead will work on timing convergence and methodology hands on for the world’s most energy-efficient, general-purpose processor. This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies. The role is cross functional and we are a integrated highly interdisciplinary team of world class engineers.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Drive and develop Timing flows, methodology for state of the art finfet and multi patterning  based technologies from scratch in Cadence Tempus or Synopsys Primetime.
• Own and drive timing convergence of IP, Subsystem and SOC blocks.
• Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation.
• Develop slew rate, glitch noise checks to ensure robust design quality.
• Develop custom timing checks as pertains to Efficients proprietary Ultra low power architecture.
• Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints.
• Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design.
• Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective.
• Work with 3rd party vendor resources and coordinate their work in the timing domain.
• Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes.

Required Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies.
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques
• Hands-on experience in  timing convergence of high-frequency and low power designs.
• Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining.
• Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs.
• Excellent scripting skills in TCL, shell and python.

Desired Qualifications 

• Knowledge of computer architecture
• Knowledge of physical design and ASIC implementation
• Experience in full chip sign-off budgeting
• Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
• Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
• Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
• Experience in integrating analog or mixed-signal macro on top-level design.

We offer a competitive salary for this role, generally ranging from $200,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

 Efficient is seeking a CAD Lead - PD flows/infrastructure  to join our growing team. The ideal CAD Lead would have worked on significant portion of the full gamut of Physical Design flows and flow infrastructure (flowtracer etc).  This role is in a newly formed hardware engineering group and is the seed hire for this discipline. You will get to setup CAD flows and infra from scratch and influence and shape this aspect in the future.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Drive and develop PD flows, methodology for state of the art finfet and multi patterning  based technologies from scratch in Cadence Tempus or Synopsys Primetime.
• Help develop repeatable, predictable , design and process agnostic PD flows.
• Develop state of the art flow infrastructure to enable consistent and rapid design under tight schedule constraints for multiple product lines in the energy efficient edge AI computing market.
• Work closely with PD team leads to propose and develop end to end build and signoff flows.
• Build regression frameworks for ensuring high quality flows and achieve hardware engineering vision of spending 90% or more time on actual design tasks and NOT wrestling with tools.
• Develop collateral quality checking utils to ensure high design efficiency.
• Develop and deploy a unified environment for specifying all collaterals (stdcell, memory, PDK, hardips…)  and all flow dependencies (cycle time, PVTRC corners, per flow design and process dependent configuration).
• Work with 3rd party vendor resources and coordinate their work.
• Continuously work on improving flow consistency and efficiency in the context of multiple product lines.

Required Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• Strong python other scripting programming skills.
• Experience in developing workflow orchestration infrastructure or tools for hardware development (Airflow, flowtracer etc)
• Familiarity with kubernetes and containerization
• Experience implementing regression frameworks
• SQL or other database proficiency (MongoDB ..)
• Intimate knowledge of hardware design workflows for Physical Design and RTL/DV.
• Excellent scripting skills in TCL, shell and python.

Desired Qualifications & Experience Requirements

• Experience in full chip RTL/DV and PD flows.
• Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
• Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
• Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
• Experience in integrating analog or mixed-signal macro on top-level design.
• Experience in verifying IP collaterals.

We offer a competitive salary for this role, generally ranging from $180,000 to $220,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Efficient is seeking a Physical Design - Front End Lead  to join our growing team. The ideal candidate would drive front-end PD methodology (Synthesis, LEC, CLP, Low Power Design) hands on. We believe in a correct-by-construction philosophy and place a great emphasis on ensuring frontend flows accurately model signoff considerations. The Front End lead will ensure that we have methodologies in place to ensure the design built considers the right tradeoff between timing and power and optimizes for both aspects. The role is cross functional and we are an integrated highly interdisciplinary team of world class engineers. 

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Drive and develop frontend flows and methodology for the industry defining Energy efficient general purpose processors.
• Ensure synthesis flows accurately model all aspects of PPA to enable highly optimized and correct by construction design to enable tight and quick design loops and design convergence
• Develop LEC flows to continuously assess logical correctness of the design as the design progresses to mature thru the design lifecycle.
• Define UPF methodology and develop and converge UPF for all complex subsystems and SOC in collaboration with RTL
• Develop Conformal based ECO flows with an aim to address ALL ECOs rapidly..
• Develop flows for rapid uarch prototyping in conjunction with RTL.
• Deploy power and physical aware synthesis flows.
• Work with 3rd party vendor resources and coordinate their work.
• Continuously work on improving flow consistency and efficiency in the context of multiple product lines.

Required Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for frontend flows, like Genus, Fusion Compiler, Design Compiler, Conformal, Formality.
• Experience with hierarchical design and modelling
• Hands-on experience in convergence of high-frequency and low power designs.
• Knowledge of static timing analysis, defining constraints and exceptions and low power design techniques (isolation, level shifting, power switches..).
• Experience with low power implementation typical in industry,
• Excellent scripting skills in TCL, shell and python.

Desired Qualifications & Experience Requirements

• • Experience in design space exploration for maximizing PPA using synthesis flows. Doing feasibility level sweeps to figure out optimal design build points.
  • Proficiency with industry-grade physical design flow.
  • Definition of design constraints.
  • Knowledge of technology fundamentals and its implications to physical design

We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.