Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions—deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs.
• Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
• Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations.
• Familiarity with advanced packaging or multi-die integration and its impact on physical design.
• Experience with ECO methodologies and DFT-aware physical design.
• Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Salary range is CAD $180,000 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

At Tenstorrent, we build open, state of art compute for AI and RISC‑V. You will create and own our quality organization across hardware systems and custom silicon, setting the standards that let us scale fast without sacrificing reliability. This role requires regular domestic and international travel to suppliers, contract manufacturers, and Tenstorrent sites.

This role is hybrid, based out of Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• 7+ years driving hardware or semiconductor quality across design, process, incoming, supplier, and systems.
• Experienced with servers, PCs, and/or PCIe cards, plus ASIC or custom silicon quality.
• Comfortable leading global CM and supplier audits and traveling frequently worldwide.
• You have experience working in companies that have transitioned from R&D to Product focused. 
• Have built a quality org and QMS from zero and can explain your design choices.

What We Need

• Build the quality team from scratch, including org design, hiring, and cross‑functional ownership.
• Own the QMS, including ISO 9001, documentation, audits, KPIs, and continuous improvement.
•  Drive Design for Quality for hardware and silicon, from bring‑up through post‑silicon validation.
•  Define manufacturing controls, FMEAs, control plans, NPI quality gates, and supplier quality programs.

What You Will Learn

• How to apply open, state of art compute to demanding hardware and silicon quality problems.
• To shape quality culture, metrics, and supplier relationships for a fast‑growing silicon company.
• How reliability data, field returns, and standards like JEDEC and IPC drive product decisions.
• To scale quality systems that support hyperscaler, cloud, and semiconductor startup customers.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an AI Processor IP Product Engineer to be the technical bridge between our cutting-edge AI processor technology and customer success. You'll guide customers through the integration of our advanced AI processors, RISC-V CPUs, and chiplet solutions into their SoCs, ensuring optimal performance and accelerated time-to-market. If you thrive in customer-facing roles and want to shape the deployment of revolutionary AI hardware across the industry, join our team.

This role is hybrid, based out of Toronto, Canada or Vancouver, Canada.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with deep technical expertise in ASIC design and IP integration.
• Experienced problem-solver who excels at debugging complex system-level issues and silicon bring-up.
• Strong communicator who builds trusted relationships while managing technical engagements across the support lifecycle.
• Passionate about enabling customer success and translating complex technical concepts into actionable guidance.

What We Need

• 3-5 years in the semiconductor industry with a degree in EE or related field.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Strong background in analog/digital design tools, silicon validation, and system-level debug.
• Proven track record in customer-facing engineering roles with excellent communication skills.

What You Will Learn

• How to integrate state-of-the-art AI processors and chiplet architectures into diverse customer SoCs.
• Advanced debugging techniques spanning pre-silicon simulation to post-silicon validation.
• Strategies for influencing product roadmaps through direct customer feedback and technical insights.
• The full spectrum of IP productization—from technical documentation to customer training and support processes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for an ASIC Design Methodology Engineer to advance our design infrastructure and flows across RTL development, verification, and physical implementation. This role is ideal for engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate silicon success.

This role is hybrid, based out of Toronto, Ottawa, Austin, or Boston.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A strong advocate for design quality and productivity, with expertise in ASIC design flows.
• Skilled in RTL design and familiar with static and dynamic analysis tools.
• Comfortable automating design checks and improving methodology for scalability and reuse.
• A collaborative engineer who partners effectively across RTL, verification, and backend teams.

What We Need

• Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration.
• Own and evolve static code analysis (Lint, CDC, RDC, DFT) and RTL-netlist logic equivalency design methodologies
• Develop synthesis timing constraints (SDC) and low power design specifications (UPF)
• Support RTL-to-GDS flow enablement, ensuring clean handoffs and sign-off readiness.
• Collaborate with EDA vendors and internal tool owners to optimize performance, quality, and runtime.

What You Will Learn

• How large-scale AI SoCs are architected, integrated, and brought to silicon.
• How methodology choices directly impact design performance, power, and verification closure.
• How to build and scale ASIC design flows supporting cutting-edge compute architectures.
• How to integrate cross-functional workflows across design, DFT, DV, physical, and firmware teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance-aware design.

This role is hybrid, based out of Toronto, Ottawa, Boston, or Austin. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.

What We Need

• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Strong synthesis and timing closure awareness to support backend teams.
• Prior experience in on-chip fabric and interconnect designs is an asset.

What You Will Learn

• How cutting-edge AI chips are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How to blend custom logic with standard SoC elements for power and scale.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will own end-to-end technical engagements, translating complex architectural advantages into customer wins while shaping our product roadmap through direct market feedback. If you combine deep technical expertise with exceptional customer engagement skills and want to drive the adoption of next-generation compute IP, join our team.

This role is hybrid, based out of the United States or Canada near one of our main office locations.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with proven success in CPU/GPU/NPU IP sales engagements.
• Technical expert who can articulate complex architectural benefits and conduct deep-dive analyses.
• Self-driven professional who independently manages multiple customer relationships from discovery to win.
• Strategic thinker who identifies customer pain points and positions solutions effectively.

What We Need

• 7+ years in the semiconductor industry with a degree in EE or related field including customer-facing roles in CPU IP.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Deep technical knowledge of CPU architectures, semiconductor technologies, and system-level design.
• Exceptional presentation and communication skills with ability to engage all organizational levels.
• Proven track record of technical wins and managing multiple simultaneous accounts.

What You Will Learn

• How to position cutting-edge RISC-V and AI accelerator IP against industry incumbents.
• Advanced customer engagement strategies for complex technical sales in the semiconductor industry.
• Direct influence on product development through customer feedback and market insights.
• The complete IP business cycle from evaluation through design win and production success.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade-offs and verification. A background in electrical engineering, electronics or relevant fields is required. Must love all things high speed!

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above (e.g. 100GbE, GDDR6, PCIe Gen5+).
• You’re comfortable working with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT as well as knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards.
• You are proficient with PCB ECAD tools (ideally Cadence Allegro).
• You communicate clearly (written and verbal), think critically, and love solving complex signal integrity problems.
• You’re enthusiastic about all things high speed and enjoy collaborating across teams

What We Need

• Design, extract, and simulate complex breakout structures, including end-to-end simulations and validation against physical hardware. Perform simulation and extraction of board models for both SI and PI.
• Contribute to design and sign-off with internal and external ASIC packaging teams, ODMs, and internal layout teams. Create design specifications, work with external vendors, and drive adoption of new interconnect and packaging technologies.
• Actively participate in design reviews, providing insight from your SI/PI expertise and a broader system perspective.
• Support post-silicon bring-up and help troubleshoot production and field failures related to signal and power integrity. Document design processes and provide training/knowledge sharing to other team members.

What You Will Learn

• How to work at the cutting edge of high-speed interconnects, influencing the next generation of ASIC packaging and PCB architectures.
• Deep exposure to advanced ASIC packaging flows and collaboration models with internal and external packaging teams.
• Hands-on experience with emerging high-speed connector technologies and materials, including evaluating material trade-offs for performance and manufacturability.
• Best practices for end-to-end SI/PI validation, from simulation through to lab correlation, post-silicon bring-up, and field failure analysis.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Proto is accelerating the world's transition to an open economy with products that increase access and independence for everyone. We're building Bitkey, a simple and safe self-custody bitcoin wallet that will put customers in control, as well as hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We're developing these products in the open - you can read more about them at bitkey.build and mining.build. Within Proto, our Bitcoin Products team delivers the product and go-to-market strategy, software, firmware, and custom silicon needed to make Bitkey and our ambitious mining initiatives a reality. Come build the future of money with us!

The Role

We are looking for an ASIC Validation Engineer to help bridge the gap between custom mining silicon design and real-world operation. In this highly hands-on, lab-focused role, you'll work closely with ASIC designers and system engineers to debug issues, build test infrastructure, and generate the data needed to enable rapid design iteration and system-level development.

You Will:

• Bring up new silicon on bench platforms, evaluation boards, and system hardware
• Debug issues across ASIC, board, firmware, and system interactions
• Develop bench tests, scripts, and tools to exercise silicon features and collect data
• Build and maintain test setups (lab automation, instrumentation, fixtures, scripts)
• Partner with ASIC designers to validate functionality and root-cause failures
• Work with system engineers to ensure silicon performs correctly in target system environments, including mining systems
• Generate and analyze data to support design decisions, characterization, and bring-up
• Create lightweight, reusable test workflows and documentation for the broader team
• Support early manufacturing efforts with practical validation and debug, as needed
• Travel up to 20% to the labs in Oakland, CA or Toronto, Canada

You Have:

• Bachelor's degree in Electrical Engineering or related field
• 4+ years of experience in silicon validation, hardware test, or related roles
• Strong hands-on experience in a lab environment (bench bring-up, debugging, instrumentation)
• Solid understanding of digital systems and basic analog concepts
• Experience writing scripts or tools (Python preferred) for test and data analysis
• Comfortable debugging issues that span multiple layers (ASIC ↔ board ↔ system)
• Clear communication skills and ability to work closely with cross-functional teams

Preferred:

• Experience with ASIC or FPGA bring-up and validation
• Familiarity with common interfaces (SPI, I2C, JTAG, UART, etc.)
• Experience using lab equipment (oscilloscopes, logic analyzers, power supplies, etc.)
• Exposure to high-performance, power-dense systems (e.g., mining ASICs, accelerators, or similar)
• Experience building test automation or internal tooling
• Familiarity with data analysis and visualization

Nice to Have

• Experience working with early silicon / first bring-up environments
• Exposure to manufacturing test or ATE
• Experience working on systems with tight power, thermal, and performance constraints

About The Team 

Cerebras builds wafer-scale AI processors—single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras’ pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE, and NeurIPS) and directly influences the design of next-generation wafer-scale systems. 

About The Role 

Most AI research today is shaped by the constraints of existing hardware. This role starts from the other direction: what would you build if the architecture let you rethink the fundamentals? You will design and develop AI models and training methodologies on wafer-scale hardware, working at the level of optimization theory, model architecture, and statistical foundations rather than assembling existing components. 

The ATG sits at the intersection of AI, computational science, and computer architecture, and your work will draw on all three. You will collaborate closely with Cerebras’ ASIC, compiler, kernel, and AI teams as well as external partners at universities and national laboratories. 

What You Will Do 

• Design AI models and training methods from first principles, leveraging architectural properties of wafer-scale hardware that are unavailable on conventional platforms. 
• Investigate how techniques from computational science—numerical methods, PDE solvers, simulation—can inform and advance AI model design, and explore hybrid workflows that couple simulation and learning. 
• Develop a deep understanding of the hardware substrate and use it to guide algorithmic choices: model structure, optimization strategy, memory access patterns, numerical precision. 
• Publish findings and present at top-tier venues (NeurIPS, ICML, ICLR, etc.); represent Cerebras in the broader AI/ML research community. 
• Inform the design of future Cerebras hardware and software by identifying the computational patterns that matter most for next-generation AI workloads. 

What We Are Looking For 

• PhD in Machine Learning, Computer Science, Applied Mathematics, Statistics, Physics, or a related quantitative field preferred; exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply. 
• Mathematical maturity: comfort with the theory behind gradient methods, loss landscapes, generalization, and the relationship between model structure and data statistics. 
• Track record of published research at top-tier AI or computational science venues. 
• Proficiency in Python and PyTorch; comfort with C or other low-level languages is a strong signal. 
• Excellent communication and interpersonal skills: able to present complex technical material to both ML and systems audiences, and to collaborate effectively in a fast-paced, small-team environment. 

Why This Opportunity Is Exciting And Unique 

• You will have direct access to hardware that changes what’s algorithmically possible. Tens of PB/s of memory bandwidth and fine-grained dataflow execution open design spaces that don’t exist on GPU clusters. 
• You will work alongside researchers in computational science, computer architecture, and performance engineering. The synthesis across these fields is central to ATG’s approach. 
• Your research will influence silicon - ATG’s findings directly shape the design of future Cerebras chips and systems. 

We are hiring for multiple positions across experience levels. If this work resonates, we encourage you to apply. 

The Role 

We are seeking a highly skilled and motivated Manufacturing Bring-up Engineer to join our team. As the Manufacturing Bring-up Engineer you will support our system level bring-up process execution, implementation, and evolution in the manufacturing pipeline. This is a high visibility role that requires strong technical expertise, coordination, and collaboration to deliver our product from manufacturing to the customer. 

Responsibilities 

• Support the Cerebras manufacturing bring-up process execution to configure, test, and validate system performance prior to customer shipment 

• Collaborate cross-functionally with Asic, SW, Diagnostics, and QA teams to further automate and streamline the workflow for optimal manufacturing efficiency 

• Troubleshoot and resolve technical issues during system bring-up across Asic, SW, and QA domains 

• Design and implement efficient processes to manage and track system bring-up status and progress 

• Track and report on critical bring-up metrics to drive continuous improvement  

• Implement further SW automation and efficiencies to effectively scale the manufacturing bring-up process in support of the manufacturing roadmap 

Skills & Qualifications 

• BS or MS in EE, ECE, CS or equivalent work experience 

• 3+ years of industry experience in an operations environment 

• Experience in hardware bring-up and the debug of complex systems 

• Working knowledge and experience in Asic bringup and test processes 

• Working knowledge of scripting in languages such as Python and/or Perl 

• Proven experience in system bring-up and validation of complex computer systems or equivalent technologies 

• Understanding of computer system architecture and hardware components  

• Proficiency in scripting and automation tools for system bringup  

• Excellent problem-solving and communication skills with the ability to work collaboratively in a fast-paced environment 

• Very strong coordination and collaboration skills to manage a business-critical workflow directly in support of customer demand 

Preferred: 

• Familiarity in creating test and s/w infrastructure at large scale 

• Working across global time zones  

Location 

Sunnyvale, California/ Bangalore, India/Toronto, Canada.

The base salary range for this position is $170,000 to $230,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:

Sunnyvale, California.

Bangalore, India

Toronto, Canada 

The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:
Bangalore, India

Toronto, Canada

Sunnyvale, California.

For Sunnyvale: The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

About The Role

We're looking for a deeply technical, hands-on software engineer to join our on-field Kernel Reliability team. You'll help tackle a critical challenge: improving the reliability of our advanced compute clusters and the underlying inference, training, and internal production services. In this role, you'll work close to the code and design solutions that will scale with our rapidly growing system production and software service offerings. If you have strong fundamentals in systems, debugging, and failure analysis—and enjoy building tools and solving hard reliability problems—we want to hear from you. New college graduates are welcome.

Responsibilities

• Contribute to the technical roadmap and execution for kernel-centric reliability of our internal and customer-facing systems.
• Partner with System and Cluster Operations teams to reduce system and service downtime after failure through tooling, analysis, and hands-on debugging support.
• Work with the Debug Team to enhance debug tools with the goal of speeding up failure analysis.
• Collaborate with software teams to improve the software stack—including kernels—to improve on-field debugging and failure analysis.
• Work with ASIC and hardware architecture teams to co-design next-generation architectures with reliability and ease of debug in mind.
• Participate in incident response, root-cause analysis, and post-mortems; drive follow-ups that measurably improve reliability over time.

Skills & Qualifications

• We recognize great engineers come from different backgrounds. If you're excited about the role, we encourage you to apply even if you don't meet every qualification.
• Required (or demonstrated through projects/internships/coursework):
  • Strong programming skills in C/C++ and Python.
  • Solid foundations in operating systems, computer architecture, and systems programming fundamentals.
  • Ability to debug complex issues using logs, traces, and standard debugging workflows; interest in root-cause analysis.

Nice to have:

• Exposure to parallel and distributed programming (message passing, multicore, GPU, embedded, etc.).
• Experience building or using debug/diagnostic tools (debuggers, core dump handling, tracing, sanitizers, profilers, etc.).
• Familiarity with debugging distributed and parallel applications (deadlocks, livelocks, race conditions, etc.).
• Knowledge of computer architecture concepts (instruction pipelining, multithreading, networking, memory systems, etc.).
• Operations & Monitoring: familiarity with monitoring, incident response, and post-mortem culture.

About The Team 

Cerebras builds wafer-scale AI processors—single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras’ pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE, and NeurIPS) and directly influences the design of next-generation wafer-scale systems. 

About The Role 

We are seeking R&D Engineers to join Cerebras' Advanced Technology Group. You will design and implement workloads that establish new performance benchmarks on wafer-scale hardware, leveraging architectural features that no traditional platform offers. The 
scope ranges from large-scale scientific simulations to emerging AI/ML models, and the work sits at the intersection of algorithm design, compiler co-optimization, and hardware architecture. You will collaborate closely with Cerebras’ ASIC, compiler, kernel, and AI teams as well as external partners at universities and national laboratories. 

What You Will Do 

• Design and implement challenging scientific computing and AI workloads on Cerebras’ Wafer-Scale Engine, targeting performance results that advance the state of the art. 
• Lead algorithm–hardware co-design efforts with internal R&D teams and external research partners, turning architectural capabilities into measurable application-level advantages. 
• Build analytical performance models that quantify bottlenecks, guide optimization, and inform future chip and compiler design decisions. 
• Contribute to Cerebras’ multi-year technology roadmap by identifying high-impact workloads, proposing architectural experiments, and validating them on silicon. 
• Publish findings and present at top-tier conferences and journals; represent Cerebras in the broader HPC and AI research communities. 

What We Are Looking For 

• PhD in Computer Science, Engineering, Applied Mathematics, Physics, or a related quantitative field preferred. Exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply. 
• Deep experience in at least one of the following: computer architecture and accelerator design; parallel, distributed, or high-performance computing; numerical methods and scientific simulation; AI/ML theory and model design at a mathematical level. 
• Strong ability to analytically model and optimize the performance of complex systems and algorithms. 
• Track record of published research or patents in relevant venues. 
• Proficiency in C and Python; comfort working close to hardware. 
• Excellent communication and interpersonal skills: able to present complex technical material to both specialist and cross-functional audiences, and to collaborate effectively in a fast-paced, small-team environment. 

Areas Of Particular Interest 

We are hiring across several focus areas. Exceptional depth in one or more of the following is a strong signal: 

• Computational science: researchers who can bring insights from numerical methods and simulation into AI, or couple simulation and learning into joint computational workflows. Depth in hydrodynamics, solid mechanics, electromagnetics, molecular dynamics, or related PDE-based fields. 
• AI/ML foundations: deep understanding of model architecture, optimization methods, and their statistical underpinnings—the ability to design from first principles, not just apply established recipes. 
• Computer architecture: microarchitecture design, computing paradigms at the circuit and datapath level, memory hierarchy design. 
• Performance engineering: roofline modeling, bandwidth analysis, kernel optimization, communication-computation overlap, and compiler-level tuning for novel hardware. 

Why This Opportunity Is Exciting And Unique 

• Build on a fundamentally different architecture, unconstrained by GPU assumptions. 
• Publish and open-source your research. We present at Supercomputing, SIAM, IEEE, NeurIPS, and beyond. 
• Work on the fastest AI system in the world, with direct access to the hardware your compiler targets. 
• Join at a pivotal moment: Cerebras is pre-IPO with strong commercial traction and rapid growth. 
• Be part of a small, technical team with high autonomy, minimal bureaucracy, and a culture that values depth over hierarchy. 

We are hiring for multiple positions across experience levels. If this work resonates, we encourage you to apply. 

• Provide hands-on technical leadership, owning the technical vision and roadmap for the kernel-centric reliability of our internal and customer-facing systems
• Assist System and Cluster Operations teams on reducing system and service downtime after failure by providing tooling and manual intervention for failure analysis and diagnostic
• Work with the Debug Team to enhance debug tools with the goal of speeding up failure analysis
• Collaborate with SW teams to improve the software stack, including Kernels, to improve on-field debugging and failure analysis
• Work with the ASIC an HW architecture teams to codesign the next generation architectures with reliability and ease of debug in mind
• Lead, mentor, and grow a high-caliber team of engineers, fostering a culture of technical excellence and rapid execution. 

• 6+ years in software engineering, with 3+ years leading teams in SW/HW reliability, debug, diagnostic, failure analysis or related fields 
• Expertise in parallel and distributed programming (message passing, multicore, GPU, embeded, etc.), debug and diagnostic tool development or expert usage (debuggers, core dump handling, code sanitizers, etc.), experience debugging distributed and parallel applications (deadlocks, livelocks, race conditions, etc.), deep understanding of computer architectures (instruction pipelining, multithreading, networking, etc.)
• Operations & Monitoring: Strong background in monitoring and reliability engineering (incident response, post-mortem analysis, etc.)
• Leadership & Collaboration: Demonstrated ability to recruit and retain high-performing teams, mentor engineers, and partner cross-functionally to deliver customer-facing products.

The Role 

We are seeking a highly skilled and motivated Manufacturing Bring-up Engineer to join our team. As the Manufacturing Bring-up Engineer you will support our system level bring-up process execution, implementation, and evolution in the manufacturing pipeline. This is a high visibility role that requires strong technical expertise, coordination, and collaboration to deliver our product from manufacturing to the customer. 

Responsibilities 

• Support the Cerebras manufacturing bring-up process execution to configure, test, and validate system performance prior to customer shipment 

• Collaborate cross-functionally with Asic, SW, Diagnostics, and QA teams to further automate and streamline the workflow for optimal manufacturing efficiency 

• Troubleshoot and resolve technical issues during system bring-up across Asic, SW, and QA domains 

• Design and implement efficient processes to manage and track system bring-up status and progress 

• Track and report on critical bring-up metrics to drive continuous improvement  

• Implement further SW automation and efficiencies to effectively scale the manufacturing bring-up process in support of the manufacturing roadmap 

Skills & Qualifications 

• BS or MS in EE, ECE, CS or equivalent work experience 

• 3+ years of industry experience in an operations environment 

• Experience in hardware bring-up and the debug of complex systems 

• Working knowledge and experience in Asic bringup and test processes 

• Working knowledge of scripting in languages such as Python and/or Perl 

• Proven experience in system bring-up and validation of complex computer systems or equivalent technologies 

• Understanding of computer system architecture and hardware components  

• Proficiency in scripting and automation tools for system bringup  

• Excellent problem-solving and communication skills with the ability to work collaboratively in a fast-paced environment 

• Very strong coordination and collaboration skills to manage a business-critical workflow directly in support of customer demand 

Preferred: 

• Familiarity in creating test and s/w infrastructure at large scale 

• Working across global time zones  

Location 

Bangalore, India/Toronto, Canada/ Sunnyvale, California.

The base salary range for this position is $170,000 to $230,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Senior ASIC (Front End) Design Engineer

Summary:

• As a Senior ASIC (Front End) Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
• Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
• Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
• You will be a trusted self-starter who can work with very little guidance or oversight.
• This position is located in: Toronto, Canada - Hybrid

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC RTL design and/or architecture experience
• Proven track record with the development of complex SoCs
• Strong understanding of digital design fundamentals and methodologies
• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:

Experience in any of the following areas:

• Networking (Ethernet MAC, PHY/PCS, Switching, TCP/IP, PCIe and other industry standard protocols)
• Digital signal processing filters
• Digital Mixed-Signal modeling, design, and integration
• IP integration (SerDes, controllers, processors, etc.)
• Video standards, protocols, processing
• Perl, TCL, C/C++, Make

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

#LI-Hybrid

We are hiring a Digital Design Engineer to help develop an ASIC for the next-generation artificial intelligence computing architecture alongside a team of world-class scientists and engineers. If your passion is innovation, solving challenging technical problems, and doing impactful work, you should join our team and help build the world's first optical computers!

In this job, you will work in close collaboration with computer architects, software engineers, verification engineers, and physical design engineers to design innovative compute accelerators that work with photonic technology to power the growing AI/ML workloads that customers want while keeping power low. This will be a great opportunity to define the next advance in computer architecture!

Responsibilities

• Develop microarchitecture design and RTL for advanced ML/AI accelerator ASICs/SoCs including advanced memory system and high-performance NoC.
• Understand and integrate silicon photonic communication and compute technology into digital accelerator design.
• Actively work with Architecture, Design Verification, Implementation, Photonic, Analog and Software teams to realize high performance, low power designs in advanced technology nodes.
• Create design specifications and documentation to facilitate collaboration with partner teams.
• Manage RTL implementation to achieve functionally correct, performant designs within project schedules by identifying, communicating and mitigating risks.

Qualifications

• 8 years of related experience with a Bachelor’s degree; or 6 years and a Master’s degree in Electrical or Computer Engineering (or related fields)
• Expertise with high-speed digital design techniques
• Expertise with power-efficient digital design techniques
• Experience in ASIC design with multiple successful tape outs

Preferred Qualifications

• Experience in communication protocols (e.g. PCIe)
• Experience interfacing with memory systems (e.g. HBM/DDR5)
• Knowledge of processor design, accelerators, and/or memory hierarchies
• Knowledge of machine learning algorithms

We are hiring a Digital Design Engineer to help develop an ASIC for the next-generation artificial intelligence computing architecture alongside a team of world-class scientists and engineers. If your passion is innovation, solving challenging technical problems, and doing impactful work, you should join our team and help build the world's first optical computers!

In this job, you will work in close collaboration with computer architects, software engineers, verification engineers, and physical design engineers to design innovative compute accelerators that work with photonic technology to power the growing AI/ML workloads that customers want while keeping power low. This will be a great opportunity to define the next advance in computer architecture!

Responsibilities

• Develop microarchitecture design and RTL for advanced ML/AI accelerator ASICs/SoCs including advanced memory system and high-performance NoC.
• Understand and integrate silicon photonic communication and compute technology into digital accelerator design.
• Actively work with Architecture, Design Verification, Implementation, Photonic, Analog and Software teams to realize high performance, low power designs in advanced technology nodes.
• Create design specifications and documentation to facilitate collaboration with partner teams.
• Manage RTL implementation to achieve functionally correct, performant designs within project schedules by identifying, communicating and mitigating risks.

Qualifications

• 8 years of related experience with a Bachelor’s degree; or 6 years and a Master’s degree in Electrical or Computer Engineering (or related fields)
• Experience in ASIC design with multiple successful tape outs
• Expertise with high-speed digital design techniques
• Expertise with power-efficient digital design techniques

Preferred Qualifications

• Experience in communication protocols (e.g. PCIe)
• Experience interfacing with memory systems (e.g. HBM/DDR5)
• Knowledge of processor design, accelerators, and/or memory hierarchies
• Knowledge of machine learning algorithms

We are hiring a Digital Design Engineer to help develop an ASIC for the next-generation artificial intelligence computing architecture alongside a team of world-class scientists and engineers. If your passion is innovation, solving challenging technical problems, and doing impactful work, you should join our team and help build the world's first optical computers!

In this job, you will work in close collaboration with computer architects, software engineers, verification engineers, and physical design engineers to design innovative compute accelerators that work with photonic technology to power the growing AI/ML workloads that customers want while keeping power low. This will be a great opportunity to define the next advance in computer architecture!

Responsibilities

• Develop microarchitecture design and RTL for advanced ML/AI accelerator ASICs/SoCs including advanced memory system and high-performance NoC.
• Understand and integrate silicon photonic communication and compute technology into digital accelerator design.
• Actively work with Architecture, Design Verification, Implementation, Photonic, Analog and Software teams to realize high performance, low power designs in advanced technology nodes.
• Create design specifications and documentation to facilitate collaboration with partner teams.
• Manage RTL implementation to achieve functionally correct, performant designs within project schedules by identifying, communicating and mitigating risks.

Qualifications

• 8 years of related experience with a Bachelor’s degree; or 6 years and a Master’s degree in Electrical or Computer Engineering (or related fields)
• Expertise with high-speed digital design techniques
• Expertise with power-efficient digital design techniques
• Experience in ASIC design with multiple successful tape outs

Preferred Qualifications

• Experience in communication protocols (e.g. PCIe)
• Experience interfacing with memory systems (e.g. HBM/DDR5)
• Knowledge of processor design, accelerators, and/or memory hierarchies
• Knowledge of machine learning algorithms