What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Layout to lead the development of next-generation SRAM solutions.

• Lead the development and execution of full-custom SRAM memory layout and sign-off verification flows (including compiler automation where applicable).
• Collaborate closely with circuit designers to translate schematics into efficient, high-performance physical layouts, own floor planning, placement, routing, and tape-out.
• Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power, yield, and manufacturability.
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification.
• Debug and resolve layout issues efficiently, including process-specific challenges in advanced nodes.
• Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques, design-rule compliance, and knowledge sharing.
• Develop automation scripts (Perl, Tcl, SKILL, etc.) to improve productivity.
• Address reliability concerns such as EM/IR drop, soft errors, and process variability. 
• Work cross-functionally with circuit, architecture, verification, and foundry/process teams to ensure first-pass silicon success and support product integration

What You Bring

• Bachelor's degree with 10+ years of experience in custom SRAM, memory compiler and IC physical layout design or master's degree 8+ years of experience strongly preferred. 
• 3 year’s experience in leadership of management role preferred.
• Extensive experience in SRAM layout design in advanced process nodes (e.g., 3nm, 2nm, or below).
• Demonstrated ability to lead, mentor, and manage a team of layout engineers. 
• Strong project management skills to handle complex schedules and cross-functional collaboration. 
• Strong proficiency with industry-standard EDA tools: 
• Candence Virtuoso (or Custom Compiler/IC Compiler) for custom/analog layout. 
• Physical verification tools for DRC/LVS/ERC flows. 
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification. 
• Experience with RC extraction, parasitic reduction, and memory-specific verification. 
• Scripting/automation skills (Perl, Tcl, SKILL, etc.) are highly valued. 
• Proven ability to drive layout quality, constraints, and closure while collaborating in global, cross -functional teams. 
• Prior work on high-speed, low-power SRAM in leading-edge nodes preferred. 
• Mentoring or technical leadership experience preferred. 
• Understanding of SRAM architecture, timing, power analysis, and yield optimization preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are looking for a dynamic, self-motivated, experienced engineer to architect and lead functional test coverage and test methodologies for NVMe SSDs.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Manage Enterprise server infrastructure, execute Customer Qual tests and debug failures
• Execution of enterprise SSD qualifications in customer systems.
• Communicate with team lead to understand qualification processes and test plans. Report status of qualifications and manage customer expectations.
• Coordinate  with internal team and customer test engineers to execute qual plans as per schedule. Teams will be both local and remote.
• Triage test failures and do a first level FA. Design and execute experiments to root cause defects and verify fixes in coordination with development teams.
• Provide feedback to functional test teams on issues seen in customer quals to better functional test coverage.
• Contribute in Triaging customer field issues and provide support for timely resolution of customer issues.
• Identify automation opportunities and help Automation team to continue to improve and add to the existing framework.

What You Bring

• BS in Computer Science or related technical field with 10+ years of system level testing or development of enterprise servers and enterprise storage systems experience or MS with 8+ years preferred.
• Experience with at least storage protocol like NVMe/PCIe, SAS, SATA, Fibre Channel
• Familiar with one of protocol analyzers like LeCroy, SerialTek, or Xgig System or device level performance analysis
• Proficiency in server operating systems especially system debug tools such as system logs.
• Knowledge of enterprise storage/server system technologies.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, Test execution and bug management tools.
• Scripting experience such as in Perl, Shell or Python
• Experience with SSD or HDD testing
• NetApp/HPE/Dell/IBM System Experience
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Design and development of high performance firmware and software for cutting-edge enterprise SSD products.
• Debug, optimize, and validate SSD firmware on complex embedded multi-core architectures.
• Support customer qualification and adoption of SSD products.
• Participate in ground-breaking advanced SSD storage development and research projects.

What You Bring

• BS in Computer/Electrical Engineering or Computer Science with 3+ years of working experiences in silicon development or MS in Computer/Electrical Engineering or Computer Science with 1+ years of relevant working experience or PhD and 0+ years of relevant experience in storage firmware development is required.
• Strong programming experience and demonstrated proficiency in C/C++ for embedded systems, including development of algorithms, manipulation of complex data structures, and implementing highly optimized code, is required.
• Relevant hands on experience in embedded software or firmware development, including storage devices or other embedded platforms is required.
• Experience with one or more of the following storage related technologies: NVM Express, PCI Express, SAS, SCSI, NAND Flash/FTL, Fibre Channel, SATA, eMMC, or UFS is beneficial.
• Experience with ARM or equivalent embedded multi-core microprocessor architectures is required.
• Hands on experience with JTAG/ICE debuggers and protocol analyzers is required.
• Some scripting experience in one of Python/Perl/Javascript is desired.
• Familiarity and experience with modern agile software development methodologies and practices is preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

Memory IO Lab is part of Samsung’s Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume. Memory IO’s vision is to provide memory interface technology solutions which can be adopted in DDR, LPDDR, GDDR, and more. We are an integral part of Samsung’s paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps.

Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy

What You'll Do

• Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES.
• Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary.
• Ownership of circuit and system specifications.
• Simulate designs with state-of-the-art CAD tools.
• Document designs and simulation results.

What You Bring

• BS 10+ years experience, MS 8+years of experience, PhD 5+ years experience in Electrical Engineering, Computer Science preferred. 
• 5+ years of experience working with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes.
• Prior experience in design of any one of the standard high speed interfaces like DDR, LPDDR, , GDDR, HBM I/O interface.
• Needs to be an expert in providing and understanding layout requirements of high speed circuits.
• Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design.
• Experience working closely with device/process team to define transistor specs
• The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
• Ability to troubleshoot and analyze complex problems.
• Excellent communication (written and verbal) and interpersonal skills
• Experience in high frequency clock distribution design, implementation, and analysis.
• Deep understanding of PPA (performance, power, and area) trade-offs.
• Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools
• Experience on silicon bring-up and automatic measurement using script
• Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design  to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms.

This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design.

• Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm).
• Optimize SRAM designs for performance, power and area (PPA) and yield.
• Develop custom layouts and perform physical design verifications (e.g., DRC, LVS).
• Evaluate trade-offs between speed, power, and area to meet design targets.
• Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification.
• Work with product and test engineers to develop test plans and support silicon bring-up.
• Mentor Junior engineers, providing guidance on SRAM design techniques and best practices.
• Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance.
• Contribute to patents, technical papers, or industry conferences to advance SRAM technology.

What You Bring

• Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. 
•  Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes.
• Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.).
• Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths.
• Familiarity with timing analysis, power analysis, and design for manufacturability (DFM).
• Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc.
• Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks.
• Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams.
• Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond).
• Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling).
• Background in silicon debug and root-cause analysis.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change. 

#LI-SF1

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we're revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution.

In this highly strategic role, you'll serve as Astera Labs' technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You'll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers exceptional scope for impact—your work will directly enable the rack-scale AI infrastructure that's transforming cloud computing and enterprise data centers worldwide.

Key Responsibilities

• Strategic Leadership & Methodology Development
• Define and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols
• Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality
• Represent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verification
• Drive cross-functional collaboration to influence technical direction across the organization
• Technical Execution & Innovation
• Develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications
• Identify key logic components and critical micro-architectural properties essential for ensuring design correctness
• Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs
• Apply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth
• Develop and maintain scripts to enhance FV productivity and streamline verification processes
• Team Development & Cross-Functional Partnership
• Mentor Principal and Lead Engineers across global sites in advanced formal verification techniques
• Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels
• Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback
• Prepare and deliver customer meetings and executive presentations with minimal supervision

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
• 15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization
• Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification
• Advanced scripting abilities with Python or Perl for automation and productivity enhancement
• Proven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision
• Strong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus
• Entrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards

Preferred Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification
• Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold
• Experience with both bug hunting and static proof verification techniques
• Familiarity with automating formal verification workflows within a CI/CD environment
• Deep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink
• Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)
• Patents or publications in formal verification or hardware verification methodologies
• Track record of recruiting, mentoring, and developing formal verification talent across distributed teams

Salary range is $230,000 to $285,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.

Key Responsibilities

• As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
• Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
• Architect and recommend flow improvements and enhance existing methodology for high performance design.
• Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
• Work with cross function teams to define requirements and specifications to achieve best PPA
• Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity
• Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• 2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Knowledge of agentic AI solutions is a plus.
• Experience working with EDA/IP vendors for both RTL and hard-macro integration.
• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.

We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation.  The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues.  The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.

Basic qualifications:

• Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.
• Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required experience:

• Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols.
• High level of proficiency in System Verilog and verification environments.
• Experience understanding software and hardware co-simulation limitations and debug methods.
• Experience in programming and scripting languages (like perl/python/C).
• Currently based locally or open to relocation.

Preferred experience:

• Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.
• Experience in modeling for emulation and prototyping, and/or non-UVM environments

As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.

Key Responsibilities

• Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
• Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
• Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
• Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

Basic Qualifications

• Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
• ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

• Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
• Experience working with IP vendors for both RTL and hard-macro integration.
• SystemVerilog/Verilog familiarity.

The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description

We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
  required, and a Maser’s is preferred.
• ≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in US and start immediately.

Required Experience

• Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
  environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
  generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
  writing assertions, cover properties and analyzing coverage data
• Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.
• Must have prior experience on verification with firmware to control and configure the SerDes and related components.

Preferred Experience

• SW debugging for Mix-Signal based designs.
• Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.
• Experience with FPGA-based verification/emulation.

As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
• ≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. 
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in tcl, python or Perl.

Preferred Experience:

• Knowledge of design for test (DFT)
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.

Senior ASIC Front-End Design Engineer

Summary:

• As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
• Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
• Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
• You will be a trusted self-starter who can work with very little guidance or oversight.
• This position is located in: San Jose, CA (Hybrid)

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC RTL design and/or architecture experience
• Proven track record with the development of complex SoCs
• Strong understanding of digital design fundamentals and methodologies
• In-depth knowledge of Verilog/System Verilog and simulation tools.
• Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:

Experience in any of the following areas:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• IP integration (SerDes, controllers, processors, etc.)
• Perl, TCL, C/C++, Make

Personal Skills:

• Excellent communication/documentation skills.
• Attention to details.
• Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

#LI-Hybrid

We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedul.e The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency.

This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities 

• Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones
• Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria
• Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors
• Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases
• Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning
• Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs
• Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions
• Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams
• Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases
• Own the bug lifecycle — triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects
• Manage the regression framework — defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines
• Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments
• Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams
• Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews
• Represent verification readiness in tapeout sign-off reviews and program-level decisions

• Support running gate-level simulations as part of design signoff.
• Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.

Required Qualifications & Experience 

• Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.
• UVM Mastery: Deep expertise in UVM-based testbench architecture and constrained-random verification methodology — not just usage, but architectural decision-making and optimization.
• SystemVerilog: Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages.
• Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
• Debug Skills: Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels.
• SoC Architecture: Strong understanding of modern SoC building blocks — processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
• Scripting & Automation: Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development.
• Communication: Clear and effective communication of verification status, risk, and trade-offs to technical peers and program leadership.

We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

As a Sr. Staff/ Principal Digital Design Engineer, you will be working with a team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. In addition to delivering high quality digital solutions in the context of the product architecture, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing, etc.

Key Responsibilities

• Contribute to/review SoC specifications and architectures
• Front to back digital design and verification – RTL through physical implementation
• Hands on technical leadership
• Support schedule and resource planning
• Help define and socialize digital/system design, implementation methodologies and test strategies and flows
• Debug designs and provide timely closure
• Work with System, Software, RF, Analog, and Test teams and provide necessary support

Job Requirements

• MS/PhD EE/CS preferred
• 10 or more years of experience digital SoC development required
• Experience bringing highly integrated mixed signal SoCs to commercial mass production
• Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces
• Deep RTL design knowledge (Verilog/VHDL) and SystemVerilog, checkers, and other design verification techniques
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Proven knowledge of synthesis, static timing, DFT and (Front to Back) F2B digital SoC design flow
• Experience with ATPG, fault grading, scan, BIST, DFT/DFM
• Proven knowledge of SystemVerilog assertions,
• Knowledge of languages such as C/C++, Perl, Tcl and Python
• Strong communication and presentation skills
• Good skills and interest in mentorship
• Ability to foresee issues and design in flexibility and workarounds for both known and unknown unknowns
• Expert in RTL design and implementation (architecture and micro-architecture)
• Deep knowledge of front-end tools and flow - Verilog simulators, linters, synthesis, static timing, clock trees, power simulation, floor plan development, and power supply implementation
• Deep knowledge of system modeling and verification using System Verilog or System C
• Proven knowledge in acquiring and integrating 3rd party IP
• High speed logic design (GHz+) , and high speed clock distribution experience.
• Understanding of mixed signal concepts

 Desirable Skills

• Experience with Cadence F2B design tools
• Experience with formal verification tools
• Able to work effectively with incomplete or changing requirements
• Good mentorship skills
• Strong knowledge of mixed signal concepts
• Focused, goal driven finisher