The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role

As a Staff Security Firmware Test Developer, you’ll be the technical owner of security validation for enterprise SSD firmware — designing, building, and executing test strategies that ensure our drives meet the highest standards for data protection, compliance, and interoperability.

You’ll work at the intersection of firmware, hardware, and security protocols — validating features like Secure Boot, TCG OPAL, SPDM Firmware Attestation, Caliptra 2.1, and OCP NVMe Security Requirements across FPGA and ASIC platforms.

You’ll lead test automation, debug complex failures, and drive quality from design to production — ensuring our firmware is not just functional, but secure by design.

Responsibilities

• Lead end-to-end security validation for enterprise NVMe SSD firmware — from architecture review to production sign-off — ensuring compliance with Secure Boot, TCG OPAL, SPDM Firmware Attestation, Caliptra 2.1, and OCP NVMe Security Requirements.
• Design, build, and maintain automated test frameworks that validate security features across FPGA and ASIC platforms, enabling rapid regression and continuous integration.
• Debug and root-cause complex security failures — working closely with firmware, hardware, and security architects to resolve issues at the protocol or implementation level.
• Define and execute test strategies that prove “secure by design” — not just functional correctness, but cryptographic integrity, attestation, and tamper resistance.
• Own test coverage and quality gates for security-critical features — ensuring no release ships without passing validation against defined security specs.
• Stay ahead of evolving standards — actively track and implement upcoming TCG Storage Spec Requirements and other industry security mandates.
• Collaborate cross-functionally with firmware, hardware, and security teams — translating specs into testable requirements and driving alignment on security validation outcomes.

Minimum Qualifications

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field — or equivalent practical experience in firmware or embedded security.
• 5+ years of hands-on experience validating security features in firmware or embedded systems — specifically in NVMe SSDs, storage controllers, or similar hardware platforms.
• Proven experience validating at least 3 of the following:
• Secure Boot (UEFI/TPM/Bootloader)
• TCG OPAL (Self-Encrypting Drive)
• SPDM (Firmware Attestation)
• Caliptra 2.1 (or equivalent hardware root of trust)
• OCP NVMe Security Requirements
• TCG Storage Spec Requirements (upcoming or current)
• Strong experience building and maintaining automated test frameworks for firmware or hardware validation — with scripting (Python,Java, Bash, C) and CI/CD integration.
• Experience debugging low-level firmware/hardware issues — using tools like JTAG, logic analyzers, or firmware logs — with ability to trace failures across protocol layers.
• Working knowledge of NVMe protocol, PCIe, and storage security standards — with ability to read and implement test cases from specs.
• Experience working with FPGA or ASIC platforms — validating firmware behavior in pre-silicon or post-silicon environments.
• Strong ownership mindset — able to define test strategy, drive quality gates, and ensure security validation is not an afterthought, but built into the design.

Preferred Qualifications

• Experience with formal security certification processes (e.g., FIPS 140-3, Common Criteria, ISO 27001, or similar).
• Hands-on experience with Caliptra 2.1 or similar RISC-V-based hardware root of trust architectures.
• Experience with SPDM or similar attestation protocols in production firmware.
• Contributions to open-source security test frameworks or industry standards (e.g., TCG, OCP, NVM Express).
• Experience with security validation in cloud-scale storage environments (e.g., hyperscale data centers, enterprise storage arrays).
• Strong communication skills — able to present technical findings to engineering leadership and security compliance teams.

COMPENSATION: $110,000-$160,000

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness

We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation.  The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues.  The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.

Basic qualifications:

• Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.
• Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required experience:

• Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols.
• High level of proficiency in System Verilog and verification environments.
• Experience understanding software and hardware co-simulation limitations and debug methods.
• Experience in programming and scripting languages (like perl/python/C).
• Currently based locally or open to relocation.

Preferred experience:

• Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.
• Experience in modeling for emulation and prototyping, and/or non-UVM environments

Job Description

We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
  required, and a Maser’s is preferred.
• ≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in US and start immediately.

Required Experience

• Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
  environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
  generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
  writing assertions, cover properties and analyzing coverage data
• Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.
• Must have prior experience on verification with firmware to control and configure the SerDes and related components.

Preferred Experience

• SW debugging for Mix-Signal based designs.
• Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.
• Experience with FPGA-based verification/emulation.

As a Senior Software Diagnostics Engineer on the Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture of cutting-edge high-speed datacenter products.  You will be working on a project from conception to the final production stage at contract manufacturer.

The role requires a strong and broad software background and a good understanding of hardware design and manufacturing practices.  At the same time, we welcome candidates with deep experience in smaller areas and desire to learn.  Depending on your experience, you may be focusing on design/validation or automation/manufacturing.

Key Responsibilities:

• Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.
• Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product
• Bring-up newly manufactured boards and port the first level of software.
• Isolate and perform root-cause analysis of reported failures
• Support new platform software and hardware features
• Coordinate with the hardware engineering team on bring-up schedules and feature delivery
• Participate proactively in design discussions, design review and project management

Basic Qualifications

• Bachelors in Computer Science/Computer Engineering or equivalent experience.
• Knowledge of modern software development
• Proficiency in Python, C or similar
• Ability to work cross-functionally in a fast-paced, highly technical environment.

Required Experience

• 2+ years of Experience in subset of diagnostics, hardware bring-up, test or manufacturing automation
• Strong debugging skills across hardware, firmware, and system layers

Preferred Experience/Nice to Have

• Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing
• Ability to read schematic/layout
• System debug experience
• Embedded programming and good knowledge of OS internals (Linux/Unix)
• Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.
• Experience with DDR5

The base salary range is $120,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job Description:

As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products.  You will be working on projects from conception to the final production stage at contract manufacturer.

The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices.  At the same time we welcome candidates with deep experience in smaller areas with the desire to learn.  Depending on your experience, you may be focusing on design/validation or automation/manufacturing.

Key Responsibilities

• Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.
• Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product
• Bring-up newly manufactured boards and develop the first level of software.
• Isolate and perform root-cause analysis of reported failures
• Support new platform software and hardware features
• Coordinate with the hardware engineering team on bring-up schedules and feature delivery
• Participate proactively in design discussions, design review, and project management
• Work independently as well as in team roles, mentor younger team members

Basic Qualifications/Required Experience

• Bachelor’s in CS/CE or equivalent experience.
• 8+ years of Experience in subset of diagnostic, hardware bring-up, test or manufacturing automation
• Knowledge of modern software development 
• Proficiency in Python, C/C++

Preferred experience

• Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing
• Ability to read schematic/layout
• System debug experience
• Embedded programming and good knowledge of OS internals (Linux/Unix)
• Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.
• Experience with DDR5

The base salary range is $203,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

The Role and Its Impact 

Our Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications, providing critical signal conditioning for high-speed connectivity in AI infrastructure. The firmware you develop will manage complex system and IP integration, SERDES configuration, link training sequences, and diagnostic capabilities for these devices deployed in data centers worldwide. 

As a Principal Engineer in our Signal Connectivity Engineering group, you'll contribute to firmware that directly impacts the performance and reliability of Ethernet connectivity solutions powering AI infrastructure globally. Working closely with the SoC software, transceiver module software, and system validation teams, you'll take ownership of feature development and rollout, software integration testing, and customer debug activities. Working at the intersection of embedded systems and high-speed Ethernet connectivity, you'll collaborate closely to bring these systems to production. 

We're a startup, and this role reflects that reality. You'll have responsibilities spanning firmware development, customer engagement, debug and validation support, and cross-functional coordination. We're looking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. 

This position offers strong mentorship opportunities as you work alongside experienced engineers and help bring products from development through customer deployment. 

Level is negotiable based on experience and qualifications. 

Location 

This is an on-site position based in our San Jose, CA office. 

Core Responsibilities 

Firmware Development & Debug 

• Develop and maintain embedded firmware for Ethernet retimers and gearboxes, from low-level hardware abstraction through customer-facing APIs 
• Drive Layer 1 PHY and SERDES debug activities, including link bring-up issues, signal integrity problems, and interoperability failures 
• Support complex IP integration efforts across multiple subsystems within the SoC 
• Implement and optimize link training sequences, equalization tuning, and diagnostic features 
• Assist with software quality gates and validation criteria at each development phase 

Product Rollout & Customer Integration 

• Partner with the software lead to drive product rollout activities from development through production deployment 
• Support customer integration efforts through firmware customization, debug assistance, and technical guidance 
• Investigate field-reported issues and coordinate resolution with internal teams 
• Develop and maintain SDK/API interfaces that enable customer platform integration 

Cross-Functional Collaboration 

• Work extensively with digital SoC teams to understand hardware behavior, register interfaces, and IP integration requirements 
• Collaborate with field applications engineers to support customer bring-up and resolve deployment issues 
• Partner with platform applications teams to ensure firmware meets system-level requirements 
• Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases 
• Provide regular project updates on progress, risks, dependencies, and technical challenges 

What You Bring 

Required Qualifications: 

• BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field 
• 10+ years of embedded C/C++ firmware development in resource-constrained environments 
• Deep understanding of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware design 
• Experience with Layer 1 PHY firmware, SERDES bring-up, or SDK/API development for networking devices 
• Strong proficiency with Linux development tools: gcc/clang, make, bash scripting, gdb, and git 
• Excellent verbal and written communication skills; ability to explain complex technical concepts clearly 
• Demonstrated problem-solving ability and systematic debugging approach on real hardware 
• Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment 

Highly Valued Skills: 

• Experience with PMA, FEC, or related PHY-layer subsystems beyond the PMD/SERDES 
• Familiarity with NIC or switch management software, for system test purposes 
• Exposure to SAI (Switch Abstraction Interface) or OpenBMC 
• Experience with Python for test automation, data analysis, or general scripting 
• Hands-on experience building and maintaining Jenkins CI/CD pipelines and automated test infrastructure 
• Background in retimer or gearbox firmware/API, active electrical cables, or high-speed Ethernet connectivity 
• Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, BERT, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar 
• Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin 
• Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments 
• Experience with RTOS, device drivers, or coroutines 
• Prior technical lead, mentorship, or team lead experience 

Compensation 

Salary range is $185,000 USD - $203,000 USD depending on experience, level, and business need. This role will include a discretionary bonus, competitive equity package, comprehensive health/dental/vision coverage, professional development opportunities, and a culture that values technical excellence, collaboration, and innovation.

Figure is an AI robotics company developing autonomous general-purpose humanoid robots. The goal of the company is to ship humanoid robots with human level intelligence. Its robots are engineered to perform a variety of tasks in the home and commercial markets. Figure is headquartered in San Jose, CA.

We are looking for an Electrical Engineering Intern to support the design and test of critical hardware components during Fall 2026. 

Responsibilities:

• Design and test full or sub sections of PCBAs on the Humanoid like power distribution boards, battery management systems, sensing boards, motor controllers, or computer boards.
• Support the review of design artifacts (schematics, layouts, bill of materials…) from your peers or external suppliers.
• Support system integration and test activities by contributing to test execution and problem diagnostics and resolution.

Requirements: 

• Undergraduate student (Senior) or recent graduate in Electrical Engineering or related field.
• Minimum 10 weeks internship, 1 to 2 terms preferred.
• Solid EE fundamentals with hands-on experience designing, building, and testing PCBAs.
• Experience with design automation (EDA) tools, preferably Altium in both schematics and layout.
• Experience with power electronics (motor driver, switch mode power supplies…), digital electronics (MCU, FPGA, Ethernet, USB, SPI, I2C…), and analog electronics (filters, ADC/DAC…)
• Strong verbal and written communication skills.

Bonus Qualifications: 

• Experience using LTspice, Python, and Matlab.
• Embedded programming of DSPs, microcontrollers, and FPGAs.
• Basic understanding of mechanical design fundamentals

The US base salary range for this full-time position is between $40 - $45/hr. 

The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended.

Efficient is looking for a seasoned Design Verification & Emulation Manager to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers.

This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond! 

Key Responsibilities 

• Define end-to-end verification strategy from block-level through full-chip simulation to emulation and prototyping
• Own UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoption
• Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling
• Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising
• Deliver pre-silicon platforms for early software development in partnership with firmware and software teams
• Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments
• Own functional coverage models and sign-off criteria, driving closure across simulation and emulation combined
• Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution
• Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership
• Build, mentor, and scale a high-performing team of verification and emulation engineers
• Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness
• Represent verification and emulation in tapeout readiness reviews and program-level decision forums
• Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams
• Manage emulation lab infrastructure, including hardware resources, licensing, and vendor relationships
• Evaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques.
• Define right DV  mix for in-house  vs outsourcing to 3rd party vendors. Coordinate 3rd party vendor resources towards achieving project goals.

Required Qualifications & Experience 

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
• Experience: 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
• Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.
• Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
• Languages & Tools: Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
• SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
• Leadership: Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.
• Execution: Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).

Preferred Qualification

• Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.
• Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.
• Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).

We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

About the role

Muon seeks a Staff Software Engineer to join our flight software team. The ideal candidate is an expert software developer with significant previous experience architecting and building robust bare-metal / RTOS embedded devices or appliances. In this role, you will both set architectural direction for, and lead design, development, integration, and testing of much of the software and firmware that runs on our orbiting satellites. This position is based at our San Jose, CA office.

Responsibilities

• Leading member of the team defining and building Muon’s satellite bus platform
• Define and architect design and execution against the basic concepts and requirements of our missions to get the right software and firmware on orbit
• Design, bring up, and support the embedded software environment that runs in our satellite flight systems and peripherals using ARM Cortex-M CPUs.
• Guide evaluation and selection of technologies for our software foundation
• Write application, platform, and driver functionality in our flight software environment and set the standards for how others use it
• Build the architectural patterns, shared libraries, services and technical strategy documents that enable high-quality and high-velocity development of flight software
• Integrate compute and peripheral subsystems in both software and hardware
• Collaborate with hardware team members on the design and bring up of Muon hardware
• Align team roadmaps with product requirements and mission needs
• Define metrics aligned with critical company goals and enable the team to achieve aggressive goals
• Ensure effective software and hardware-in-the-loop test strategies
• Mentor senior engineers

Qualifications 

• B.S., M.S., or Ph.D. in computer science, electrical engineering, or related field
• 10+ years experience as a software engineer in a team environment
• Strong C/C++ programming, with practical familiarity of other languages
• Great embedded systems fundamentals: distributed system architecture, resource-efficient design, low-level drivers, bit manipulation, responsive software and IRQ handling, RTOS frameworks, I/O and communication buses.
• Integration and control of external hardware devices
• Read and understand hardware data sheets
• Excellent communication and presentation skills

Nice-to-have Skills

• Experience working in flight software or some closely related domain
• Rust and Python experience
• Knowledge of industry-standard data formats and schemas (ProtoBuf, YAML, JSON, etc)
• Familiarity with a Linux-based development environment
• Experience with one or more of: embedded linux, FPGA, HW design, RF communication systems, cloud/server infrastructure, network architecture.
• End-to-end development from product concept to delivery to customer/market.

Salary

The salary range for this role is $210,000 - $234,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process. 

About the role

Muon seeks a Flight Software Engineer to join our satellite flight software team. The ideal candidate is a self-motivated versatile software developer with significant previous experience developing robust bare-metal / RTOS embedded devices or appliances. In this role, you will design, develop, integrate, and test the software and firmware that runs on our orbiting satellites. This position is based at our San Jose, CA office.

Responsibilities

• Integral member of the team defining and building Muon’s satellite bus platform
• Translate concepts and requirements into design and working implementations, supporting through to on-orbit operations
• Design, bring up, and support the embedded software environment that runs in our satellite flight systems and peripherals using ARM Cortex-M CPUs.
• Participate in evaluating and selecting technologies for our software foundation
• Write application, platform, and driver functionality in our flight software environment and teach others how to use it
• Integrate compute and peripheral subsystems in both software and hardware
• Collaborate with hardware team members on the design and bring up of Muon hardware
• Collaborate with software team members to set flight software architecture, select infrastructure and tools, and communicate with cloud backends.
• Participate in developing software and hardware-in-the-loop test strategies

Qualifications 

• B.S., M.S., or Ph.D. in computer science, electrical engineering, or related field
• 5+ years experience as a software engineer in a team environment
• Strong C/C++ programming, with some practical familiarity of other languages
• Great embedded systems fundamentals: resource-efficient design, low-level drivers, bit manipulation, responsive software and IRQ handling, RTOS frameworks, I/O and communication buses.
• Integration and control of external hardware devices
• Read and understand hardware data sheets
• Excellent communication and presentation skills

Nice-to-have Skills

• Knowledge of industry-standard data formats and schemas (ProtoBuf, YAML, JSON, etc)
• Familiarity with a Linux-based development environment
• Experience with one or more of: embedded linux, FPGA, HW design, RF communication systems, cloud/server infrastructure, network architecture.
• End-to-end development from product concept to delivery to customer/market.

Salary

The salary range for this role is $156,000 - $186,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process. 

About the role

Muon seeks a Flight Software Engineer to join our satellite flight software team. The ideal candidate is a self-motivated versatile software developer with significant previous experience developing robust bare-metal / RTOS embedded devices or appliances. In this role, you will design, develop, integrate, and test the software and firmware that runs on our orbiting satellites. This position is based at our San Jose, CA office.

Responsibilities

• Integral member of the team defining and building Muon’s satellite bus platform
• Translate concepts and requirements into design and working implementations, supporting through to on-orbit operations
• Design, bring up, and support the embedded software environment that runs in our satellite flight systems and peripherals using ARM Cortex-M CPUs.
• Participate in evaluating and selecting technologies for our software foundation
• Write application, platform, and driver functionality in our flight software environment and teach others how to use it
• Integrate compute and peripheral subsystems in both software and hardware
• Collaborate with hardware team members on the design and bring up of Muon hardware
• Collaborate with software team members to set flight software architecture, select infrastructure and tools, and communicate with cloud backends.
• Participate in developing software and hardware-in-the-loop test strategies

Qualifications 

• B.S., M.S., or Ph.D. in computer science, electrical engineering, or related field
• 8+ years experience as a software engineer in a team environment
• Strong C/C++ programming, with some practical familiarity of other languages
• Great embedded systems fundamentals: resource-efficient design, low-level drivers, bit manipulation, responsive software and IRQ handling, RTOS frameworks, I/O and communication buses.
• Integration and control of external hardware devices
• Read and understand hardware data sheets
• Excellent communication and presentation skills

Nice-to-have Skills

• Knowledge of industry-standard data formats and schemas (ProtoBuf, YAML, JSON, etc)
• Familiarity with a Linux-based development environment
• Experience with one or more of: embedded linux, FPGA, HW design, RF communication systems, cloud/server infrastructure, network architecture.
• End-to-end development from product concept to delivery to customer/market.

Salary

The salary range for this role is $184,000 - $208,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process. 

We are seeking a Senior Software Optimization Engineer to join our growing team. Efficient’s Senior Software Optimization Engineer will design, optimize, and deploy applications for the world’s most energy-efficient programmable processor (the “Fabric”). In this role, you will take ownership of complex, performance-critical applications, working closely with Efficient’s compiler team to implement customer requirements, validate software quality, and provide deep technical insight into compiler interactions. This position is a unique opportunity to work on cutting-edge hardware/software co-design, while making an immediate impact in building the next generation of embedded applications.

Key Responsibilities 

• Independently design and implement complex embedded applications based on customer requirements, specifications, and existing code.
• Drive application optimization using Efficient’s compiler and software stack targeting the Fabric.
• Deploy and validate applications on the Fabric across software simulation and FPGA emulation environments.
• Own performance and energy-efficiency analysis, developing benchmarks and methodologies to evaluate applications against customer requirements.
• Identify, reproduce, and distill issues into minimum-viable test cases, conveying precise feedback to the compiler team.
• Collaborate deeply with the compiler team to test, debug, and refine compiler features.
• Contribute advanced optimizations to frameworks and libraries in domains such as DSP and machine learning.
• Provide architectural feedback based on hands-on experience to influence both software and hardware evolution.

Required Qualifications & Experience Requirements 

• Must be an excellent embedded engineer with 8+ years of work experience
• 3+ years of C/C++ experience
• Deep knowledge of at least one embedded platform, such as MSP430, STM32, Ambiq Apollo, PIC32, or similar
• Experience developing and deploying applications under resource constraints
• Experience using non-standard build environments and compiler toolchains, especially for embedded systems
• Experience using industry standard development and debugging tools for embedded development
• Strong attention to detail, good work ethic, ability to work on multiple projects simultaneously, and good communication skills 
• Good problem solving skills

Desired Qualifications & Experience Requirements 

• Experience using LLVM, MLIR, GCC, or a similar compiler framework to develop compiler passes
• Experience building TinyML models and deploying models under severe resource constraints (e.g. limited memory)
• Experience writing optimized BLAS and DSP kernels
• Knowledge of computer architecture

We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.