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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.
This role is hybrid, based out of Bangalore.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
Experience & Qualifications:
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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Apply to Tenstorrent
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Silicon Verification Engineer
Multiple roles across different levels
Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.
As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.
The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.
Responsibilities
Essential skills:
•8 to 12 Years of experience
•Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux
Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL
Benefits:
In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Ready to apply?
Apply to Graphcore
Silicon Verification Engineer
Multiple roles across different levels
Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.
As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.
The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.
Responsibilities
Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux
Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL
Benefits:
In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Ready to apply?
Apply to Graphcore
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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.
This role is hybrid, based out of Bengaluru, India.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
What You Will Learn
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
Apply to Tenstorrent
Share this job
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We're looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.
This role is hybrid, based out of Bangalore.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
What We Need
What You Will Learn
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
Apply to Tenstorrent
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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
As an Astera Labs’ Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs’ connectivity products that support the world’s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams.
Basic qualifications:
Required experience:
Preferred experience:
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Ready to apply?
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Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.
Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.
Responsibilities:
Skills & Qualifications:
Preferred:
Location:
Bangalore, India
Toronto, Canada
Sunnyvale, California.
For Sunnyvale: The base salary range for this position is $175,000 to $275,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.
People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:
Read our blog: Five Reasons to Join Cerebras in 2026.
Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.
This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.
Ready to apply?
Apply to Cerebras Systems
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Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.
Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.
Responsibilities:
Skills & Qualifications:
Preferred:
Location:
Sunnyvale, California.
Bangalore, India
Toronto, Canada
The base salary range for this position is $175,000 to $275,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.
People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:
Read our blog: Five Reasons to Join Cerebras in 2026.
Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.
This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.
Ready to apply?
Apply to Cerebras Systems
Role Overview
We are seeking a Senior Staff DFT Engineer to join a rapidly growing DFT design team focused on next-generation AI accelerator SoCs. In this role, you will define, architect, and implement current and future DFT/DFX solutions, supporting advanced SoC designs that leverage innovative memory-centric compute and heterogeneous chiplet architectures.
This is a highly hands-on role requiring both deep technical execution and high-level planning, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.
Location:
Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.
Drive DFT partitioning strategies for ATPG, including hierarchical and scalable approaches.
Implement ATPG compression and serialization, and perform RTL scan insertion with associated design rule fixes.
Own Memory BIST (MBIST) solutions, including memory repair and in-system test (IST), from implementation through verification and silicon debug.
Support boundary scan and define DFT mode constraints for IPs, providing timing feedback to STA teams.
Generate and integrate DFT RTL, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).
Apply and support IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.
Execute and verify ATPG (SAF, TDF) and MBIST using unit-delay and min/max timing simulations.
Perform detailed ATPG coverage analysis and drive coverage closure.
Collaborate with product and test engineering teams to deliver manufacturing test patterns for ATE.
Develop diagnostic tools and flows for ATPG, MBIST, and silicon bring-up on ATE.
Work hands-on with industry-standard DFT tools, contributing from low-level implementation through architectural planning.
BE/ME (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7+ years of experience in DFT, including scan test and MBIST.
Proficiency with HDLs such as Verilog, SystemVerilog, or VHDL.
Experience with scripting or programming languages (e.g., Python, Perl, TCL, C).
Strong ability to collaborate effectively in cross-functional and diverse teams.
Experience producing clear, detailed technical documentation.
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Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.
Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!
Compensation:
Ready to apply?
Apply to Baya Systems
Share this job
Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.
Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!
MICROARCHITECT AND RTL DESIGN
BENGALURU, INDIA
About the role:
We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities:
Design and develop microarchitectures for a set of highly configurable IP's
Microarchitecture and RTL coding ensuring optimal performance, power, area
Collaborate with software teams to define configuration requirements, verification collaterals etc.
Work with verification teams on assertions, test plans, debug, coverage etc.
Qualifications and Preferred Skills:
BS, MS in Electrical Engineering, Computer Engineering or Computer Science
8+ years and current hands-on experience in microarchitecture and RTL development
Proficiency in Verilog, System Verilog
Familiarity with industry-standard EDA tools and methodologies
Experience with large high-speed, pipelined, stateful designs, and low power designs
In-depth understanding of on-chip interconnects and NoC's
Experience within Arm ACE/CHI or similar coherency protocols
Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's
Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
Experience with modern programming languages like Python is a plus
Excellent problem-solving skills and attention to detail
Strong communication and collaboration skills
Compensation:
Ready to apply?
Apply to Baya Systems
Share this job
Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.
Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!
DESIGN VERIFICATION ENGINEER
BENGALURU, INDIA
About the role:
We are seeking a seasoned Design Verification Engineer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities:
Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems
Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards
Collaborate with software teams to define and implement configurable test benches
Work with design teams test plans, failure debug, coverage, etc.
Qualifications and Preferred Skills
BS, MS in Electrical Engineering, Computer Engineering or Computer Science
8+ years and current hands-on experience in block-level/IP-level/SoC-level verification
Proficiency in Verilog, SystemVerilog
Familiarity with industry-standard EDA tools for simulation and debug
Deep experience with UVM-based test benches
Experience with modern programming languages like Python
Knowledge of Arm AMBA protocols such as AXI, APB, and AHB
Understanding of Arm CHI protocol is a plus
Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs
Experience with formal verification techniques, emulation platforms is a plus
Excellent problem-solving skills and attention to detail
Strong communication and collaboration skills
Compensation:
Ready to apply?
Apply to Baya Systems
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