The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Implementation of DFT features into RTL using verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in finFET technologies.
• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

Silicon Verification Engineer

Multiple roles across different levels

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:

•8 to 12 Years of experience
•Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Silicon Verification Engineer

Multiple roles across different levels

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Bengaluru, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An experienced micro-architect who thrives in building CPU systems (multiple cores, multiple clusters of cores and subsystem components) from scratch.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

What We Need

• 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
• Collaborate closely with DV, PD, architecture and performance engineers to meet functional, timing, and power goals.
• Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environment, tools, and methodologies to improve development efficiency.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• How to design and optimize a custom RISC-V CPU system from first principles.
• Integration of open-source and industry-standard tools to improve RTL flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

We're looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You thrive in building robust verification environments using SystemVerilog, UVM and C++, and can define and drive verification plans independently.
• You bring a system-level mindset, with experience integrating multiple IPs into clusters or SoCs and verifying their interactions.
• You have a strong grasp of stimulus planning, debug techniques, and coverage closure for verifying complex hardware subsystems like caches, NoCs, and memory hierarchies.
• You’re comfortable working on features that span multiple IPs — such as coherence, security — and ensuring their correct behavior at the cluster or SoC level.

What We Need

• A Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• Strong experience with System Verilog and UVM-based verification.
• Proven ability to drive subsystem or SoC-level DV projects with integration and system feature validation responsibilities.
• Familiarity with AXI/CHI protocols, System IPs flows (like debug/trace, power management), and integration flows for multi-IP verification environments.

What You Will Learn

• Techniques to scale DV infrastructure for verifying high-performance RISC-V clusters and SoCs.
• How to verify multi-agent interactions across CPUs, system IPs and NoC or fabric components.
• Best practices for cross-IP feature convergence, integration-level planning, and reuse across cluster/SOC programs.
• How to collaborate with global teams across RTL, DV, software, and validation for cohesive system-level bring-up.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

As an Astera Labs’ Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs’ connectivity products that support the world’s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams.

Basic qualifications:

• Minimum of bachelor’s degree in computer engineering/ electrical engineering, Masters preferred.
• Minimum 10+ years of experience in a semiconductor company as a DFT engineer
• Must be local or willing to relocate

Required experience:

• Chip design, Verilog and System Verilog
• Verification, UVM methodology
• ATPG tools
• Scan insertion tools
• Gate-level simulations
• Static timing analysis
• Scripting (Perl/Tcl)
• Familiarity with ATE
• Hands-on expertise with commercial test generation tools for large complex designs
• Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression
• Experience running test compression software
• Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools

Preferred experience:

• Experience with defining and implementing SOC level verification on large designs.
• Working with 93k Tester

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:
Bangalore, India

Toronto, Canada

Sunnyvale, California.

For Sunnyvale: The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:

Sunnyvale, California.

Bangalore, India

Toronto, Canada 

The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Role Overview

We are seeking a Senior Staff DFT Engineer to join a rapidly growing DFT design team focused on next-generation AI accelerator SoCs. In this role, you will define, architect, and implement current and future DFT/DFX solutions, supporting advanced SoC designs that leverage innovative memory-centric compute and heterogeneous chiplet architectures.

This is a highly hands-on role requiring both deep technical execution and high-level planning, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.

Location:

Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.

Key Responsibilities

• Drive DFT partitioning strategies for ATPG, including hierarchical and scalable approaches.

• Implement ATPG compression and serialization, and perform RTL scan insertion with associated design rule fixes.

• Own Memory BIST (MBIST) solutions, including memory repair and in-system test (IST), from implementation through verification and silicon debug.

• Support boundary scan and define DFT mode constraints for IPs, providing timing feedback to STA teams.

• Generate and integrate DFT RTL, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).

• Apply and support IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.

• Execute and verify ATPG (SAF, TDF) and MBIST using unit-delay and min/max timing simulations.

• Perform detailed ATPG coverage analysis and drive coverage closure.

• Collaborate with product and test engineering teams to deliver manufacturing test patterns for ATE.

• Develop diagnostic tools and flows for ATPG, MBIST, and silicon bring-up on ATE.

• Work hands-on with industry-standard DFT tools, contributing from low-level implementation through architectural planning.

Minimum Qualifications

• BE/ME (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 7+ years of experience in DFT, including scan test and MBIST.

• Proficiency with HDLs such as Verilog, SystemVerilog, or VHDL.

• Experience with scripting or programming languages (e.g., Python, Perl, TCL, C).

• Strong ability to collaborate effectively in cross-functional and diverse teams.

• Experience producing clear, detailed technical documentation.

MICROARCHITECT AND RTL DESIGN  

BENGALURU, INDIA

About the role:

We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities:

• Design and develop microarchitectures for a set of highly configurable IP's

• Microarchitecture and RTL coding ensuring optimal performance, power, area

• Collaborate with software teams to define configuration requirements, verification collaterals etc.

• Work with verification teams on assertions, test plans, debug, coverage etc.

Qualifications and Preferred Skills:

• BS, MS in Electrical Engineering, Computer Engineering or Computer Science

• 8+ years and current hands-on experience in microarchitecture and RTL development

• Proficiency in Verilog, System Verilog

• Familiarity with industry-standard EDA tools and methodologies

• Experience with large high-speed, pipelined, stateful designs, and low power designs

• In-depth understanding of on-chip interconnects and NoC's

• Experience within Arm ACE/CHI or similar coherency protocols

• Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's

• Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus

• Experience with modern programming languages like Python is a plus

• Excellent problem-solving skills and attention to detail

• Strong communication and collaboration skills

DESIGN VERIFICATION ENGINEER

BENGALURU, INDIA

About the role:

We are seeking a seasoned Design Verification Engineer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities​:

• Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems

• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards

• Collaborate with software teams to define and implement configurable test benches

• Work with design teams test plans, failure debug, coverage, etc.​

Qualifications and Preferred Skills​

• BS, MS in Electrical Engineering, Computer Engineering or Computer Science

• 8+ years and current hands-on experience in block-level/IP-level/SoC-level verification

• Proficiency in Verilog, SystemVerilog

• Familiarity with industry-standard EDA tools for simulation and debug

• Deep experience with UVM-based test benches

• Experience with modern programming languages like Python

• Knowledge of Arm AMBA protocols such as AXI, APB, and AHB

• Understanding of Arm CHI protocol is a plus

• Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs

• Experience with formal verification techniques, emulation platforms is a plus

• Excellent problem-solving skills and attention to detail

• Strong communication and collaboration skills