We are seeking a junior-to-mid level SOC Emulation Engineer to support our hardware emulation infrastructure and internal chip design teams. This role focuses on integrating vendor and custom hardware transactors, developing Python-based test frameworks, and providing technical support to emulation users across multiple chip projects.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Background in Electrical/Computer Engineering or Computer Science with 1-3 years of experience in chip design, verification, or emulation.
• Proficient in Python for automation and test development, with a working knowledge of C++ and the ability to navigate SystemVerilog RTL.
• Skilled at using modern AI tools (Claude, ChatGPT, Copilot) to accelerate code generation, debugging, and documentation analysis.
• Energetic about supporting diverse teams, from high-level software to low-level firmware, to solve complex runtime and build issues.

What We Need

• Ability to integrate vendor and custom transactors into RTL testbenches while handling clock domain and tri-state resolution.
• Experience building Python APIs (using pybind11) and maintaining CMake-based compilation flows for emulation libraries.
• Solid understanding of standard chip interfaces, bus protocols, and hardware synchronization (resets/clocking).
• A commitment to triaging and debugging the full stack, spanning from Python tests and C++ bindings down to hardware.

What You Will Learn

• Deepening your expertise with world-class platforms like Synopsys Zebu for massive-scale silicon validation.
• Gaining a holistic view of chip development by bridging the gap between hardware RTL and software drivers.
• Building and optimizing large-scale emulation build and run tooling for high-performance engineering teams.
• Refining your ability to gather requirements and facilitate communication between hardware designers and software engineers.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

JOB SUMMARY

We are seeking a highly skilled and experienced Engineering Manager to lead Hardware Integration at Apptronik. You will be at the forefront of bringing our humanoid robot platform to life, ensuring every physical subsystem—from high-performance actuators to complex sensor suites—is meticulously integrated into a cohesive, functional system. This is a critical leadership role for an engineer who excels at bridging the gap between individual component design and a fully realized, top-level robotic platform.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

• Team Leadership: Lead and mentor a specialized team of engineers and technicians focused on the physical integration and assembly of complex humanoid robotic systems.
• Hardware Bring-Up: Direct prototype hardware integration, guiding the team through physical assembly, initial power-on, and the transition of new hardware designs from the bench to the platform.
• Wiring & Interconnect Architecture: Own all aspects of Wiring and Harness Design and Integration, ensuring robust, manufacturable, and reliable power and data distribution across the entire platform.
• Kinematic & Dynamic Calibration: Develop and release calibration schemes to ensure the robot's physical assembly is precisely aligned with its digital and control models.
• Design for Integration (DfI): Collaborate with mechanical and electrical design teams to ensure sub-assemblies are optimized for modularity, ease of integration, and long-term reliability.
• Lead HIL (Hardware-in-the-Loop) Testbed Development: Design and build hardware in the loop testbed to enable rapid iteration cycle and facilitate integration and bring up tasks, as well as future testing activities.
• Configuration Management: Serve as the primary owner for hardware configuration, including revision control and the creation/maintenance of accurate Top-Level System Bills of Materials (BoM) for the robot and auxiliary equipment.

SKILLS AND REQUIREMENTS

• Experience: 6+ years of hands-on hardware engineering experience, specifically focused on complex robotics systems
• Leadership: 2+ years in a direct management or technical lead role, with a proven track record of mentoring multi-disciplinary teams.
• Harness Expertise: Deep, hands-on expertise in the design, routing, and manufacturing of high-density wiring and cable harnesses.
• Configuration Mastery: Direct experience managing complex BoMs and hardware versioning within a fast-paced R&D or production environment.
• Systems Thinking: Strong ability to troubleshoot interface issues between mechanical, electrical, and firmware layers during the integration phase.
• Communication: Exceptional leadership and problem-solving skills, with the ability to coordinate across diverse engineering departments.

EDUCATION and/or EXPERIENCE

• Education: Bachelor’s or Master’s degree in Electrical Engineering.

PHYSICAL REQUIREMENTS 

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate

Graphcore is a globally recognized leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data center hardware that provide the specialized processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.   

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. 

RESPONSIBILITIES

The thermal engineer will work in a project team delivering complex AI data center hardware.  Primary responsibility is to ensure the overall product functionality and meet all applicable technical thermal specifications.  The engineer will be responsible for the overall thermal solution, creation of specifications, design review and qualification, and testing and validation.  This role involves deep understanding of thermal management principles, simulation, testing, and collaboration with cross-functional teams to deliver high-performance and reliable server cooling systems. 

You’ll be responsible for designing, developing, modifying and evaluating the liquid cooling solutions focusing on direct liquid cooling (DLC).  As part of the technical function, you will be responsible in working with select ODM vendors to manage the product thermal specification, development schedule, meet various deliverables, resolve technical issues, and ensure product meets specification, cost and quality goals.  You will be responsible in guiding and directing ODM vendors to deliver thermal designs, implementation, monitor testing, review cost and review technical design information to provide clear directions to ODM.  In addition, you will also be working with third party vendors and suppliers to ensure product features are being achieved.  

REQUIREMENTS

Bachelor’s, Master’s or Ph. D degrees in mechanical engineering.  Minimum of 2 to 5 years of server thermal design experience.  Experience in system level thermal design focusing on DLC and cold plate cooling heatsink technology as well as system level control logic is a plus. 

Skills:

• Understanding the basic foundations of thermal fluid dynamics and heat transfer.
• Ability to lead the design and development of liquid cooling solutions. This includes conceptualization, prototyping, simulation, validation, and optimization of heat sinks, cold plates, CDU/CDM, and other liquid cooling components.
• Ability to perform thermal simulations and analyses utilizing industry-standard software (e.g., FlowTherm, ANSYS, COMSOL) to analyze thermal behavior and optimize design for performance and efficiency.
• Ability to develop and execute test plans to validate thermal solutions, ensuring compliance with industry standards and performance goals.
• Experience working closely with senior engineers, chip and board designers, and software/firmware engineers to integrate liquid cooling solutions into server products.
• Understanding of microprocessor architecture and thermal profiles.
• Understanding of system level thermal design focusing on fan and heatsink technology.
• Experience effectively dealing with conflict.
• Communicates well verbally, in writing, and graphically.
• Ability to establish clear goals and formulate plans to achieve them.
• Good root-cause analysis and problem-solving skills.
• Works independently and as part of a team.
• Excited about technology and has the desire to learn new tasks and technologies.

DIFFERENTIATORS

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.

We are seeking an IP Software Generalist to develop and optimize the software stack for our IP customers, enabling them to successfully integrate our AI and RISC-V hardware into their systems. In this role, you will build and support a versatile range of software components, from bare-metal firmware and drivers to system-level tools and APIs, ensuring a seamless customer experience. You will partner closely with hardware engineering, IP delivery, customer support, and product teams to deliver robust, scalable, and high-performance software solutions tailored to diverse customer architectures. Success in this role requires adaptability, strong system-level debugging skills, and the ability to bridge the gap between complex hardware IP and user-friendly software integration.

This role is hybrid, based out of Austin, TX; Toronto, ON; or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced software engineer with a strong foundation in C/C++, system programming, and low-level software design.
• Background in firmware, device drivers, embedded systems, or hardware-software co-design.
• Skilled at navigating and troubleshooting complex, full-stack software environments.
• Known for working effectively with cross-functional teams and external customers to resolve integration challenges.
• Able to balance versatile, hands-on coding with high-level architectural problem-solving.

What We Need

• Develop, optimize, and maintain software components for Tenstorrent’s hardware IP offerings.
• Define and build reference software, SDKs, and toolchains to streamline the customer integration process.
• Diagnose and resolve complex hardware/software interaction issues during customer bring-up and deployment.
• Drive the creation of high-quality documentation, test suites, and integration guides for IP software deliverables.
• Partner cross-functionally with hardware and architecture teams to ensure future IP designs are optimized for software usability.

What You Will Learn

• How to build and deploy robust software stacks for cutting-edge AI and RISC-V silicon IP.
• How to drive successful hardware-software integration across a diverse range of customer environments and architectures.
• Firsthand exposure to the complete silicon IP lifecycle, from initial bring-up to massive-scale customer deployment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is hybrid based in Austin, TX

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills

Join our innovative team as a Director, Systems & Solutions where you'll play a pivotal role in deploying and optimizing cutting-edge computer systems and AI hardware. If you have a passion for hardware technologies, including accelerators, CPUs, GPUs, and thrive in a dynamic, hands-on technical environment, we would love to hear from you. In this role you will be leading a team and helping us scale our customer base.

This role is hybrid, based out of Santa Clara, CA; Austin, TX or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on manager with a deep understanding of computer systems and AI hardware, driven by curiosity and a passion for performance.
• You’re comfortable getting into the technical details - from CPU and GPU architecture to firmware and drivers and thrive in dynamic, hands-on environments.
• You excel at problem solving and enjoy working directly with customers to implement and optimize advanced computing solutions.
• You communicate clearly, collaborate effectively across teams, and take pride in delivering reliable, high-quality systems.
• You’re motivated by impact - eager to see your work come to life in the next generation of AI and high-performance compute deployments.

What We Need

• Strong experience with computer hardware and system architecture, including CPUs, GPUs, FPGAs, and AI accelerators.
• Deep understanding of Linux operating systems, with experience in configuration, performance optimization, and administration.
• Proficiency in system software, including drivers, firmware, and related hardware-level tools.
• Working knowledge of electrical systems, including wiring, cabling, and thermal management.
• The ability to travel up to 50% of the time both domestically and internationally. 

What You Will Learn

• How to deploy, validate, and optimize AI compute systems at scale across diverse customer environments.
• End-to-end exposure to hardware-software integration, from firmware and drivers to full system bring-up.
• Hands-on experience with accelerator-based architectures and cutting-edge hardware design.
• Collaboration with world-class engineering teams building open, high-performance systems based on RISC-V and modular chiplet architectures.
• The opportunity to directly shape how customers adopt and scale next-generation AI and HPC hardware, helping push the boundaries of performance and efficiency.
  
  

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

At Tenstorrent, you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated mentor and the opportunity to move between the digital design, verification, firmware, software and system engineering teams.   

This role is on-site based in Austin, TX; Santa Clara, CA; or Toronto, ON

Responsibilities:

• Develop machine learning graph compiler 
• Participate in the co-design of Tenstorrent's hardware and software stack 
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack 
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler 
• Develop high-performance run-time engine 
• Integrate the Tenstorrent software into leading machine learning frameworks 
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications 
• Develop novel ML models and primitives that take advantage of Tenstorrent’s breakthrough architecture to deliver orders of magnitude performance & efficiency improvements 

Experience & Qualifications:

• Final year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well 
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus 
• Strong problem solving and analytical skills

Our Tensix team is building custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI. Design Verification Engineers on this team validate compute IP and subsystems and build scalable DV infrastructure to keep verification fast, automated, and production-grade.

This role is hybrid, based out of Toronto, ON or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Experienced in modern verification methodologies with strong SystemVerilog skills and exposure to structured testbench development.
• Comfortable working from block-level to system-level verification and reasoning about microarchitecture behavior from specs and waveforms.
• Proficient in Linux environments with Python, or Bash scripting for automate builds, parse logs, manage CI pipelines.
• Skilled in coverage-driven verification and confident debugging across RTL, testbench, and workload scenarios.
• Motivated by AI hardware and eager to learn verification strategies for new architectures and domains.

What We Need

• Contribute to verification of Tensix IP and subsystems from early planning through tape-out, owning coverage goals and driving them to closure.
• Build and maintain reusable verification environments, agents, scoreboards, and supporting infrastructure in SystemVerilog and Python.
• Develop constrained-random and directed tests and close functional, code, and assertion coverage using data-driven approaches.
• Debug complex issues across RTL and testbench while collaborating with design, firmware, compiler, and architecture teams.
• Help evolve DV infrastructure including regression flows, CI/CD integration, EDA compute environments, and reproducible setups.

What You Will Learn

• How Tenstorrent verifies AI-native compute architectures including Tensix cores, RISC-V CPUs, matrix units, vector units, and datapath.
• How simulation, emulation, and software-driven workloads combine to validate both functional correctness and performance.
• How numerical precision formats such as BF16, FP4, and INT8 and on-chip dataflow impact verification complexity and coverage strategy.
• How to build scalable DV infrastructure across hybrid compute environments including containerized regression systems.
• How data analytics and modern AI tooling can enhance verification workflows and accelerate convergence.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments.

This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems.

The Team

The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms.

The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems.

This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment.

Responsibilities and Duties

• Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure.
• Support engineering bring-up activities, including component validation and firmware interaction testing.
• Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues.
• Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements.
• Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles.
• Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability.
• Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation.
• Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics.
• Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases.

Candidate Profile

Essential

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
• Strong experience with server hardware architectures and board-level debugging.
• Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures.
• Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure.
• Strong collaboration skills and ability to work effectively in fast-paced engineering environments.
• Excellent written and verbal communication skills.

Desirable

• Experience supporting prototype or pre-production hardware bring-up.
• Familiarity with data center facilities, including liquid cooling and power distribution systems.
• Experience using Python, Bash, or automation tools for hardware validation or troubleshooting.
• Exposure to structured failure analysis and reliability engineering methodologies.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments.

This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems.

The Team

The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms.

The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems.

This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment.

Responsibilities and Duties

• Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure.
• Support engineering bring-up activities, including component validation and firmware interaction testing.
• Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues.
• Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements.
• Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles.
• Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability.
• Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation.
• Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics.
• Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases.

Candidate Profile

Essential

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
• Strong experience with server hardware architectures and board-level debugging.
• Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures.
• Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure.
• Strong collaboration skills and ability to work effectively in fast-paced engineering environments.
• Excellent written and verbal communication skills.

Desirable

• Experience supporting prototype or pre-production hardware bring-up.
• Familiarity with data center facilities, including liquid cooling and power distribution systems.
• Experience using Python, Bash, or automation tools for hardware validation or troubleshooting.
• Exposure to structured failure analysis and reliability engineering methodologies.

JOB SUMMARY
We are looking for a seasoned Staff Technical Program Manager to lead complex, cross-functional programs that span multiple product lines and engineering organizations. As a Staff Technical Program Manager, you will set the strategic direction for how programs are planned and executed, drive alignment between executive stakeholders and engineering leadership, and shape the technical and operational frameworks that enable Apptronik to deliver humanoid robots at scale. You will mentor other program managers, influence org-wide priorities, and serve as a trusted partner to engineering leaders in navigating the most ambitious and highest-risk initiatives in the business.

JOB SUMMARY

We are looking for an experienced Senior Technical Program Manager to lead large cross-functional teams through a full product lifecycle. As a Senior Technical Program Manager, you will orchestrate the integration of various engineering disciplines to help develop and drive program plans. 

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Ownership: Own programs end-to-end. Identify resource requirements and be accountable for executing on company goals and roadmap. Challenge assumptions and foster a results-driven culture.
• Orchestration: Partner directly with engineering teams to execute solutions and adapt quickly when priorities shift. Coordinate across multiple functions including engineering, operations, supply chain, and finance to keep all stakeholders aligned and informed.
• Planning: Create and communicate clear paths to success. Develop schedules, define milestones, and maintain execution plans that keep programs on track.
• Communication: Proactively communicate project status, risks, and issues to stakeholders. Clearly articulate requirements, goals, and milestones across teams.

SKILLS AND REQUIREMENTS

• System-Level Product Development Leadership – Experience managing complete hardware + software product life cycles from concept through deployment and scaled production.
• Hands-On Technical Partnership – Proven ability to work closely with engineering teams on architectural decisions, interface definition, and complex technical problem-solving — not just schedule management.
• New Product Introduction (NPI) - Demonstrated success transitioning products from prototype to manufacturing, including DFM/DFA considerations. 
• Cross-Disciplinary System Integration – Proven experience coordinating mechanical, electrical, firmware, product, software, and AI/ML teams to deliver fully integrated, sophisticated systems. 
• Program Execution & Results Orientation – Track record of driving measurable outcomes, managing critical path and interdependencies, and delivering against company roadmap goals.
• Deployment & Commercialization Readiness – Experience supporting system integration and scaling hardware/software platforms. 
• Influence in Resource-Constrained Environments – Ability to align product and engineering teams, prioritize effectively, and execute successfully in fast-paced, limited-resource settings.

EDUCATION AND EXPERIENCE

• Bachelor's degree in Electrical, Computer, Mechanical Engineering or Applied Physics required
• 5+ years of experience in program management or engineering management, including leading cross-functional teams in both hardware and software
  • Preferred: Experience in robotics
  • Preferred: Master's degree in Engineering

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer.
• Must be able to lift 15 pounds at times.
• Vision to read printed materials and a computer screen.
• Hearing and speech to communicate.

JOB SUMMARY

At Apptronik, we are building humanoid robots that require an operating system as sophisticated and resilient as their hardware. As a Senior Embedded Linux Engineer, you will own the entire Linux platform ecosystem. You aren't just "using a build tool"; you are architecting a custom distribution from the ground up to ensure our robots are performant, secure, and field-ready.

Your mission is to manage the full lifecycle of the OS: from factory provisioning and secure imaging to real-time kernel tuning and reliable OTA updates. You will ensure that every cycle of the CPU is optimized for our control loops and that our fleet remains stable.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

Custom OS Architecture & Distribution:

• Architect and maintain a custom, production-grade Linux distribution using Yocto, Buildroot, or an equivalent professional build system.
• Demonstrate complete ownership of the OS layers, managing the relationship between the bootloader, kernel, board support packages (BSPs), and user-space libraries.
• Develop and maintain a highly repeatable and well-documented build process that serves as the single source of truth for all robot compute modules.

Hardware Enablement & Performance Optimization:

• Perform low-level kernel configuration and tuning to meet the strict latency requirements of humanoid robotics.
• Implement core isolation and process priority optimization to ensure critical control loops have deterministic access to resources.
• Optimize the OS footprint and resource utilization (CPU, memory, and I/O) to maximize the efficiency of our Nvidia Jetson (Jetpack) and AMD64 platforms.
• Integrate and debug hardware drivers for peripherals, including Bluetooth (BlueZ), Wi-Fi, and specialized robotics sensors.

Platform Resilience, Provisioning & Updates:

• Factory & Provisioning: Architect the workflows for initial device provisioning, including secure boot initialization, disk partitioning, and factory imaging processes.
• OTA Strategy: Own the end-to-end Over-the-Air (OTA) update architecture (A/B atomic updates) using frameworks like Mender, RAUC, or SWUpdate.
• System Stability: Implement OverlayFS or similar union-mount strategies to create a resilient, "unbreakable" system that supports read-only roots and safe factory resets.

Platform Security & Hardening

• Hardware Root of Trust & Secure Boot: Architect and implement end-to-end Secure Boot chains (from BootROM to Kernel) using TPM 2.0 or Secure Enclaves to ensure only authenticated firmware and OS images execute on the robot.
• System Hardening & Isolation: Implement Linux Security Modules (LSMs) such as SELinux or AppArmor to enforce mandatory access controls; utilize cgroups and namespaces to isolate critical robotics processes from non-critical telemetry.
• Cryptographic Infrastructure: Manage the lifecycle of device identity and cryptographic keys; oversee disk encryption (dm-crypt/LUKS)

Infrastructure & Tooling:

• Own the CI/CD pipeline for OS image generation, ensuring that builds are automated, tested, and traceable.
• Create and maintain comprehensive documentation for the platform architecture, build environment, and flashing procedures.
• Develop specialized diagnostic tools (Python/Bash) for system monitoring and field troubleshooting.

SKILLS AND REQUIREMENTS

• OS Construction: Proven ability to build a custom Linux distribution from scratch. You must understand how to manipulate every layer of the rootfs and toolchain.
• Build System: Experience Yocto/OpenEmbedded, Buildroot, or equivalent professional-grade embedded build environments.
• Kernel & Performance Tuning: Experience with PREEMPT_RT, core isolation (isolcpus), and tuning Linux for real-time robotics or industrial control.
• Nvidia Ecosystem: Deep familiarity with Nvidia Jetson hardware, including L4T, Jetpack SDK, and flashing utilities.
• Resiliency Engineering: Hands-on experience with OverlayFS, partition management, and fail-safe OTA update mechanisms.
• Security Engineering: Hands-on experience with LUKS disk encryption, TPM 2.0 integration, and managing PKI (Public Key Infrastructure) for embedded devices.
• Hardware Interfacing: Experience debugging hardware protocols (I2C, SPI, UART, USB) and wireless stacks (Bluetooth/BlueZ).
• Documentation & Process: A disciplined approach to documentation and creating repeatable engineering processes.

Preferred:

• Experience with "Modern DevOps" (Containerized build environments, GitLab CI, or automated hardware-in-the-loop testing).
• Knowledge of Secure Boot, disk encryption, and TPM integration.
• Knowledge of real time operating systems
• Programming experience in C++ and Python.

EDUCATION and/or EXPERIENCE

• Bachelor’s degree in Computer Science, Computer Engineering, or a related technical field.
• 5+ years of experience in Embedded Linux or Systems Engineering.
• Demonstrated experience shipping and maintaining a custom Linux OS on high-complexity physical hardware.

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate

JOB SUMMARY

Apptronik is seeking a Robotics Test Engineer to join the Software Integration & Test (RSIT) team. In this role, you will write the automated tests that verify Apollo's software at the integration layer, partner with senior engineers on defect investigations, and help grow the regression coverage that keeps each release safer than the last. You will work hands-on with our pytest-based test infrastructure, HIL benches, and the broader RSIT platform to turn software-level requirements into verifiable tests. This is a role designed for someone who wants to grow into deep expertise in robotics test engineering, with mentorship from senior teammates and meaningful ownership of test suites from day one.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

• Test Authoring: Write automated integration, contract, and ICD conformance tests in pytest against software-level requirements, with clear pass/fail signals that feed the release gate.
• Defect Investigation: Partner with senior engineers on root-cause investigations for CI failures, escaped defects, and stochastic issues, building familiarity with debugging tools (sanitizers, log analysis, MCAP playback) over time.
• Regression Coverage: Convert defects into permanent regression tests, ensuring every escape becomes a new automated check in the gate.
• HIL Test Execution: Run and maintain test suites on hardware-in-the-loop benches, capture data, and report results into the team's dashboards and result reporting systems.
• Test Suite Maintenance: Keep existing test suites healthy: triage flaky tests, update fixtures as the stack evolves, and improve readability and reliability of test code.
• Requirements Engagement: Read software-level requirements and Systems Validation plans, ask clarifying questions, and surface ambiguity or untestable language to senior teammates and Systems Engineering.
• Tooling Feedback: Serve as an active customer of the RSIT platform, surfacing friction in CI, dashboards, or release tooling so the Release & Integration team can improve developer experience.
• Cross-Functional Collaboration: Work with stack engineers, firmware engineers, and senior RSIT teammates to understand the systems being tested and produce verification that reflects how those systems actually behave.

SKILLS AND REQUIREMENTS

• Programming: Working proficiency in Python, including ability to write clean, maintainable test code and small utility scripts. Comfort reading C++ to understand the systems under test.
• Test Frameworks: Hands-on experience with pytest or an equivalent framework (unittest, Google Test, JUnit), including fixtures, parameterization, and test organization.
• Linux Comfort: Day-to-day fluency on the Linux command line, including basic systemd, log inspection, file system navigation, and shell scripting.
• Version Control: Solid Git fundamentals, including branching, pull requests, and code review participation.
• Debugging Mindset: Demonstrated curiosity and persistence in tracking down bugs, including willingness to read code in unfamiliar parts of the stack to understand a failure.
• Communication: Ability to write clear bug reports, test documentation, and pull request descriptions. Comfort asking questions and surfacing blockers early.
• Learning Orientation: Eagerness to grow into deeper expertise in robotics, real-time systems, and verification engineering through mentorship, code review, and hands-on work.
• Preferred Qualifications:
• Exposure to ROS or ROS2.
• Experience with CI/CD systems (Bitbucket Pipelines, GitHub Actions, Jenkins, or similar) as a user.
• Familiarity with hardware-in-the-loop testing or other forms of hardware-integrated software verification.
• Experience with observability tools (Grafana, Loki, Prometheus) as a consumer of dashboards and logs.
• Background in robotics, autonomous systems, aerospace, or another hardware-integrated domain through coursework, internships, or prior roles.
• Familiarity with sanitizer tooling (ASan, TSan, UBSan) or other dynamic analysis approaches.

EDUCATION and/or EXPERIENCE

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, Robotics, or a related technical field.
• 2-4 years of professional experience in software development, test engineering, or a related discipline. Strong internship and project experience may substitute for a portion of this requirement.
• Experience writing or maintaining automated tests in a production codebase is strongly preferred.

PHYSICAL REQUIREMENTS:

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate

Team Description:

Join the Brain Interfaces Software Team and be part of a team of remarkable and driven engineers accelerating our pathway to human ready brain-computer interfaces. We are a small, but fast-moving team that collaborates with other exceptional teams of mechanical, electrical, and firmware engineers.

Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Description & Responsibilities:

We are looking for a versatile Software Engineer who is passionate about architecting and implementing elegant software solutions and thrives with autonomy to propose creative approaches to problems. You will be responsible for writing software to interact with Neuralink’s implant, as well as building systems for manufacturing and testing the device. Additionally, you will be expected to:

• Develop and improve Neuralink’s implant manufacturing line acceptance software and station
• Develop and improve Neuralink's implant design verification testing software
• Optimize and maintain Neuralink’s implant software build infrastructure
• Develop and improve Neuralink’s implant SDK

Required Qualifications:

• Fluent in Python and at least one system language including Rust, C++, and C (don’t get hung up on this—being an exceptional software engineer matters above all)
• Experience and proficiency with Linux/Unix systems
• Evidence of exceptional ability in engineering, mathematics, or computer science
• Solid understanding of engineering first principles
• Strong intuition for what matters in a production system vs. research-grade environments

Additional Requirements and Competencies:

• You find large challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver; you may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that what matters is delivering reliable solutions (Our ultimate aim is to help people; the “right” solution doesn’t always achieve that)
• You are mission-driven and goal-oriented in your approach to solving problems
• You feel a sense of urgency to get things done sooner rather than later—because there is so much we, as people, can contribute to the world and accomplish in this life, it’s a shame to waste time
• You are resourceful, flexible, and adaptable; no task is too big or too small

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Energy/performance profiling and analysis
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing cost and performance under manufacturing process variation 
• Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 5+ years of experience in digital design
• Expertise in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer Intern, your responsibilities will include:

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and implementation of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing energy efficiency and performance under manufacturing process variation 
• Complex system-on-chip verification
• Behavioral level modeling and model equivalence check
• FPGA emulation
• Analog mixed-signal co-simulation
• Design for testability 
• Collaboration on silicon bring-up tests with silicon validation engineers 

Required Qualifications:

• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 2+ years of experience in digital design
• Proficient in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications:

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVM 
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization
• Experience designing PCBs or writing firmware.

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

Team Description:

We build the electrical systems that make high-bandwidth brain–computer interfaces possible. This includes neural signal acquisition and stimulation to wireless power delivery, embedded processing, and system integration—all within devices small enough to be implanted in the human body and efficient enough to operate under strict thermal and power constraints. Our work sits at the intersection of analog, RF, digital, and biological systems. Many problems in this space do not present clean abstractions or clear failure modes. Success often depends on careful measurement, iteration, and engineering judgment across multiple interacting systems.

Job Description and Responsibilities:

We are looking for an experienced, hands-on electrical engineer for implant electronics board design, integration with our custom chips, testing, and quality control. You will have the opportunity to contribute to advanced projects, not only work on incremental changes, and be an integral member of a small, fast-moving team. You will be working on all phases of board design (part selection, schematic design, layout, and bring-up) as well as collaborating closely with chip designers, firmware engineers, mechanical engineers, and microfabrication experts for system integration.

• Utilize electrical engineering fundamentals and best system design practices to build on your ability to deliver high-performant, reliable, and manufacturable extremely size-constraint systems
• Gain understanding of all phases of system and board design, from system definition to part selection, schematic design, layout, bring up, and design verification
• Contribute to R&D investigations and experiments to demonstrate feasibility of new technology for the implant and the charger
• Gain experience working cross functionally to ensure successful systems integration
• Contribute to system improvements that decrease latency and increase battery life, reliability, and safety
• Develop ability to design and deploy systems for implant-charger hardware in the loop testing, and manufacturing line quality control

Required Qualifications: 

• Strong EE fundamentals
• Experience designing PCBs for low power and size constrained applications
• Experience with PCB CAD tools (Altium, Eagle, KiCad, Allegro)
• Experience with sensors, power management, and signal/power integrity
• Comfortable with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable with lab equipment (oscilloscope, VNA, etc.)
• Basic C and Python programming skills

Preferred Qualifications:

• Experience with firmware development for embedded systems (C/C++)
• Experience with wireless systems (BLE, WIFI, Zigbee)
• Experience building and bringing-up MCUs or FPGA
• Proficiency with ME CAD tools (Solidworks, AutoCAD)
• Experience with analog circuit design

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

Team Description:

The Surgery & Robotics Hardware Team is looking for Electrical Engineers who want to advance the future of healthcare solutions with technology. At Neuralink we recognize that increasing healthcare costs, lack of access, and insufficient numbers of neurosurgeons globally require new approaches to enable greater access to our devices. To address these challenges we design fully autonomous robotics systems, human assistive surgical tools, and design entire surgical suites in order to provide better experiences for our customers.

Our team works on our surgical robot system which aims to fully automate the implantation of the Neuralink implant. We design and integrate multi-axis robotic arms, perception systems including custom imaging hardware, optical coherence tomography tissue imaging, power electronics, and safety systems such as 3D spatial mapping/object avoidance sensors. Robotics is part of a larger system of tools we work on. For example, using pre-op MRI scans we generate patient anatomy data that we later use in surgery to register precise surgery site locations. 

In addition to research and development of modern surgical technology, we also are responsible for bringing these technologies to market. We perform full lifecycle testing for all devices we design and ultimately manufacture them for use in human surgeries. To date, our designs have served over 20 individuals, and in the coming years our designs will serve thousands of individuals who wish to use our implant technology.

Job Description and Responsibilities:

As an Electrical Engineer on the Surgery & Robot Hardware Team, you will be expected to design, verify, and oversee the transition to production of a variety of custom electronics systems.  This role offers substantial autonomy and the exciting opportunity to own creative decisions and execute on new, impactful projects such as robotics stage designs, motor drives and controls, custom camera designs, manufacturing automation, and the firmware that enables all of these devices.

Required Qualifications: 

• Bachelor’s degree in Electrical Engineering or a related field or equivalent experience
• Professional experience delivering on all phases of electronics design (requirements, part selection, schematic, layout, manufacturing, test)
• Demonstrated depth in at least one of the following:
  • Power electronics: experience designing custom power conversion, distribution, eFusing, and battery management systems in the low-to-medium (1W-2kW) range
  • FPGA hardware design for time sensitive systems such as image processing, high-speed data acquisition, or real time networking. Professional experience in FPGA selection, RTL development, digital signal processing theory and techniques, and hardware design to interface high speed physical layer devices via PCIe, MIPI, SLVS-ec, LVDS, etc
  • Manufacturing automation design: professional experience architecting and implementing manufacturing automation solutions for products that currently ship at the scale of 1000’s+
• Practical electronics design knowledge including designing for EMC, ESD, thermals and packaging

Preferred Qualifications: 

• A portfolio showcasing your hardware designs 
• Demonstrable experience developing electronics for safety critical systems such as medical devices, aerospace, automotive, or military
• Demonstrable experience shipping code in one of the following languages: C, C++, Python, or Rust
• Altium experience

Team Description:

Join the Brain Interfaces Embedded Systems Team and be part of an elite team of engineers working on high-performance, safety-critical embedded systems for the next-generation brain-computer interfaces. You will have the opportunity to work closely with chip designers, electrical engineers, and software engineers on a small, fast-moving team.

Job Description and Responsibilities: 

We are looking for experienced, hands-on engineers who are interested in exploring what's possible in highly powered and latency-constrained environments. Firmware is the kernel of operation for the implant, and you have the chance to define and implement features that have a significant impact on the product’s capabilities. As an Embedded Software Engineer, you will be expected to:

• Own complex challenges from definition to solution
• Utilize your ability to work cross functionally to deliver safety critical systems while considering power, radio, and thermal requirements
• Take ownership of products and/or core features; from planning and design to execution and testing
• Build on your fundamental understanding of hardware while contributing to bare-metal firmware
• Embrace a fast-paced iterative environment that prioritizes shipping manufacturable solutions 

Note: The team is hiring embedded engineers at all levels, both junior and senior. What matters most is evidence of exceptional abilities and a drive to succeed.

Required Qualifications: 

• Bachelor’s degree in computer science, electrical engineering, related field, or equivalent experience 
• 1+ years of experience with embedded systems (including internships)
• Proficient in embedded C or Rust
• Ability to design bare-metal embedded systems in highly constrained environments
• Strong Electrical Engineering fundamentals 
• Signal processing fundamentals 
• You find enormous challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver. You may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that delivering reliable manufacturable solutions matters
• You are a cross-disciplinary team member. You are excited to work with and learn from chip designers to neuroscientists

Preferred Qualifications: 

• Experience with embedded stacks for ARM cores
• Experience with safety-critical systems
• Experience with FPGA development and testing
• Experience with RF, BLE, TCP/IP stacks from a practical embedded perspective
• Prior work or experience with applied cryptography and embedded systems security

Team Description:

At Neuralink, we're engineering the future of automated surgeries, focusing on the safe and effective implantation of our groundbreaking Neuralink implant. Our team — a cross-functional mix of roboticists, engineers from various disciplines, and medical professionals — collaborates on developing a surgical flow from first principles. In this critical role, you'll straddle the cutting-edge worlds of robotics, software, and neuroscience.

Job Description and Responsibilities:

This is a new and foundational role for our team that will allow you to create new embedded systems from scratch while challenging and refining the old. As a Firmware Engineer, your responsibilities will encompass:

• Developing and optimizing embedded software for robotic surgery applications
• Streamlining our codebase by refining and, when necessary, retiring legacy embedded software
• Rigorous testing and validation of software systems to meet the highest safety and reliability standards
• Participating in peer code reviews
• Writing drivers and applications to extend the functionality of our robotics
• Specifying hardware and software choices as we develop future hardware platforms
• Sharing your findings and progress with the team in a collaborative environment

Required Qualifications:

• Demonstrated track record of success in a science or engineering field, evidenced by outstanding projects, innovations, or advanced problem-solving
• Proven experience in software development, preferably with exposure to embedded systems

Preferred Qualifications:

Embedded Software Development:

• 2+ years of experience with embedded systems
• Proficient with common communication protocols (SPI, UART, I2C, etc.)
• Comfortable/working knowledge of more advanced protocols such as PCIe, MIPI CSI/DSI, USB, and 802.3
• Proficient in at least one embedded language such as C, C++, or Rust
• Proficient with embedded toolchains and workflow
• Experience building and bringing-up MCUs or FPGAs
• Experience with embedded stacks for ARM cores
• Experience developing on embedded Linux platforms
• Experience with embedded Linux kernel configuration and device tree setup
• Experience with kernel driver development
• Experience with ARM bootloaders
• Experience coding drivers for actuators and sensors
• Experience with high speed data acquisition and processing

Electrical Engineering:

• Foundational understanding of MCU architectures and peripheral integration
• Solid knowledge in electrical engineering and DSP
• Ability to interpret electrical schematics and datasheets, along with proficiency in using lab equipment

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

• Micro-architecture design and RTL implementation of: 
• Low-power digital signal processors
• Low-power general-purpose hardware accelerators
• Low-power graphics processing units
• Low-power radio MAC/PHY
• Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
• Complex system modeling for energy and performance benchmarks
• Workload analysis and modeling
• Energy/performance profiling and analysis
• Leveraging architecture-level design trade-offs with process technology and workload type
• Balancing cost and performance under manufacturing process variation 
• Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• Experience designing and implementing embedded software in C or Rust
• Expertise in SystemVerilog, C/C++, Python
• Experience designing and implementing  emulation models, transactors, and test environments to replicate hardware behavior
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Job Summary

We are seeking a talented Signal Processing Engineer to design, develop, and optimize advanced digital signal processing (DSP) algorithms for on-chip and embedded implementation. In this role, you will create efficient, hardware-friendly algorithms that run directly on custom SoCs, enabling real-time processing with constraints on power, latency, area, and throughput. You will collaborate closely with the SoC, Firmware, and Machine Learning teams to translate high-level signal processing needs into production-ready solutions.

Key Responsibilities

• Design and develop signal processing algorithms for sensing neural activity in the cortex (e.g. spike detection), monitoring cortical electrode health, and more.
• Design and develop numerical algorithms, such as custom data compression to increase radio throughput.
• Develop fixed-point or quantized versions of algorithms optimized for constrained hardware.
• Implement and verify algorithms in high-level languages and transition them to hardware-friendly representations.
• Perform algorithm-to-architecture mapping: analyze trade-offs between accuracy, latency, power, and resource utilization on the SoCs.
• Collaborate with the digital design team to define micro-architectures for custom on-chip processing pipelines, including dataflow, pipelining, and parallelization.

Required Qualifications

• Education: BS, MS or PhD in Electrical Engineering, Computer Engineering, Signal Processing, or a related field.
• Experience: 3+ years in digital signal processing algorithm development or real-world products, with a focus on embedded or hardware-constrained implementations.
• Fluent in signal processing fundamentals (both analog and digital) and strong numerical capabilities.
• Familiarity with fixed-point arithmetic, quantization effects, and numerical precision trade-offs.
• Proficiency in Python and C for algorithm prototyping and simulation.

Preferred Qualifications

• Hands-on experience with Verilog/VHDL, or transitioning algorithms to RTL.
• Experience with dedicated DSP cores or accelerators.
• Track record of optimizing for power/area/latency in resource-constrained environments.

Base Salary Range:

 $121,000 - $230,500

Team Description:

The Brain Interfaces Software Team is responsible for the end to end software stack that manages implant communication, verification, manufacturing and monitoring. We own client side SDKs and full-stack platforms that are used by various divisions within the company. We are looking for versatile engineers who are interested in architecting and implementing elegant software solutions and who thrive with the autonomy to propose creative approaches to problems. 

Neuralink strives to be a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Responsibilities:

As a Software Engineer on the Brain Interfaces Software Team, your responsibilities will encompass:

• Developing and improving Neuralink’s Implant and Charger SDK
• Maintaining Neuralink’s brain interface software and firmware build tooling
• Developing and improving Neuralink’s Implant manufacturing line acceptance software
• Maintaining Neuralink's Implant design control verification testing software
• Developing and improving Neuralink’s Implant recorder system
• Developing and improving Neuralink’s Implant monitoring system

Required Qualifications:

• Fluent in Python and C or Rust (don’t get hung up on this—being an exceptional software engineer matters above all)
• Experience (and comfortable) with the Linux/Unix systems and command line
• Evidence of exceptional ability in engineering, mathematics, or computer science
• Strong understanding of engineering first principles
• Strong intuition for what matters in a production system (vs. research-grade)

Preferred Qualifications:

• Prior experience developing software for safety-critical systems
  

About You:

• You find large challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver. You may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that what matters is delivering reliable solutions. (Our ultimate aim is to help people; the “right” solution doesn’t always achieve that)
• You are mission-driven and goal-oriented in your approach to solving problems
• You feel a sense of urgency to get things done sooner rather than later—because there is so much we, as people, can contribute to the world and accomplish in this life, it’s a shame to waste time
• You are resourceful, flexible, and adaptable; no task is too big or too small

Team Description: 

The Infrastructure Team builds the foundation that enables the company to operate safely, robustly, and move at light-speed. We run a mixture of cloud-based and on-prem systems and have a user base spanning from highly technically proficient engineers to non-technical scientists and doctors; but all of them need solid systems, rugged networking, and bullet-proof software to do their jobs. This role will integrate tightly with teams across the company, and span all layers of the work environment stack, from deployment of physical hardware on the manufacturing line, to custom tooling to stream neural recordings from implants.

Tech Stack:

• Rust, Python
• Terraform
• Bazel and Nix
• Kubernetes
• GitLab CI
• AWS
• Ubuntu, Fedora

Focus:

• Developing the foundations for teams to build the software and systems required for record-breaking BCI experiences.
• Enhancing developer experience with robust tooling and build-system infrastructure.
• Building foundational infrastructure for HITL (hardware in the loop) testing across firmware, BCI, and robot teams.
• Ground-up infrastructure of on-premise solutions as well as cloud architecture.
• Foundational software engineering with a focus on serving internal software teams.

Qualifications: 

• Experience using IAC tools such as Terraform, Docker, Packer, Ansible, Cloud-Init, Kickstart.
• Working knowledge of compiled languages, ideally Rust, Go, or C/C++.
• Working knowledge of major cryptographic protocols and authentication schemes such as TLS, x509, 802.1x, U2F, SAML.
• Familiarity with modern Linux boot process, UEFI, TPM measured boot, Secure Boot, Systemd.
• Systems administration experience on Windows, macOS, and Linux.
• In-depth understanding of modern networking and common protocols.
• Ability to architect, build, and ship 0 to 1 infrastructure quickly and efficiently.

Team Description:

The Brain Interfaces Software Team is responsible for the end to end software stack that manages implant communication, verification, manufacturing and monitoring. We own client side SDKs and full-stack platforms that are used by various divisions within the company. We are looking for versatile engineers who are interested in architecting and implementing elegant software solutions and who thrive with the autonomy to propose creative approaches to problems. 

Neuralink strives to be a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

Job Responsibilities:

As a Software Engineer Intern on the Brain Interfaces Software Team, your responsibilities will encompass:

• Developing and improving Neuralink’s Implant and Charger SDK
• Maintaining Neuralink’s brain interface software and firmware build tooling
• Developing and improving Neuralink’s Implant manufacturing line acceptance software
• Maintaining Neuralink's Implant design control verification testing software
• Developing and improving Neuralink’s Implant recorder system
• Developing and improving Neuralink’s Implant monitoring system

Required Qualifications:

• Fluent in Python and C or Rust (don’t get hung up on this—being an exceptional software engineer matters above all)
• Experience (and comfortable) with the Linux/Unix systems and command line
• Evidence of exceptional ability in engineering, mathematics, or computer science
• Strong understanding of engineering first principles
• Strong intuition for what matters in a production system (vs. research-grade)

Preferred Qualifications:

• Prior experience developing software for safety-critical systems
  

About You:

• You find large challenges exciting and enjoy discovering and defining problems as much as solving them
• You deliver. You may enjoy thoughtful conversations about problems and perfecting design, but in the end, you know that what matters is delivering reliable solutions. (Our ultimate aim is to help people; the “right” solution doesn’t always achieve that)
• You are mission-driven and goal-oriented in your approach to solving problems
• You feel a sense of urgency to get things done sooner rather than later—because there is so much we, as people, can contribute to the world and accomplish in this life, it’s a shame to waste time
• You are resourceful, flexible, and adaptable; no task is too big or too small

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.

It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of a best-in-class family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from a diverse set of backgrounds and bring a broad range of skills and perspectives.   A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a principled and dynamic Lead Systems and Validation Engineer to drive end-to-end system validation for AI compute blade and rack platforms. This high-visibility role focuses on first silicon bring-up, system enablement, and post-silicon validation across hardware, firmware, and software domains. You will lead validation strategy, execution, and debug while collaborating closely with cross-functional engineering teams to deliver high-quality, industry-leading AI systems.

The Team

The Systems Validation team is responsible for enabling and validating Graphcore’s AI compute platforms from first silicon through production. The team works closely with system architects, firmware, silicon, and infrastructure teams to ensure system readiness, scalability, and quality at rack level.

Responsibilities and Duties

• Lead system enablement including first silicon bring-up and integration of firmware and platform components to meet system architecture specifications.
• Develop validation methodologies, lab hardware infrastructure, system software capabilities, and debug tools for blade and rack-level validation.
• Triage and debug issues across bring-up, post-silicon validation, and production phases ensuring timely resolution with high quality.
• Define and own validation test plans, develop test cases, and drive execution across domains such as CPU, GPU, memory, HBM, and IO.
• Drive innovation in validation through development of tools, scripts, and improved methodologies to enhance coverage, efficiency, and quality.
• Enable comprehensive system verification by integrating storage, networking, and infrastructure capabilities within lab environments.  
• Collaborate with multi-functional teams including system architecture, embedded software, hardware build, and ODM partners.    
• Provide technical leadership and mentorship, fostering engineering perfection and continuous improvement.

Candidate Profile

Essential:

• Strong analytical and problem-solving skills with high attention to detail.
• Extensive experience in system validation encompassing initial silicon integration and HW/FW/SW validation.  
• Strong understanding of industry-standard interfaces such as PCIe and CXL.
• Experience enabling storage and networking systems in lab environments for end-to-end validation.
• Deep knowledge of ARM or x86 architectures, SoC design, memory, RAS, and power management.
• Experience with system-level debug, operating systems, BIOS, and device drivers.
• Strong experience with Linux, Windows, and virtualization technologies (VMware, KVM, Hyper-V).
• Excellent communication, organization, and cross-functional collaboration skills.
• Ability to lead multiple workstreams and deliver under tight timelines.
• Experience in technical program management and driving validation initiatives.

Desirable:

• Master’s or PhD in Electrical Engineering, Computer Engineering, or related field.
• Demonstrated ability working on complex system validation and debug in data center or rack-scale environments.
• Experience designing or validating AI/ML rack-scale systems.
• Knowledge of hardware development best practices and industry standards.
• Familiarity with emerging AI and data center infrastructure technologies.
• Experience collaborating with ODM partners globally.

About us

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.

It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.

As part of the SoftBank Group, Graphcore is a member of a best-in-class family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.

Graphcore’s teams are drawn from a diverse group of backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.

Job Summary

We are seeking a senior validation lead engineer to lead at-scale rack validation efforts for next-generation AI hyperscale systems. This role focuses on post-silicon system validation across the full lifecycle, ensuring functional, electrical, and thermal performance meets product objectives. You will own end-to-end blade and rack validation including planning, development, execution, and debug while collaborating across firmware, systems, and hardware teams.

The Team

The Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms.

Responsibilities and Duties

• Lead post-silicon validation of AI compute blades and racks including test planning, development, and automation.
• Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness.
• Own execution against program achievements and report validation progress and risks.
• Triage test failures, collect debug data, and collaborate on root cause analysis.
• Track validation coverage and continuously improve test processes and infrastructure.
• Collaborate with ODM/JDM partners on validation and quality.
• Mentor engineers and drive engineering excellence.

Candidate Profile

Essential:

• Bachelor’s or Master’s degree or equivalent experience in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• Proven track record in system, rack, or embedded validation with leadership experience.
• Strong experience in large-scale hardware validation environments.
• Expertise in CPU/GPU, memory, IO, and firmware validation.
• Experience with Linux/server OS and automation using Python/Bash.
• Knowledge of IPMI, Redfish, PLDM.
• Experience with CI/CD pipelines and hardware interfaces.

Desirable:

• Experience in hyperscale environments.
• Familiarity with OpenBMC and processes for verifying firmware functionality.  
• Knowledge of firmware security and HIL testing.
• Experience with test management tools.

Graphcore is a globally recognized leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialized processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.   

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. 

About the Role

We are seeking a Storage Architect to design, evaluate, and optimize the high-performance storage architectures powering our AI data centers. In AI training and inference, keeping GPUs fed with data is one of the most critical challenges; even a slight I/O bottleneck can lead to massive inefficiencies. In this role, you will be our resident expert on solid-state storage, focusing heavily on NVMe SSDs, PCIe topologies, and the Linux storage stack. You will ensure our local and distributed storage tiers deliver the microsecond predictable latency and massive throughput required for large language model (LLM) checkpointing, massive datasets, and high-speed data loading pipelines.

RESPONSIBILITIES

• Hardware Qualification: Lead the evaluation, qualification, and lifecycle management of NVMe SSDs (e.g., E1.S, E3.S, U.2/U.3 form factors) from major vendors for use in high-density AI servers and AI Clusters.
• Architecture & Topology: Design and optimize local server storage topologies, managing PCIe lane distribution, minimizing NUMA node crossings, and ensuring optimal data paths between NVMe drives, CPUs, and GPUs.
• Performance Tuning: Conduct rigorous performance profiling and tuning of the Linux kernel storage stack, block layer, and file systems to maximize IOPS and bandwidth while minimizing tail latency (i.e., 99.99%).
• AI Workload Optimization: Optimize storage configurations specifically for AI workloads, including tuning for GPU direct storage to enable direct memory access between NVMe storage and GPU memory, bypassing the CPU.
• Telemetry & Automation: Drive telemetry strategy for the storage subsystem including SSD health monitoring (i.e., wear leveling, DWPD, thermals) and latency anomaly detection. Provide requirements and technical guidance to the automation team building test framework to characterize the storage subsystem in our AI Platforms. Additionally, manage firmware rollouts at scale.
• Troubleshooting: Act as the highest point of escalation for complex, storage-related performance degradation or hardware failures, utilizing tools like nvme-cli, fio, and PCIe analyzers.
• Vendor engagement:  Responsible for working closely with storage vendors, supply chain teams, and our Systems engineering team in the selection and proper deployment of storage components into our AI server fleet. 
• “Futures”:  As a storage architect you will be responsible for scoping the industry for new storage technologies that will give us an advantage on future AI Server designs.
• Storage Control and Dataplane Definition: Storage expert in charge of the definition and architecture of our external storage Data plane and Control plane solutions using leading vendor solutions such as Weka, VAST, Pure Storage, and others. 

REQUIREMENTS

• Bachelor’s, master’s degree or equivalent experience in Information Technology, Computer Science, Computer engineering, or a related field.
• 12+ years of hands-on experience in storage engineering and architecture and 5+ years supporting storage solutions on AI or Hyperscale Datacenters.
• Deep NVMe/PCIe Knowledge: Expert-level understanding of the NVMe protocol, PCIe architecture (Gen 5/Gen 6), NAND flash characteristics, and SSD controller behavior (garbage collection, wear leveling, write amplification).
• Linux Storage Stack: Deep operational knowledge of Linux internals, specifically the block layer, I/O schedulers, direct I/O, and modern local file systems (XFS, ext4, ZFS).
• Performance Profiling: Extensive hands-on experience with benchmarking and profiling tools such as fio, blktrace, iostat, and perf to simulate AI workloads and isolate bottlenecks.
• Scripting: Strong programming skills in Python, JSON, Bash or related scripting languages for building validation scripts, automation pipelines, and interacting with REST APIs.
• Root Cause Analysis: Proven track record of debugging complex hardware/software interactions, including kernel panics, PCIe bus errors, and SSD firmware bugs.
• Telemetry: Point of contact responsible for defining the telemetry sensors and rules to activate alerts in our Datacenter fleet monitoring frameworks.

DIFFERENTIATORS

• GPU Direct Storage (GDS): Experience implementing, testing, and troubleshooting GDS or similar technology for direct GPU-to-storage communication.
• NVMe over Fabrics (NVMe-oF): Experience designing or managing NVMe-oF (RoCEv2 or TCP) deployments to disaggregate storage without sacrificing local-NVMe performance.
• Storage Software Development: Experience with the Storage Performance Development Kit (SPDK) or developing user-space storage applications.
• Distributed AI File Systems: Familiarity with high-performance parallel file systems commonly used in AI/HPC clusters (e.g., Weka, VAST Data, Lustre, DAOS, or DDN).
• Emerging Tech: Knowledge of Compute Express Link (CXL) and its implications for future memory and storage tiering in AI servers.

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced AI HW Systems Engineering and Debug Lead to drive system-level debug and bring-up activities for Graphcore’s next-generation AI data center platforms. 

The successful candidate will lead complex debug efforts across hardware, firmware, and software layers for blade and rack-level systems. This role focuses on developing scalable debug strategies, improving debug throughput, and ensuring timely resolution of system-level issues throughout the product lifecycle. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption 

The Systems Engineering and Validation team ensures Graphcore’s AI compute platforms are fully validated, debugged, and ready for deployment in hyperscale data center environments. 

The team collaborates closely with silicon engineering, system architecture, firmware, operating system, and rack integration teams to identify and resolve system-level issues and drive improvements in validation and debug methodologies. 

Responsibilities and Duties 

• Own and develop AI systems debug methodology and system bring-up strategies for next-generation AI data center platforms. 

• Lead system-level debug and root cause analysis for issues identified during server rack validation, post-silicon validation, and production phases. 

• Drive complex debug efforts across silicon, hardware platforms, firmware, operating systems, and software stacks. 

• Manage and track technical issues, risks, and priorities to ensure program milestones are achieved. 

• Publish debug program indicators and metrics to identify roadblocks and improve debug throughput. 

• Coordinate cross-functional teams including system architecture, silicon, firmware, and validation teams to resolve system-level issues. 

• Lead development and integration of debug tools, scripts, and methodologies to improve debug efficiency. 

• Communicate program status, risks, and technical findings to engineering leadership and stakeholders. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related discipline. 

• 15+ years of experience working on complex systems engineering challenges involving HW/FW/SW debug in server or data center environments. 

• Proven experience leading validation and debug for board, blade, and rack-level hardware platforms. 

• Strong experience debugging OS, firmware, silicon, and hardware issues. 

• Understanding of industry-standard system buses such as PCIe and CXL and their software stacks. 

• Strong knowledge of ARM or x86 CPU architectures, SoC design, memory systems, and power management. 

• Experience with system architecture, validation strategies, and complex system debug methodologies. 

• Strong collaboration, communication, and cross-team coordination skills. 

Desirable 

• Experience designing or deploying AI/ML rack-scale systems. 

• Experience developing at-scale debug methodologies for hyperscale data center systems. 

• Familiarity with data center infrastructure and emerging AI hardware technologies. 

• Experience with rack integration testing and hyperscale deployment readiness. 

• Knowledge of automated validation frameworks, test analytics, and continuous validation practices. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Hardware Validation Manager to lead the validation of Graphcore hardware platforms from prototype through production release. This role is responsible for defining validation strategies, building and leading a high-performing validation engineering team, and ensuring our hardware products meet electrical, functional, and reliability targets across all development phases. 

The successful candidate will combine deep technical expertise in hardware validation with strong leadership, cross‑functional collaboration, and program execution to deliver high‑quality products at scale. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption 

The Hardware Validation team ensures Graphcore’s AI hardware platforms meet performance, quality, and reliability targets before production release. Working closely with silicon, board design, system architecture, firmware, and manufacturing teams, the group develops and executes validation strategies across development phases. 

The team plays a critical role in bridging design and production by identifying issues early, driving root cause analysis, and enabling robust, production‑ready hardware platforms. 

Responsibilities and Duties 

• Define and implement board and multi-board hardware validation plans across Proto, EVT, DVT, and PVT phases. 

• Develop and execute validation strategies covering electrical, functional, and system-level requirements. 

• Ensure validation coverage aligns with product specifications, customer requirements, and industry standards. 

• Drive root cause analysis and corrective actions for hardware validation failures. 

• Build, mentor, and manage a team of hardware validation engineers. 

• Collaborate with hardware design, silicon, firmware, and manufacturing teams across the product lifecycle. 

• Establish validation milestones and deliverables aligned with program schedules and product release goals. 

• Drive improvements in validation methodology, tooling, automation, and data analysis. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Electrical Engineering or related field. 

• 10+ years of experience in board-level hardware validation, system testing, or product validation. 

• 3+ years of experience leading engineering teams. 

• Strong understanding of hardware development lifecycle (Proto, EVT, DVT, PVT). 

• Experience with lab instrumentation such as oscilloscopes, spectrum analyzers, and power analyzers. 

• Proven track record delivering hardware products from prototype through production. 

• Strong analytical and problem-solving skills with experience driving root cause investigations. 

Desirable 

• Experience influencing validation requirements during architecture and schematic phases. 

• Experience embedding validation hooks and testability features into hardware designs. 

• Experience implementing automated hardware regression testing. 

• Familiarity with data pipelines, dashboards, and validation data analytics. 

• Experience validating multi-board systems and high-speed interfaces (PCIe, DDR, SerDes). 

• Experience working with power-dense or high-performance compute systems. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Principal Hardware Diagnostics Engineer to design and develop diagnostics software used to monitor hardware health and diagnose system-level issues across Graphcore’s AI infrastructure platforms. 

This role focuses on building diagnostics agents, tools, and analytics frameworks that enable engineers and automation systems to identify, isolate, and resolve hardware issues across blade-level servers and rack-scale clusters. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.    

The Systems Engineering and Platform Validation team ensures Graphcore’s AI compute platforms are reliable, diagnosable, and operationally robust at scale. 

The team collaborates with hardware engineering, firmware, cloud infrastructure, and automation teams to develop tools and frameworks that monitor system health, detect hardware failures, and accelerate root-cause analysis across AI clusters. 

Responsibilities and Duties 

• Design and develop automated hardware diagnostics solutions for blade-level servers and rack-scale AI systems. 

• Architect and implement diagnostic agents, monitoring tools, and analytics frameworks to track hardware telemetry. 

• Collaborate with hardware teams to integrate low-level diagnostic modules into monitoring systems. 

• Develop diagnostics tools capable of detecting hardware health conditions and isolating failures. 

• Create diagnostic modules used for internal validation and production data center operations. 

• Provide detailed hardware fault information to system engineers to accelerate troubleshooting. 

• Define remediation workflows and insights for hardware fault scenarios across nodes and clusters. 

• Collaborate with firmware, networking, and cloud platform teams to integrate diagnostics across the system stack. 

Candidate Profile 

Essential 

• Bachelor’s, Master’s, or PhD in Computer Science, Computer Engineering, or related discipline. 

• Strong software engineering experience in Python, C++, or C#. 

• Experience developing diagnostics or monitoring systems for hardware platforms. 

• Experience working with distributed systems or cloud infrastructure. 

• Strong knowledge of Linux environments and system-level diagnostics tools. 

• Experience collaborating with CM/ODM partners on manufacturing diagnostics and fault isolation. 

• Strong analytical and debugging skills. 

• Excellent communication and collaboration abilities. 

Desirable 

• Experience working with AI hardware platforms or accelerator-based computing systems. 

• Familiarity with hyperscale data center infrastructure. 

• Experience building cluster-level monitoring or diagnostics systems. 

• Experience interacting with internal or external customers during diagnostics solution development. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

Job Summary 

We are seeking an experienced Principal Security Firmware Engineer to design, implement, and validate security mechanisms within embedded firmware and low-level system software supporting Graphcore’s AI compute platforms. 

This role focuses on protecting hardware platforms through secure firmware architecture, trusted boot mechanisms, and secure firmware update frameworks while working closely with hardware, firmware, and security architecture teams. 

The Team 

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

The Firmware and Platform Security team is responsible for securing Graphcore’s AI infrastructure platforms across firmware and hardware interface layers. 

The team collaborates with silicon engineering, hardware design teams, firmware developers, and security architects to implement trusted boot chains, secure firmware update mechanisms, and hardware-rooted security capabilities. 

Responsibilities and Duties 

• Design and implement secure firmware architectures for embedded and hardware systems. 

• Develop secure boot, firmware authentication, hardware root of trust, and secure firmware update mechanisms. 

• Define threat models and security requirements for firmware components. 

• Develop and maintain secure embedded firmware using languages such as C, C++, and Rust. 

• Integrate cryptographic libraries and hardware security modules (HSM/TPM). 

• Implement protections against firmware tampering, side-channel attacks, fault injection, and reverse engineering. 

• Perform firmware security assessments, code reviews, and vulnerability analysis. 

• Conduct penetration testing, fuzz testing, and other security validation techniques. 

• Collaborate with hardware teams to integrate chip-level security features. 

• Ensure firmware implementations align with industry standards such as NIST, FIPS, and Secure Development Lifecycle practices. 

Candidate Profile 

Essential 

• Bachelor’s or Master’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related discipline. 

• 5–10+ years of experience in embedded systems or firmware development. 

• Strong programming experience in C and C++. 

• Deep understanding of secure boot architectures and trusted boot chains. 

• Strong knowledge of cryptographic protocols and secure firmware design practices. 

• Experience working with embedded operating systems such as FreeRTOS, Zephyr, or Linux. 

• Experience implementing secure firmware update systems and cryptographic key management. 

Desirable 

• Programming experience in Rust. 

• Experience integrating TPM or hardware security modules (HSM). 

• Experience with static analysis and security tools such as Coverity. 

• Knowledge of secure silicon architectures and trusted execution environments. 

• Experience contributing to open-source firmware security projects. 

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

About us 

Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. 

Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. 

This position is a senior technical engineer role.  The thermal engineer will work in a project team delivering complex AI data center hardware.  Primary responsibility is to ensure the overall product functionality and meet all applicable technical thermal specifications.  The engineer will be responsible for the overall thermal solution, creation of specifications, design review and qualification, and testing and validation.  This role involves deep understanding of thermal management principles, simulation, testing, and collaboration with cross-functional teams to deliver high-performance and reliable server cooling systems. 

Responsibilities: 
Expert in your chosen field, you’ll be responsible for designing, developing, modifying and evaluating the liquid cooling solutions focusing on direct liquid cooling (DLC).  As part of the technical function, you will be responsible in working with select ODM vendors to manage the product thermal specification, development schedule, meet various deliverables, resolve technical issues, and ensure product meets specification, cost and quality goals.  You will be responsible in guiding and directing ODM vendors to deliver thermal designs, implementation, monitor testing, review cost and review technical design information to provide clear directions to ODM.  In addition, you will also be working with third party vendors and suppliers to ensure product features are being achieved.  

REQUIREMENTS

• Bachelor’s, Master’s or Ph. D degrees in mechanical engineering.  Minimum of 10 years of server thermal design experience.  Experience needs to include thermal and acoustics, as it relates to server products.  Experience in system level thermal design focusing on DLC and cold plate cooling heatsink technology as well as system level control logic
• Understanding the basic foundations of thermal fluid dynamics and heat transfer.
• Ability to lead the design and development of liquid cooling solutions. This includes conceptualization, prototyping, simulation, validation, and optimization of heat sinks, cold plates, CDU/CDM, and other liquid cooling components.
• Ability to perform thermal simulations and analyses utilizing industry-standard software (e.g., FlowTherm, ANSYS, COMSOL) to analyze thermal behavior and optimize design for performance and efficiency.
• Ability to develop and execute test plans to validate thermal solutions, ensuring compliance with industry standards and performance goals.
• Experience working closely with system architects, chip and board designers, and software/firmware engineers to integrate liquid cooling solutions into server products.
• Understanding of microprocessor architecture and thermal profiles.
• Understanding of system level thermal design focusing on fan and heatsink technology.
• Experience with system level thermal and fan control algorithm.
• Experience effectively dealing with conflict.
• Communicates well verbally, in writing, and graphically.
• Ability to establish clear goals and formulate plans to achieve them.
• Good root-cause analysis and problem-solving skills.
• Works independently and as part of a team.
• Excited about technology and has the desire to learn new tasks and technologies.

DIFFERENTIATORS

We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.

Scope

Ambiq is seeking an Edge AI Firmware Engineer to build and optimize the embedded software stack that powers real-time, battery-powered on-device AI. You will develop Ambiq’s AI runtimes, performance-critical operator libraries, and profiling/debug tooling that enable customers to deploy efficient inference on resource-constrained devices.

While the cloud has been the default home for AI, the next frontier is distributing intelligence everywhere—directly onto real-world devices. Edge AI enables real-time responsiveness, stronger privacy, lower bandwidth cost, and reliable operation even without connectivity. This role helps accelerate the shift to on-device intelligence across a rapidly growing ecosystem of health and fitness wearables, smart glasses, industrial IoT, and always-on sensors.

You’ll work closely with platform, silicon, and applied ML teams—and directly with customers—to ensure our software extracts maximum performance and energy efficiency from Ambiq hardware while remaining easy to integrate into production embedded toolchains.

Responsibilities 

• Develop and support Ambiq’s embedded AI runtimes (HeliaRT—our fork/extension of TensorFlow Lite for Microcontrollers—and HeliaAOT) with focus on portability, correctness, performance, and usability.
• Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components.
• Build and maintain on-device profiling and performance analysis tools, including converting PMU counters into actionable insights.
• Drive improvements in latency, memory footprint, and energy (e.g., joules/inference) through compute/bandwidth and memory-hierarchy analysis.
• Develop benchmark harnesses, microbenchmarks, and regression tests to ensure numerical correctness and prevent performance regressions.
• Enable seamless customer integration across embedded environments and toolchains (bare metal, FreeRTOS, Zephyr).
• Improve memory planning/runtime efficiency and manage upstream/fork health; publish and maintain customer-facing assets (docs, guides, examples, benchmarks).

Qualifications 

• BS in Electrical/Computer Engineering, Computer Science, or related field + 5+ years relevant experience (or equivalent practical experience). MS is a plus, especially in embedded systems, compilers, computer architecture, or ML systems.
• Strong experience designing, developing, and testing embedded software in C/C++.
• Strong debugging discipline with an emphasis on correctness, reproducibility, and performance regression prevention.
• Solid understanding of compute, memory, and bandwidth/cache effects on deterministic latency and energy efficiency in constrained systems.
• Ability to interpret hardware/software documentation (datasheets, reference manuals; schematics a plus).
• Proficiency with Git (or equivalent version control).
• Efficient use of AI-assisted development tools to improve productivity while maintaining engineering rigor.
• Experience with embedded development workflows: Arm toolchains, GDB + J-Link/SEGGER-class probes, and CMake/Make build systems.

Nice to have:

• Python for profiling/analysis tooling, automation, and developer utilities.
• Rust experience.
• Familiarity with TensorFlow Lite for Microcontrollers (or similar embedded inference runtimes).
• Experience optimizing for embedded acceleration targets (e.g., DSP, vector extensions, NPU).
• Familiarity with CMSIS-NN, CMSIS-DSP, and/or Vela (or similar).
• Working knowledge of quantized inference (e.g., int8, per-channel) and embedded debugging implications.
• Packaging/integration (e.g., CMSIS-Pack/CPM.cmake) and/or lab measurement experience (power/debug with basic bench tools).

Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

We want people who are passionate about optimizing and troubleshooting data center hardware at mega-scale so our customers don’t have to worry!

Reporting to the Manager of Infra::Machines::Design, you will support sustaining engineering efforts for the hardware infrastructure of the DigitalOcean server fleet. The ideal candidate will be eager to face new challenges as DigitalOcean continues to scale its data center footprint and infrastructure cloud capacity and explore new technologies and capabilities to bring to our customers, providing top-tier support for our hardware and firmware in the DO fleet.

What You’ll Be Doing:

• Act a member of the Sustaining Engineering team in the Infra::Machines::Design Organization
• Support server hardware, cabling, and networking hardware throughout its operational lifecycle 
• Monitor the #machines channel and MACHINES JIRA project for issues and drive them to resolution
• Participate in 24/7 on-call rotation with other members of the team
• Act as Tier 2 escalation for Datacenter Operations (DCOPS) and Cloud Operations (CloudOps) regarding hardware and firmware components
• Develop and maintain standards and practices for DigitalOcean hardware operations 
• Work closely with the Qualification team, Firmware team, Fleet Lifecycle Engineering team (FLE), Foresight team, and Infrastructure Services team to resolve issues in tooling, firmware packages, hardware components, and other operational concerns
• Help with development of tooling and associated runbooks to address gaps in operational capabilities around hardware and firmware operations
• Coordinate with Ops teams on monitoring thresholds, failure modes and alerting
• Assist in troubleshooting cause of failures and work to prevent them in the future 
• Raise the quality bar in the delivery of our cloud infrastructure by identifying industry best practices and working to adopt them

What We’ll Expect From You:

• Technical Degree (BS Computer Science/Engineering) or equivalent practical experience 
• Hands-on experience operating a cloud infrastructure at mid-tier scale or better
• An in-depth understanding of server hardware, firmware, and infrastructure
• Strong knowledge in troubleshooting techniques, Python and BASH
• Extra points for JTAG debugging / Firmware troubleshooting / Wire sniffing experience
• Clear communication and collaboration across key stakeholders 
• An insatiable passion for constant improvement

Compensation Range: 

• $83,000 - $104,000

*This is a remote role

JR: 2026-7565

#LI-Remote

We want people who are passionate about optimizing and troubleshooting data center hardware at mega-scale so our customers don’t have to worry!

Reporting to the Manager of Infra Machines Design, you will act as the team lead for sustaining engineering efforts for the hardware infrastructure of the DigitalOcean server fleet. The ideal candidate will be eager to face new challenges as DigitalOcean continues to scale its data center footprint and infrastructure cloud capacity and explore new technologies and capabilities to bring to our customers, providing top-tier support for our hardware and firmware in the DO fleet.

What You’ll Be Doing:

• Act as technical lead for the Sustaining Engineering team in the Infra::Machines::Design Organization
• Support server hardware, cabling, and networking hardware throughout its operational lifecycle Monitor the #machines channel and MACHINES JIRA project for issues and drive them to resolution
• Participate in 24/7 on-call rotation with other members of the team
• Act as Tier 2 escalation for Datacenter Operations (DCOPS) and Cloud Operations (CloudOps) regarding hardware and firmware components
• Develop and maintain standards and practices for DigitalOcean hardware operations
• Work closely with the Qualification team, Firmware team, Fleet Lifecycle Engineering team (FLE), Foresight team, and Infrastructure Services team to resolve issues in tooling, firmware packages, hardware components, and other operational concerns
• Liase with DCOPS teams to develop, deliver, and support hardware-related runbooks
• Liase with vendor support teams regarding hardware and firmware issues and drive issues to resolution Identify gaps in tooling and operational processes and engage appropriate peer teams to close gaps
• Help with development of tooling and associated runbooks to address gaps in operational capabilities around hardware and firmware operationsCoordinate with Ops teams on monitoring thresholds, failure modes and alerting
• Assist in troubleshooting cause of failures and work to prevent them in the future Raise the quality bar in the delivery of our cloud infrastructure by identifying industry best practices and working to adopt them

What We’ll Expect From You:

• Technical Degree (BS Computer Science/Engineering) or equivalent practical experience
• Hands-on experience operating a cloud infrastructure at mid-tier scale or better
• An in-depth understanding of server hardware, firmware, and infrastructure
• Strong knowledge in troubleshooting techniques, Python and BASHExtra points for JTAG debugging / Firmware troubleshooting / Wire sniffing experience
• Clear communication and collaboration across key stakeholders An insatiable passion for constant improvement

Compensation Range: 

• $107,000 - $134,000

*This is a remote role

JR: 2026-7601

#LI-Remote

We want people who are passionate about optimizing and troubleshooting data center hardware at mega-scale so our customers don’t have to worry!

We are looking for an entry-level hardware technologist with experience testing and deploying firmware to server hardware at scale. Reporting to the Manager of Infra::Machines::Design, the Firmware Qualification Engineer will qualify and deploy firmware packages across DigitalOcean products and components and join a team of engineers who have already paved the way for the many tens of thousands of servers in our infrastructure. The ideal candidate will be eager to face new challenges as DigitalOcean continues to scale its data center footprint and explore new technologies to bring to our customers.

What You’ll Be Doing:

• Work with vendors and internal peer teams on qualifying, onboarding, and delivering new firmware to the DigitalOcean ecosystem
• Act as Tier 3 escalation on-call for triage, investigation, and resolution of system firmware issues in the DigitalOcean fleet (both customer-facing and internal)
• Participate in 24/7 on-call rotation with other members of the teamImprove existing firmware and hardware configuration automation/validation, for both hardware platforms and components (such as NIC, Storage and BMC)
• Engage with hardware vendors about new automation features and existing bugsHelp with development of tooling and associated runbooks to address gaps in operational capabilities around hardware and firmware operations
• Coordinate with Ops teams on monitoring thresholds, failure modes and alertingAssist in troubleshooting causes of failures and work to prevent them in the future 
• Raise the quality bar in the delivery of our cloud infrastructure by identifying industry best practices and working to adopt them

What We’ll Expect From You:

• Technical Degree (BS Computer Science/Engineering) or equivalent practical experience
• Strong understanding of x86 server hardware architecture and subsystems.
• Ideally, you’ve worked with non-x86 hardware too!Demonstrated professional proficiency in configuration management best-practices (we use Ansible and Chef)
• Experience automating server firmware components at large-scale using industry-standard tooling (Redfish, IPMI, etc) including a deep understanding of benchmarking, automating test frameworks, and process automation in general
• Practical knowledge of PXE boot, UEFI, Linux/OS boot, AMI/OEM BIOS distributions, OpenBMC/AMI/OEM BMC implementations, RAID and other storage resiliency technologies, and the full Network stack- from NIC firmware to TCP/IPAdept at Linux (or Unix) operating systems. You’ll be spending a lot of time working in one!
• Comfortable with version control systems (we use Git) and proficient in at least one programming language (such as Python or Go) Ability to participate in 24/7 on-call rotation with other members of the team
• Excellent communication skills, both within the team and with the broader company
• Have an insatiable passion for hardware, both new and old 

Compensation Range: 

• $83,000 - $104,000

*This is a remote role

JR: 2026-7606

#LI-Remote

Job Summary

We're looking for an experienced staff electrical engineer to own the electronics EMI/EMC design and test strategy as well as RF communication subsystems for the Apollo humanoid robot. We are primarily interested in candidates who have developed and released products to the market in robotics, automotive, medical, personal electronics, or enterprise spaces. In this job role, you will own the strategy for requirements, design, and testing of RF, EMI, and EMC for the electrical systems in and around Apollo.

Responsibilities

• Develop and execute comprehensive validation and test plans, design necessary test fixtures, and execute rigorous testing to confirm compliance with performance specifications and regulatory standards (e.g., FCC, CE, UL).
• Own architecture and component selection for RF communication subsystems.
• Collaborate with leadership, program management, and cross-functional teams to plan and execute company strategy.
• Innovate by bringing new core technologies, test practices, and processes into electrical engineering developments.
• Define, simulate, and verify electronics and electrical system requirements.
• Design, simulate, implement, and test multi-layer mixed signal PCBAs.
• Rapid prototyping of electrical systems at both system and board levels.
• Generate design documentation such as schematics, block diagrams, test plans and procedures, fabrication and assembly drawings.
• Design hardware to meet functional safety requirements, implementing redundant systems, fail-safe mechanisms, and diagnostic features to meet or exceed industry safety standards.
• Conduct performance benchmarking and power analysis to optimize the hardware for maximum efficiency and thermal management.
• Participate in the debugging and root cause analysis related to hardware and software defect resolution.
• Own the entire lifecycle of electronics and electrical systems from initial concept and architecture definition through design, prototyping, validation, production release, change requests, and ongoing support.
• Mentor junior and senior engineers.
• Manage 3rd party relationships with vendors, contract manufacturers, and external design services.

Qualifications

• Bachelors, Masters, or PhD degree (or equivalent) in Electrical Engineering or related field.
• 8+ years of experience in electronics development.
• Demonstrated experience taking a product through FCC (Part 15b) and CE radiated and conducted emissions testing.
• Experience with 47 CFR 15.109 and IEC 61000-6 series standards.
• Experience with RF module selection and integration, particularly for 2x2 (or 4x4) Triband Wifi (5, 6, 6E, 7), high-throughput/data rate wifi systems, mobile device RF design, cellular 5G (carrier and private).
• Experience with wifi drivers for IEEE 802.11.
• Experience with antenna integration. Can inform on antenna selection or design, antenna placement, and interaction of antennas and surrounding materials.
• Experience with RF system performance optimization (mixed HW / SW / FW configuration).
• Excellent communication (verbal & written); will be expected to develop detailed build assembly instructions and diagrams.
• Excellent problem-solving and hardware debugging skills.
• Hands-on experience with prototyping and testing, including the use of lab equipment.
• Experience with robotics or designing electronics for lightweight, space-constrained systems is a significant plus.
• Nice-to-have: RF firmware/software experience, Nvidia Orin NX, Nvidia Orin AGX, Mobile robotics experience is a plus (antennas on robot vacuums or industrial AMRs), Intel Wi-Fi 6 AX201.

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate

JOB SUMMARY

We are seeking a Staff Test Engineer – Actuation to own the design validation and NPI test process for Apptronik's custom actuator systems. This is a hands-on, multi-disciplinary role spanning mechanical, electrical, firmware, and software testing — requiring someone who can independently drive actuator characterization and validation from initial bringup through design verification, and build the test methods and automation that transfer to test ops as programs move into production.

You will design and execute actuator test campaigns, develop robust bringup and calibration workflows, diagnose hardware issues across the full electromechanical stack, and deliver validated, well-documented test processes that are ready for handoff. You will work closely with mechanical, electrical, firmware, and controls engineers — connecting test data to root-cause analysis and hardware design improvements.

KEY RESPONSIBILITIES

• Actuator Bringup & Calibration: Lead the bringup process for new actuator hardware — including firmware deployment, motor and encoder calibration, and functional verification. Develop documented, repeatable procedures that can be transferred to test ops for production use.
• Design Validation Testing: Plan and execute design validation campaigns to characterize actuator performance across the operating envelope. Tests span mechanical (e.g., efficiency, stiffness, backlash, life), electrical (e.g., peak current, thermal limits, drive performance), and system-level (e.g., positional accuracy, off-axis loading, effort production) domains.
• Test Method Development for Production: Design and validate the production test methods used during NPI — including test scripts, post-processing, pass/fail criteria, and operator documentation — then hand off to the test ops team with the tooling and training needed to run them at scale.
• Test Automation & Data Infrastructure: Build Python-based test automation, data pipelines, and analysis tools that enable repeatable, scalable validation across multiple actuator types and hardware revisions.
• Test Equipment Operation: Operate and configure dynamometer, benchtop, and custom test setups. Manage fixture configurations and load motor modes across different actuator and gearbox variants.
• Cross-Stack Root-Cause Analysis: Diagnose actuator performance issues spanning firmware, electrical, and mechanical domains using structured, data-driven reasoning. Provide clear, actionable feedback to design teams.
• System Identification: Apply system identification techniques to characterize actuator dynamics — including inertia, friction, bandwidth, and torque constant — providing data that supports both hardware validation and simulation fidelity.
• Collaboration & Reporting: Work closely with mechanical, electrical, firmware, and controls engineers. Communicate test results, failure modes, and recommendations clearly to engineering and program leadership.

SKILLS AND REQUIREMENTS

Required Qualifications

• Direct hands-on experience testing and characterizing actuators, motors, or gearboxes — including operation of dynamometer or motor test stand systems.
• Experience with motor bringup and calibration workflows, with enough firmware and electrical fluency to diagnose calibration and drive faults independently.
• Strong cross-disciplinary debugging ability across mechanical, electrical, and firmware domains.
• Proficiency writing production-grade Python for test automation, data analysis, and post-processing.
• Demonstrated experience designing test methods and procedures — including pass/fail criteria and handoff documentation — not just executing pre-written scripts.
• Ability to read and interpret electrical schematics, mechanical drawings, and motor datasheets.
• Experience working in multi-disciplinary hardware teams with fast iteration cycles.
• Comfortable operating at staff level: leading technical workstreams, influencing engineering decisions with data, and mentoring others.

Preferred Qualifications

• Experience with humanoid or legged robot actuator systems.
• Familiarity with thermal modeling and thermal test methods for electric motor systems.
• Knowledge of motor drive electronics, power electronics, and power stage design margins.
• System identification background: frequency-domain analysis, bandwidth measurement, and dynamic model extraction.
• Experience transitioning test methods from R&D into production or manufacturing environments.
• Simulation experience (MuJoCo, Isaac Sim/Lab, etc.) and sim-to-real validation workflows.
• Docker, scripting, or infrastructure tooling for test automation at scale.

EDUCATION AND/OR EXPERIENCE

• BS in Mechanical Engineering, Electrical Engineering, Robotics, Computer Science, or related field + 6 years of relevant experience, OR
• MS in related field + 4 years of relevant experience, OR
• PhD in related field + 2 years of relevant experience.

Candidates with non-traditional backgrounds who can demonstrate equivalent hands-on experience with actuator testing and robotic hardware bringup are strongly encouraged to apply.

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer.
• Must be able to lift 15 pounds at times.
• Vision to read printed materials and a computer screen.
• Hearing and speech to communicate.

Austin is home to Optiver’s hardware research, development, and manufacturing group. We build some of the world’s most competitive trading hardware—high-speed, high-density systems that push the limits of performance, reliability, and manufacturability.

We’re growing fast and looking for a Manufacturing Test Engineer focused on PCBA test development and deployment. You’ll own board-level test solutions from early prototypes through volume production—building fixtures, developing automation, driving debug, and partnering closely with contract manufacturers and our internal EE/ME/FPGA/firmware teams.

We’re a small, highly technical team, and this role comes with real autonomy: you’ll have the runway to improve how we do test, raise the bar on factory readiness, and build scalable processes as our hardware footprint grows.

Who we are

Optiver is a tech-driven trading firm and leading global market maker. As one of the oldest market making institutions, we are a trusted partner of 70+ exchanges across the globe. Our mission is to constantly improve the market by injecting liquidity, providing accurate pricing, increasing transparency and acting as a stabilizing force no matter the market conditions. With a focus on continuous improvement, we participate in the safeguarding of healthy and efficient markets for everyone who participates.

Based in ‘The Domain’ neighborhood, Optiver’s Austin office serves as the firm’s innovation nucleus, with a strong focus on quantitative research, software and hardware engineering initiatives. With tech innovation an integral part of our core business, the booming city proved an ideal backdrop for our heavy investment into machine learning, research infrastructure and big data computing. What’s more, with world-class music, food and art scenes, as well as countless scenic outdoor activities, the quality of life for Austin Optiverians is second to none.

What you’ll do

• Own PCBA manufacturing test strategy across the product lifecycle:
• EVT/DVT/PVT → ramp → sustaining
• coverage definition, limits/thresholds, logging, and yield monitoring
• Design and build PCBA test fixtures spanning:
• ICT & Functional verification test (FVT)
• Burn-in / reliability screening
• Final assembly tests (FATP)
• System interoperability testing
• Develop automated test software with strong emphasis on Python scripting, maintainability, and scalability
• Partner with contract manufacturers to deploy tests on the line, train vendor teams, and drive continuous improvement.
• Drive DFT/DFM feedback into design reviews with EE and ME teams
• Define and maintain test documentation:
• Test plans, work instructions, golden unit strategy, calibration/maintenance procedures, and acceptance criteria.
• Use modern tooling (including AI-assisted workflows where helpful) to speed up debug, log triage, and documentation—without compromising repeatability and traceability.
• Travel periodically to supplier sites to support NPI builds, line bring-up, and ramp

Who you are

Requirements

• BS in Electrical Engineering, Computer Engineering, or related discipline.
• 3+ years of industry experience
• Strong Python skills: automation, hardware I/O, parsing logs, data analysis, packaging/CI practices.
• Ability to understand register maps and leverage HALs for creation of test scripts
• Proficient ECAD skills to develop schematics and oversee layout work: Altium, Mentor Graphics, Cadence or equivalent.
• Hands-on experience developing and deploying manufacturing PCBA tests in a production environment.
• Comfortable with hardware debug using scopes, DMMs, logic analyzers, protocol analyzers; strong troubleshooting instincts.
• Experience working with contract manufacturers and external vendor engineering teams, including clear communication and escalation management.

Nice to have

• Familiarity with FPGA prototyping and basic RTL concepts (enough to support debug/bring-up and test hooks).
• Familiarity with C and/or C++ for embedded firmware development
• Experience with high-speed digital board debug (clocking, SERDES links, power sequencing, SI/PI-related failure modes).
• Solidworks familiarity.

What you’ll get:

• Work alongside best-in-class professionals from over 40 different countries.
• Performance based bonus structure that is unmatched anywhere in the industry. We combine our profits across desks, teams and offices into a global profit pool fostering a truly collaborative environment to work in.
• Ownership over initiatives that directly solve business problems.  

Alongside this you will get great other benefits such as 25 paid vacation days and market holidays, fully paid health insurance, daily breakfast and lunch, training opportunities, 401(k) match up to 50% and charitable match opportunities, regular social events and clubs, and many more.

At Optiver, we are committed to creating a diverse and inclusive environment of mutual respect. Optiver recruits, employs, trains, compensates and promotes regardless of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics. 

JOB SUMMARY

We are seeking a Firmware Engineer with an interest in developing software for Battery Management Systems (BMS), robot communications, and sensing in robotic systems.

In this role, you will be responsible for the design, implementation, optimization, and testing of BMS firmware, robot communication systems, and real-time feedback control systems. You will also support hardware bring-up activities, develop and execute Hardware-in-the-Loop (HIL) and Software-in-the-Loop (SIL) tests, and contribute to system integration, validation, and debugging as embedded devices come online.

These embedded systems are core components that enable robots, including humanoids and mobile manipulators, to perform meaningful work across a wide range of applications.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

• Collaborate with systems, electrical, mechanical, and software engineers to develop the next generation of robotic platforms
• Lead cradle-to-grave development of Battery Management Systems (BMS), robot communications firmware, and sensing systems, including design validation
• Develop and execute Hardware-in-the-Loop (HIL) and Software-in-the-Loop (SIL) testing to validate system performance and reliability
• Design and implement fault detection, fault injection, and recovery mechanisms for safety-critical systems
• Manage over-the-air (OTA) firmware updates for embedded systems deployed on robotic platforms
• Partner with cross-functional engineering teams to bring up robot power distribution and sensing systems from prototype through production

SKILLS AND REQUIREMENTS

• Strong fundamentals in microcontrollers and battery systems
• Knowledge of real-time operating systems (RTOS) and hands-on experience working with an RTOS
• Understanding of distributed computing, multithreaded, and multi-process system design and debugging
• Experience with industrial control systems, industrial robotics, or process automation
• Experience developing in C and C++ for TI C2000 microcontrollers
• Proficiency in C/C++ and Linux; familiarity with Python, Docker, and Git
• Experience working in Agile teams, including participation in sprint planning, design reviews, and code reviews
• Strong hardware debugging skills using tools such as oscilloscopes and logic analyzers
• Ability to read and interpret electrical schematics (Altium Designer preferred) and hardware datasheets
• Experience with embedded communication protocols such as SPI, EtherCAT, Ethernet, UART, RS485, and CAN
• Familiarity with safety-critical embedded system design standards (e.g., ANSI/RIA R15.06, MISRA)
• Experience managing firmware deployments for fielded products

EDUCATION and/or EXPERIENCE

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
• Minimum of 1 year of relevant industry experience (excluding academic training) developing production-grade embedded software

PHYSICAL REQUIREMENTS 

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate

Job Summary

We're looking for experienced senior and junior electrical engineers to drive our electronics developments for the end effectors of the Apollo humanoid robot. We are primarily interested in candidates who have developed electronics for robotic end effectors, prosthetics, and wearables. In this job role, you will own electronic systems from ideation through design, testing, and into mass production. 

Responsibilities

• Own the development of complex electronic components and sub-systems.
• Design, simulate, implement, and test multi-layer mixed signal PCBAs and wiring harnesses.
• Rapid prototyping of electrical systems at both system and board levels.
• Simulate and verify electronics and electrical system requirements.
• Generate design documentation such as schematics, block diagrams, test plans and procedures, fabrication and assembly drawings.
• Collaborate closely with cross-functional teams, including software, mechanical, thermal, systems engineers, and manufacturing. 
• Conduct performance benchmarking and power analysis to optimize the hardware for maximum efficiency and thermal management.
• Develop and execute comprehensive validation and test plans, design necessary test fixtures, and execute rigorous testing to confirm compliance with performance specifications and regulatory standards (e.g., FCC, CE, UL).
• Participate in the debugging and root cause analysis related to hardware and software defect resolution.
• Drive excellence in EMI/EMC/SI/PI and DFM/DFA.
• Own the entire lifecycle of electronics and electrical systems from initial concept and architecture definition through design, prototyping, validation, production release, change requests, and ongoing support.
• Manage 3rd party relationships with vendors, contract manufacturers, and external design services.
• Act as a mentor within the electrical engineering team, guiding junior engineers on best practices for hardware design, documentation, and troubleshooting.

Qualifications

• Bachelors, Masters, or PhD degree (or equivalent) in Electrical Engineering or related field.
• 4+ years of experience in electronics development.
• Preferred experience with end effectors/end of arm tooling (EOAT), prosthetics, wearables, motor drives, firmware, communication protocols (Ethernet, EtherCAT, CAN, etc.), and wiring harnesses.
• Experience with product lifecycle management and PLM systems such as Arena.
• Competent in CAD tools including Altium or similar tools.
• Proven experience designing, prototyping, and debugging PCB/PCBAs as well as interfacing with manufacturing groups during release/build.
• Extensive experience with electronics lab tools and simulation tools (ex: LTSpice, PSpice).
• Excellent communication (verbal & written); will be expected to develop detailed build assembly instructions and diagrams.
• Excellent problem-solving and hardware debugging skills.
• Hands-on experience with prototyping and testing, including the use of lab equipment.
• Experience with robotics or designing electronics for lightweight, space-constrained systems is a significant plus.
• Nice to have - subject matter expertise in the following areas: power electronics, battery and charger development, high-speed digital or compute carrier board design, functional safety, compliance, or DFx.

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate 

JOB SUMMARY

As a Senior Hardware Test Engineer - Actuation, you will own the validation infrastructure for the robotic actuation systems that power Apptronik’s humanoid robots. This includes defining how actuators are tested, validated, and qualified before they are integrated into the robot and deployed to production.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES:

Actuation Test Ownership 

• Serve as the technical owner for manufacturing validation of robot actuators ● Define test strategies for servo-driven electromechanical systems, including: ○ Calibration and alignment
  • Functional validation
  • Performance characterization
  • Fault detection and failure analysis 

• Ensure test coverage supports product reliability and manufacturability Test System Architecture 
• Define the architecture and requirements for actuator test systems and fixtures ● Work with internal software teams to translate test requirements into automated test software 
• Specify instrumentation and interfaces including:
  • Servo drives and motor controllers
  • EtherCAT motion networks
  • Position, torque, current, temperature, and vibration sensors
  • Data acquisition systems 

• Lead integration and validation of automated test stations 

System Integration 

• Collaborate with controls, hardware, firmware, and systems teams to ensure testability is designed into actuator architectures 
• Support integration with manufacturing infrastructure including MES systems and production databases 
• Lead bring-up, debugging, and release of new test stations 

Production Ramp & Sustaining Engineering 

• Support transition from engineering builds to high-volume manufacturing ● Improve test processes for:
  • Yield
  • Cycle time
  • Reliability detection 

• Investigate and resolve production issues related to actuator performance ● Drive continuous improvement of test systems and validation methodologies 

Manufacturing Enablement 

• Develop and maintain:
  • Operator and technician training materials
  • Test equipment maintenance plans
  • Calibration procedures
  • Troubleshooting workflows
  • Create clear, production-ready documentation including test procedures, specifications, and system diagrams 

SKILLS AND REQUIREMENTS:

• Hands-on experience testing servo-driven actuators or motion systems ● Strong understanding of:
  • Servo control systems
  • Motor drives
  • Closed-loop feedback systems 

• Experience working with EtherCAT-based motion networks 
• Experience deploying automated test systems for hardware products ● Proven ability to lead complex technical projects from concept through production deployment
• Strong cross-functional collaboration with hardware, controls, and manufacturing teams ● Comfortable working in fast-paced robotics or hardware product environments

EDUCATION and/or EXPERIENCE 

• Bachelor’s degree in Electrical, Electronic, Mechanical Engineering, or relevant experience.
• 7+ years of experience in hardware test, manufacturing test, or system validation of electromechanical systems 

 PHYSICAL REQUIREMENTS  

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times 
• Vision to read printed materials and a computer screen 
• Hearing and speech to communicate

Perks:

• Competitive salary w/ benefits
• Highly motivating equity incentive package
• Flexible work hours policy
• Professional development opportunities
• Generous Paid Time Off (PTO)
• 401k plan

JOB SUMMARY

We are seeking an experienced Staff Systems Engineer to to own the end-to-end architecture, integration, and lifecycle of our next-generation dexterous humanoid robot hands. This role sits at the intersection of mechanical design, embedded systems, sensing, controls, and software integration. You will be responsible for defining system requirements, driving cross-functional execution, and ensuring that our humanoid hands meet performance, reliability, safety, and manufacturability targets. This is a high-impact role with ownership from concept through deployment. If you thrive in a fast-paced environment, with a successful track record of leading engineering design verification and product validation of electro-mechanical products, we’d love to speak with you. This position requires deep experience in robotics systems design, scaling complex systems, and the ability to balance technical vision with pragmatic execution.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

• Define and maintain system-level requirements and specifications.
• Develop and manage system architecture for dexterous humanoid hands (mechanical, electrical, sensing, actuation, firmware, controls).
• Drive interface definitions between hand hardware and higher-level robot control systems.
• Perform trade studies across performance, weight, cost, manufacturability, and reliability.
• Lead system integration efforts across hardware, firmware, and control stacks.
• Develop verification and validation (V&V) plans and test protocols.
• Define performance benchmarks (force control, grip strength, dexterity, tactile feedback, latency, thermal limits).
• Partner with mechanical, electrical, embedded, controls, AI, and manufacturing teams.
• Lead Systems requirement definition and integration across all hardware, sensing, compute, power management and distribution, EE architecture, capabilities, and operator interfaces.
• Design for real-time performance, fault tolerance, and reliability in a production environment
• Coordinate prototype builds and design reviews.
• Support supplier selection and qualification for actuators, sensors, and precision components.
• Support compliance, safety standards, and field deployment readiness.
• Design and develop requirements for real-time monitoring, data logging and remote diagnostics for production scale robot fleets
• Drive and support root cause failure analysis and fault recovery mechanism to enhance uptime and performance

SKILLS AND REQUIREMENTS

• Deep experience in designing and scaling complex hardware systems for real-time, high-DOF robotics applications.
• Strong understanding of Precision actuation (BLDC, tendon-driven systems, harmonic drives, etc.), Embedded systems and real-time control, Sensor integration (tactile, force/torque, encoders) and Closed-loop control systems
• Excellent cross-functional communication skills.
• Experience with dexterous manipulation systems or anthropomorphic robotic hands.
• Background in tactile sensing, impedance control, or compliant actuation.
• Experience taking robotic hardware from prototype to production.
• Knowledge of safety standards for collaborative robotics.
• Strong grasp of robotics architecture patterns, perception, sensing, actuation, kinematics and dynamics.
• Strong background in systems architecture, human machine interface design and experience with reliability engineering, including logging, telemetry, debugging, and automated test frameworks.
• Knowledge of communications protocols, perception (camera) systems, tactile (touch) sensing and their implementation and application in robotics and robotic manipulation
• Familiarity with human grasp taxonomies and principles of robotic manipulation
• Well-informed on state-of-the-art in Machine Learning and its applications in robotics controls and robotics manipulation
• Collaborative, communicative, and motivated by leading a tight knit team of expert engineers
• Adaptable and comfortable with ambiguity in an R&D focused environment

EDUCATION and/or EXPERIENCE

• Bachelor’s degree in engineering. Master’s and / or PhD degree in engineering preferred.
• 10+ years in systems and/or software engineering with at least 5+ in complex robotics systems or autonomous systems
• Demonstrated experience owning system-level architecture of robotic or mechatronic products.

PHYSICAL REQUIREMENTS 

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 15 pounds at times.
• Vision to read printed materials and a computer screen.
• Hearing and speech to communicate.

JOB SUMMARY

The Manufacturing Test Software Manager is responsible for leading and scaling the manufacturing test software function that supports production, bring-up, and validation of complex electromechanical systems. This role manages a team of senior test software engineers and is accountable for both technical execution and program delivery across multiple manufacturing lines and contract manufacturers. This position requires a hands-on technical leader with strong experience in manufacturing test software development, production-scale systems, and program
management—someone who can translate product and manufacturing requirements into robust, scalable, and well-planned test solutions while maintaining accountability, visibility, and execution rigor.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES:

People & Technical Leadership

• Lead, mentor, and develop a team of senior manufacturing test software engineers.
• Set clear technical and execution expectations, ensure accountability, and provide regular performance feedback.
• Establish coding standards, architectural best practices, and test coverage expectations for manufacturing environments.
• Balance hands-on technical guidance with delegation and team scalability.

Manufacturing Test Software Development

• Own the architecture, development, and maintenance of manufacturing test software used for:
  • Sub-assembly testing
  • System bring-up
  • Functional and acceptance testing
•  Factory automation and data capture
• Ensure test software is robust, scalable, maintainable, and production-ready.
• Drive improvements in test reliability, execution time, fault isolation, and data quality
• Partner closely with hardware, firmware, systems, and manufacturing teams to ensure end-to-end test coverage.

Program & Execution Management

• Own planning, prioritization, and execution of test software deliverables across multiple
  programs.
• Create and maintain roadmaps, schedules, and dependency tracking for test software
  initiatives.
• Proactively manage risks, resource constraints, and cross-team dependencies.
• Provide clear status reporting, metrics, and execution visibility to leadership.
• Ensure alignment between engineering development timelines and manufacturing ramp
  schedules.

Manufacturing & CM Engagement

• Support internal manufacturing and contract manufacturers (e.g., CM sites) with scalable, well-documented test solutions.
• Ensure test software deployments are repeatable, configurable, and easy to support on
  the factory floor.
• Drive improvements in manufacturing throughput, yield, and first-pass success through
  software-enabled testing.

Process & Continuous Improvement

• Define and improve processes around test software releases, validation, deployment, and change control.
• Promote automation, data-driven decision making, and continuous improvement across the test ecosystem.
• Ensure documentation, onboarding materials, and knowledge transfer are maintained at a high standard.\

 SKILLS AND REQUIREMENTS

• Strong background in manufacturing test software architecture, automation frameworks, and factory-scale systems.
• Proven experience in program management: planning, prioritization, scheduling, and cross-functional execution.
• Experience working closely with hardware, firmware, systems, and manufacturing teams.
• Ability to operate effectively in fast-paced, ambiguous, and scaling production environments.
• Strong communication skills, with the ability to align technical execution to business and manufacturing needs.

Preferred Qualifications

• Experience with robotics, electromechanical systems, or complex hardware products.
• Experience supporting contract manufacturers and multi-site production environments.
• Familiarity with manufacturing data systems, traceability, and yield analytics.
• Experience building or scaling test infrastructure during NPI and production ramps.
• Background in both hands-on engineering and leadership roles.

EDUCATION and/or EXPERIENCE:'

• 8+ years of experience in software development, with significant focus on manufacturing or production test systems.
• 3+ years of experience managing engineers, preferably in a manufacturing or test environment.

PHYSICAL REQUIREMENTS: 

• Prolonged periods of sitting at a desk and working on a computer
• Must be able to lift 25-45 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate
• International travel likely; passport highly desired
• Travel up to 50% may be required

We are looking for a Lead RTL Design Engineer to own microarchitecture definition and RTL implementation across the dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and standard peripheral IP (RiscV, NVM, I2S, I2C) integration. You will work from architecture spec through synthesis-ready RTL, collaborating with architects, microarchitects, DV leads, physical design, and firmware teams to tape out an industry leading power-efficient SoC.

This is a unique opportunity to be a part of a newly formed HW engineering org and have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.  Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities 

• Microarchitecture definition (core focus): Own the design and definition of processor and compute-unit microarchitecture, including dataflow pipelines, execution units, and interfaces. Set performance, power, and area targets, and guide the team toward achieving them.
• On-chip interconnects and system integration: Define and drive the design of on-chip networks and data movement across the fabric, balancing performance, scalability, and implementation constraints in collaboration with physical design.
• Memory subsystem & system architecture: Define the interface to the memory subsystem, including data movement, ordering, and synchronization behavior, ensuring a clean and scalable model for software and future system expansion.
• Reconfiguration and execution model: Lead the architecture of configuration, scheduling, and execution of workloads on the fabric, including multi-kernel support and interaction with host systems.
• Power management and low-power design: Drive power architecture across the design, including clocking, reset, power domains, and low-power strategies to meet aggressive energy and efficiency goals.
• HW/SW co-design: Collaborate closely with compiler and software teams to define the hardware execution model, ensuring efficient mapping of workloads onto the architecture.

Specifications, Documentations and Reviews: Author and own uArch specification documents for assigned blocks; drive design reviews with architecture, compiler, DV, and physical design stakeholders.

• Mentoring and process improvement: Mentor senior and junior RTL engineers; review RTL, flag microarchitecture risks, and enforce coding style and lint-clean standards across the team.
• Driving PPA Metrics: Participate in PPA analysis loops: synthesize blocks regularly, review area/timing/power reports, and make data-driven tradeoffs against performance and feature requirements.
• DV Collaboration: Collaborate with DV leads to define/review verification plans; provide directed test scenarios for graph execution corner cases, back-pressure conditions, and power state transitions.
• Silicon Bring-up: Support silicon bring-up: contribute scan/ATPG guidelines, review DFT insertion, and provide RTL-level debug assistance during lab validation.

Required Qualifications & Experience

• 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems  or peripheral integration on a processor or accelerator SoC.
• Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware; able to design complex state machines, arbiters, token flow controllers, and datapath logic from scratch.
• Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures; familiarity with the hardware challenges of token-based firing-rule evaluation and producer-consumer synchronization.
• Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces.
• Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic.
• Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level.
• Experience taking RTL through synthesis and timing closure; ability to read and act on SDC constraints, STA reports, and synthesis QoR summaries.
• Strong written communication skills; able to produce uArch specs and design review material independently.
• Experience with memory compiler toolchains

Desired Qualifications & Experience Requirements 

• Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture with explicit producer-consumer token management.
• Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations.
• Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases.
• Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and the RTL design choices they necessitate.
• Familiarity with functional safety standards (ISO 26262, IEC 61508) as applied to execution fabric error detection and power domain isolation.
• Exposure to AI framework graph formats (ONNX, TFLite) and understanding of how graph compilation maps to hardware execution primitives.
• Tape-out credits on an edge-AI, IoT, or wearable SoC at 12nm or below.
• Experience with formal verification of flow-control logic, deadlock freedom, or bus protocol compliance.

We offer a competitive salary for this role, generally ranging from $160,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.