Role

We are looking for a Sr Staff Software Development Engineer to join our ZPA datapath team. This is a hybrid role based in San Jose (3 days in office), reporting to the Director, Engineering. As a core technical expert, you will drive the design, development, and optimization of critical network applications and protocols. You will leverage your deep expertise in C/C++ and Linux to build scalable, high-performance network solutions that secure and streamline enterprise data across cloud environments.

What you’ll do (Role Expectations)

• Develop and optimize network applications and protocols using C/C++
• Design efficient data structures for network data processing and handle system-level programming in Linux environments
• Analyze network performance to identify issues and implement optimization solutions
• Collaborate with teams to define requirements, design architectures, and integrate network solutions
• Conduct code reviews, testing, and debugging to ensure robust and reliable software

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.
• You operate with urgency. You understand that in a high-growth environment, speed and quality are not mutually exclusive. You have a relentless focus on execution and a bias for action, delivering high-impact results quickly to win for the customer and the team.
• You are a problem-solver. You seek out challenges because you are energized by finding solutions, knowing that solving the hard problems delivers the biggest impact.
• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.
• You lead with integrity. You do the right thing, even when it’s hard. You hold yourself and others to a high standard of accountability and build trust by matching your words with consistent, transparent action.

What We’re Looking for (Minimum Qualifications)

• 8+ years of experience in a distributed and enterprise-scale environment
• Strong knowledge of C programming specifically for network-related data handling and processing
• Expertise in Linux environments, including system-level programming, scripting, and troubleshooting
• Experience with networking protocols and traffic management technologies (e.g. TCP/IP, HTTP/HTTPS, SSL/TLS, QUIC)
• Strong knowledge in one of the cloud platforms like AWS, Azure, or GCP

What Will Make You Stand Out (Preferred Qualifications)

• Experience in L3 protocols, routing, BGP
• Experience in Cloud-based Networking
• Ability to stay current with industry trends and propose enhancements to improve system reliability, scalability, and network efficiency

#LI-YC2 #LI-Hybrid

About The Company

DiDi's autonomous driving unit was established in 2016 with the mission of developing Level 4 autonomous driving (AD) technology to make transportation safer and more efficient. In August 2019, the unit became an independent company, DiDi Autonomous Driving, dedicated to advanced AD R&D, product application, and business expansion. We believe integrating AD technology into a shared-mobility fleet will generate immense social value. By leveraging DiDi's specialized technology, operational expertise, and integrated ecosystem, we are positioned to build and operate a highly efficient, user-oriented autonomous fleet.

About The Role

We are seeking an experienced and mission-driven Staff System Safety Engineer, Autonomy to lead the safety strategy and deployment readiness of our fully autonomous driving systems. In this role, you will define and implement the safety frameworks, release policies, and system-level engineering processes that enable safe and scalable unmanned operations. You will act as a technical leader in system safety, ensuring that our vehicles meet rigorous safety standards while advancing toward large-scale commercial deployment.

Responsibilities

• Own the safety evaluation and release strategy for unmanned autonomous driving operations, defining clear criteria for system release, degradation, and fallback under varying operating conditions.
• Design, implement, and champion the safety-related systems engineering framework, including safety requirements, system architecture, and Verification & Validation (V&V) plans.
• Conduct systematic assessments of unmanned operational workflows, emergency protocols, and supporting tools/platforms to ensure safety and operational completeness.
• Develop and institutionalize safety evaluation methodologies and metrics frameworks, translating safety goals into quantifiable, verifiable, and continuously tracked indicators.
• Serve as the technical lead for safety-related incident review and analysis during unmanned operations, driving continuous improvements in system design, test coverage, and operational procedures.
• Collaborate cross-functionally with Software, Product, Operations, and Safety teams to support leadership decisions regarding unmanned deployment, city expansion, and operational scaling.

Qualifications

• Bachelor’s or higher degree in Computer Science, Software Engineering, Systems Engineering, or a closely related technical field.
• 5+ years of industry experience in systems engineering, safety engineering, autonomous systems, or a directly related field.
• Strong systems thinking with the ability to decompose complex safety challenges and drive practical, scalable solutions.
• Demonstrated ability to collaborate across teams, influence stakeholders, and take ownership of safety outcomes.
• Experience working in a fast-paced environment with multiple parallel projects and ambiguous requirements.

Preferred Qualifications

• Professional experience in safety-critical autonomous vehicle deployment or large-scale robotic systems operations.
• Background in functional safety (ISO 26262, SOTIF) or safety assurance of unmanned systems.
• Hands-on experience with safety validation tools, simulation-based V&V, or operational safety monitoring platforms.
• Proven track record of defining release policies or safety readiness criteria for real-world autonomous systems.

The base salary range for this full-time position is $178,286-296,400 annually in addition to bonus, equity and benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

I acknowledge that prior to submitting this application, I have read and accepted the Privacy Notice for California Residents which is available on https://v.didi.cn/AQnxlBa

Role 

We are looking for a Staff Site Reliability Engineer to join our Cloud Infrastructure & Operations team in our San Jose, CA HQ Office. This is a hybrid role reporting to the Chief Architect, REIS. You are an SRE with proven experience in Linux/UNIX System Administration and hands-on expertise in building infrastructure and managing platforms like Kubernetes using automation tools and high security standards. In this role, you will troubleshoot complex Linux networking and security issues, apply a strong understanding of firewall technologies, and manage access across various systems, platforms, and applications.

What you’ll do (Role Expectations)

• Create and maintain highly scalable solutions based on KVM Linux, Kubernetes, and Public Cloud Providers
• Analyze and troubleshoot systems performance and complex issues across operating systems and applications
• Maintain platform security and observability through nftables and comprehensive monitoring
• Manage and deploy systems and software in diverse environments, including Kubernetes and Openstack
• Write and maintain custom tools using Python, Golang, and BASH

Who You Are (Success Profile)

• You thrive in ambiguity and are comfortable building the path as you walk it, seeing a dynamic environment as the raw material to build something meaningful.
• You are a problem-solver who seeks out challenges because you are energized by finding solutions that deliver the biggest impact.
• You operate with urgency and maintain a relentless focus on execution, understanding that speed and quality are not mutually exclusive in a high-growth environment.
• You are driven by innovation and a deep curiosity for how things work, always looking for a better, more secure, and scalable way to accelerate transformation.
• You lead with integrity and hold yourself to a high standard of accountability, building trust by matching your words with consistent, transparent action.

What We’re Looking for (Minimum Qualifications)

• Strong understanding of web security, protocols, and SSH
• Technical security aptitude including PGP, SSH, PKI, and Multi-factor authentication
• Mastery of network fundamentals including DHCP, ARP, subnetting, routing, NAT, firewalls, and IPv4/IPv6
• Experience in container orchestration services including Docker and Kubernetes, alongside automation tools like Ansible
• 5+ years of experience in a Linux/UNIX System Administration or SysAdmin role

What Will Make You Stand Out (Preferred Qualifications)

• Strong Openstack and CEPH experience paired with advanced Kubernetes expertise
• Extensive professional history in dedicated Linux System Administration roles
• Direct experience with Secrets Management Systems such as Hashicorp Vault or similar technologies

#LI-Hybrid 

#LI-CM3

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop and maintain highly interactive, large-scale and complex web-based visual analytics tools on AI/ML workloads.
• Design and implement creative and performant visualizations to assist in diagnosing issues or uncovering optimization opportunities in AI/ML inference and serving.
• Collaborate closely with hardware architects and compiler engineers to define, design, and implement effective visualization solutions enhancing their workflow.
• Develop high-performance visualization workflows by integrating independent graphics modules with micro-services to handle asset optimization, ensuring a non-blocking experience on the client.
• Continuously seek improvements to existing tools and develop new approaches to meet fast-evolving requirements.
• Stay up-to-date with the latest advancements in web development and visualization techniques.
• Contribute to the development of the documentation and user guides.
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• An innate drive to clarify deep technical complexity, balancing creative visualization with engineering rigor to build analytical tools that make interdependent hardware and software models intuitive without sacrificing logical precision.
• Strong experience in full-stack visual analytics software development, with a focus on building scientific or infrastructure visualization tools. Experience in AI model visualization integrated with PyTorch is a plus.

• Strong proficiency in modern frontend technologies like React and backend technologies like Node.js or Python-based frameworks. Experience in graph-based UI is a plus.
• Proven experience in WebGL/WebGPU based frameworks such as three.js or deck.gl. GLSL experience is a plus. Experience in WebAssembly with C++ is a plus.
• Excellent problem-solving skills and ability to think critically and creatively.

• Excellent communication and interpersonal skills.
• Ability to work independently and as part of a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

Role

We are looking for a Staff Software Development Engineer - DevSecOps to join our team in a hybrid capacity in San Jose, CA, reporting to the Director, Software Development Engineering. Our Engineering team built the world’s largest cloud security platform from the ground up, and we keep building. You will support internal product teams in managing CI/CD pipelines, strengthening security practices, and maintaining shared engineering systems to enable organizations worldwide to harness speed and agility with a cloud-first strategy.

What you’ll do (Role Expectations)

• Build and manage CI/CD systems to deploy critical applications across hybrid cloud environments including AWS, GCP, and proprietary clouds

• Support internal product teams with CI/CD pipelines, automations, and tools like GitLab, GitHub, Jenkins, ArgoCD, and security scanning solutions

• Secure code, applications, and infrastructure using security scanning tools such as SonarQube, Snyk, Coverity, and CheckMarx

• Administer and optimize critical DevSecOps applications while monitoring build metrics with tools like Grafana, Prometheus, and CloudWatch

• Communicate progress to stakeholders through Jira, technical documentation, and clear status updates

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.

• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.

• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.

• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.

• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• 5+ years of professional experience including hands-on experience managing cloud environments such as AWS, GCP, or private clouds

• Proficiency in application development or automation using OOP languages like C/C++, Java, Python, or Go, plus exposure to container orchestration and automation tools

• Familiarity with application security testing methodologies and experience using tools like SonarQube, Snyk, Coverity, or CheckMarx

• Experience designing and managing GitOps-based pipelines using GitLab, GitHub, and CI/CD automation tools like Jenkins or GitHub Actions

• Bachelor’s degree in Computer Science or a related field, or equivalent practical experience

What Will Make You Stand Out (Preferred Qualifications)

• Experience with AI and ML tools in day to day DevSecOps activities

• Experience writing and developing yaml based CI/CD Pipelines and knowledge of build tools like makefiles, gradle, npm, or maven

• Experience with Networking, Load Balancers, Firewalls, and Web Security

#LI-Hybrid #LI-KM9

We are looking for a Staff Escalation Engineer to join our Shared Platform Services team. This is a hybrid role based out of either our San Jose, CA office (3 days a week), reporting to the Sr. Manager, Software Engineering QA. You will be instrumental in taking the Zscaler Client Connector Cloud service to the next level in terms of reliability, availability, and scalability. As part of the team that built the world’s largest cloud security platform, you will bring your vision and passion to enable organizations worldwide to harness speed and agility with a cloud-first strategy.

What you’ll do (Role Expectations)

• Own and resolve escalated cloud incidents end-to-end, including impact analysis, debugging, implementing solutions, and communicating with stakeholders

• Collaborate with development, security, and operations to design and implement code/configuration fixes for complex system issues

• Monitor system health, performance, and security via PagerDuty and enhance alerting to meet SLOs

• Build diagnostic tools, dashboards, and documentation to enable faster, more effective incident resolution across the team

• Lead production service ownership and supportability by deploying critical fixes, making key deployment decisions, and responding to high-pressure off-hours events

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.

• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.

• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.

• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.

• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• 5+ years of experience along with expert troubleshooting, debugging, and root-cause analysis for complex, high-priority incidents, with experience using CPU/memory profilers to diagnose resource exhaustion

• Strong hands-on skills in Python, Bash, and Java; cloud platforms (GCP, AWS, Azure); and IaC/configuration tools (Terraform, Ansible)

• Ability to write complex MySQL queries and generate business reports

• Experience with authentication protocols such as SAML and OAuth

• Solid networking fundamentals (TCP/IP, UDP, ICMP) and debugging with Postman and packet captures, along with proficiency in monitoring tools like Grafana

What Will Make You Stand Out (Preferred Qualifications)

• Experience developing applications with Java, REST APIs, MySQL, and jQuery

• Bachelor’s degree in Computer Science or Computer Engineering (or related field); MS in CS/CE preferred

#LI-JM1 #LI-Hybrid

We are looking for a Staff Engineer to join our Shared Platform Services team. This is a hybrid role based in San Jose, CA, reporting to the Sr. Manager, Software Engineering QA. As a Staff Engineer, you will be instrumental in leading functional, system, and automation testing for Zscaler features while expanding automation infrastructure to enhance quality and efficiency.

What you’ll do (Role Expectations)

• Collaborate across Development, Product Management, and Federal Cloud Operations teams to ensure timely delivery of high-quality products through design, testing, and release

• Lead functional, system, and automation testing efforts, expanding automation coverage and ensuring efficiency and robust quality assurance

• Manage Federal cloud processes, including deployment procedures, monitoring, and resolving escalations in collaboration with Federal operations and support teams

• Investigate and resolve complex production issues by identifying root causes, verifying fixes, and developing comprehensive test plans

• Contribute to team growth by hiring and training new talent, fostering a culture of inclusivity, and staying updated on evolving technologies

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.

• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.

• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.

• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.

• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• US Citizenship Required with 5+ years of Software Development or Quality Assurance experience, specifically within networking and security environments

• Strong expertise in cloud-hosted applications, database operations, API testing, microservices architecture, and automation scripting using Python

• Proficiency in L4-L7 Internet and Security networking protocols including TCP/IP, SSL/TLS, and HTTP/HTTPS

• Experience with deployment and monitoring tools such as Jenkins, GitLab, and Ansible

• Bachelor’s degree in Computer Science Engineering or a related field with a proven ability to troubleshoot complex cloud issues

What Will Make You Stand Out (Preferred Qualifications)

• Experience with AI in testing and automation, leading quality teams, and familiarity with FedRAMP qualification

• Deep knowledge of Linux system administration, traffic generation tools like Ixia or Spirent, and relevant cloud or networking certifications

• Understanding of authentication systems such as LDAP and SAML, encryption solutions, and debugging Linux systems

#LI-JM1 #LI-Hybrid

What You’ll Do

• Develop and maintain models for electric motors, inverters, thermal management systems, gearboxes, and power distribution systems.
• Create integrated multi-physics models coupling electrical, thermal, mechanical, and controls domains.
• Use analysis to inform design decisions and optimize overall propulsion system performance. Lead trade studies evaluating design alternatives to determine optimal thermal solutions.
• Design creative high performance thermal systems, then build engineering prototypes to confirm performance. 
• Design and build thermal test setups to measure system critical temperatures, flowrates, and pressures and confirm performance. 
• Plan and oversee execution of thermal test campaigns validating your thermal models, including FAA certification testing related to the thermal system. 
• Collaborate with other engineers to develop propulsion system thermal boundary requirements (external cooling flows, temperatures) and ensure propulsion system thermal design is optimized for vehicle level performance.  
• Collaborate with mechanical design teams to package your thermal designs within the volume and mass constraints of the aircraft.
• Collaborate with Software and Controls teams to develop and implement embedded thermal models, observers, and overheat prevention. 
• Clearly document and communicate thermal design rationale, analysis methodologies, and test results. 
• Review measured thermal data from propulsion systems on Archer aircraft, confirm thermal systems are meeting performance requirements on aircraft

What You’ll Need

• BS / MS / PhD in Mechanical Engineering, or Aerospace Engineering
• 4+ years experience in thermal design and simulation, preferably within the aerospace or automotive sectors.
• Strong fundamentals and demonstrated understanding of heat transfer and flow physics, including, conduction, convection and radiation
• Experience with power electronics, electric motor, heat exchanger, and gearbox thermal design. 
• Strong Experience in MATLAB/Simulink and Python (including object-oriented programming and version control via Git).
• Experience with industry-standard tools such as StarCCM+, Ansys Fluent, Ansys ICEpak and Thermal analysis packages, 
• A systematic approach to problem-solving and the ability to communicate complex technical rationale to multidisciplinary stakeholders.
• Experience with lumped parameter thermal networks modeling, reduced-order modeling, kalman filters, control theory and application, and advanced signal processing.
• Experience with thermal testing and test-data correlation
• Self-motivated with ability to work independently and drive technical initiatives
• Strong written and verbal communication skills, experience writing technical reports. 

Bonus Qualifications

• Prior experience with eVTOL aircraft
• Familiarity with FAA certification basis (Part 23/25 or 27/29)
• Experience with CAD modeling systems (e.g . NX, CATIA, Solidworks)
• Experience with embedded microcontroller software development in C
• Experience utilizing high-performance computing (HPC) to parallelize workflows
• Knowledge of simulation model validation, model calibration, and uncertainty quantification methods

Physical Requirements:

• Ability to work in laboratory and test environments
• May require occasional travel to test facilities

At Archer, we aim to attract, retain, and motivate talent with the skills and leadership needed to grow our business. We drive a pay-for-performance culture and reward performance that support the Company's strategy. For this position, we are targeting a base pay range of $172,000 - $225,000. Actual compensation offered will be determined by job-related knowledge, skills, and experience.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

What You’ll Do

The Director Foundry Customer Engineering (CE) will manage the Samsung foundry customer's programs in various process technologies. This position requires you to work with both customer and Internal stakeholders seamlessly from business development to new product introduction (NPI) to full production.

The Customer Engineer will be responsible for the business growth by providing Samsung Foundry engineering services excellence. You will act as primary technical account interface with the Customer and all other functional teams in Samsung, and you are enabled to drive manufacturing teams to achieve production milestones in order to accomplish company business goals.

The ideal candidate will be enabled to grow within Samsung and qualified for further opportunities within our alternative verticals as well as within our Foundry group.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy plus an average of <10% of domestic and international travel. 

Reports to:  Sr. Director, Customer Engineering

Req #:  42864

• Support internal account strategy plan, coordinate alignment of business and engineering executions
• Provide customer satisfaction by responding to account actions and driving collaboration on technical and cost effective solutions to meet customer and foundry's goals.
• Partners with engineering and business groups to ensure new product introduction (NPI) activities are meeting customer schedule and technical requirements.
• Complete other responsibilities as assigned.

What You Bring

• Bachelors in Electrical Engineering or related Physical Science with 20+ years of experience or Masters in Electrical Engineering or related Physical Science with 18+ Years of Industry Experience or PhD in Electrical Engineer or related Physical Science with 15+ years of Industry Experience. 
• Recent experience in Semiconductor process, product or device engineering required
• Previous work experience with major semiconductor foundry or Integrated Device Manufacturer companies preferred
• Previous project management experiences are preferred
• Strong customer orientation, good communication and presentation skills
• Proficient in Microsoft PowerPoint, Excel etc.
• Professional working proficiency in Mandarin is a plus
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Design and development of high performance firmware and software for cutting-edge enterprise SSD products.
• Debug, optimize, and validate SSD firmware on complex embedded multi-core architectures.
• Support customer qualification and adoption of SSD products.
• Participate in ground-breaking advanced SSD storage development and research projects.

What You Bring

• BS in Computer/Electrical Engineering or Computer Science with 3+ years of working experiences in silicon development or MS in Computer/Electrical Engineering or Computer Science with 1+ years of relevant working experience or PhD and 0+ years of relevant experience in storage firmware development is required.
• Strong programming experience and demonstrated proficiency in C/C++ for embedded systems, including development of algorithms, manipulation of complex data structures, and implementing highly optimized code, is required.
• Relevant hands on experience in embedded software or firmware development, including storage devices or other embedded platforms is required.
• Experience with one or more of the following storage related technologies: NVM Express, PCI Express, SAS, SCSI, NAND Flash/FTL, Fibre Channel, SATA, eMMC, or UFS is beneficial.
• Experience with ARM or equivalent embedded multi-core microprocessor architectures is required.
• Hands on experience with JTAG/ICE debuggers and protocol analyzers is required.
• Some scripting experience in one of Python/Perl/Javascript is desired.
• Familiarity and experience with modern agile software development methodologies and practices is preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

Job Title: Principal engineer, AI Serving Framework Architect (Software)

What You’ll Do    

The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a key role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42853

• As a Tech Lead, leading research teams in Korea and proposing technical direction
• Research on dynamic scheduling methodologies for maximizing AI inference performance in multi-rack scale memory-centric systems, comprised of heterogeneous compute-capable memory and hierarchical memory
• Investigating methods to accelerate search operations in RAG’s vector DB and AI Agent’s knowledge-graph by leveraging compute-capable memory
• Studying strategies for optimally placing KVCache and a vector DB in hierarchical memory to minimize frequent SSD accesses and reduce IO stalls
• Proposing SW design for implementing the derived optimization algorithms on open-source platforms such as vLLM

What You Bring

• PhD in Computer Science or a related field with 10+ years of experience in AI Serving Framework for large-scale computing, with focusing on the AI workloads. 
• Led a project to build and optimize a Large Language Model (LLM) Inference Software Stack on a multi-rack scale system to deliver AI Inference services to over 100,000 users. 
• Extensive experience in designing AI Inference Software Stacks for heterogeneous devices.In-depth understanding of the internal architecture and operation mechanisms of inference engines such as vLLM. 
• Proficiency in AI Inference System Profiling and optimization. 
• Knowledge and practical experience with future AI workloads, including reasoning models, multi-modal solutions, AI agents, and world models. 
• Strong understanding of compute, memory, and networking bottlenecks in AI systems. 
• Required skillsets: PyTorch, Python, and C++ 
• A collaborative mindset, curiosity, and resilience in solving complex challenges. 
• Excellent verbal, presentation, and written communication skills. 
• (Nice to have) Native or fluent Korean speakers are preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build. Understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change 

#LI-SF1

Job Title: Principal Engineer, AI System Architect (Hardware)

 What You’ll Do
The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a Technical Lead role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42852

• • Technically Lead the architecture team with strong  direction, shaping system‑architecture strategy and advancing key innovations
  • Conduct system-level architectural research for next-generation AI systems, spanning compute, memory, and interconnect/network subsystems.
• Develop and maintain analytical and simulation-based system modeling frameworks to evaluate AI workloads and identify performance, scalability, and efficiency bottlenecks at rack- and system-scale. 
• Analyze representative and emerging AI workloads (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power.  
• Drive architecture-level design decisions through quantitative modeling, design-space exploration, and performance/power projections. 
• Perform comparative studies of alternative system architectures, reporting performance and performance-per-watt metrics to guide strategic technology choices. 
• Collaborate closely with cross-functional teams in hardware architecture, memory, interconnect, and system engineering to align modeling insights with implementation realities.  
• Communicate architectural insights and recommendations through clear technical presentations and documentation.   
• Occasional domestic and international travel (<10%).

 What You Bring

• Ph.D. in Computer Science, Electrical Engineering, or a related field preferred,  with 15+ years of experience in system architecture for large-scale computing platforms, with a strong focus on AI workloads 
• Proven hands-on experience developing analytical and event-driven simulation models for system-level performance evaluation. 
• Deep understanding of AI system hardware architectures, including compute, memory hierarchies, and high-performance interconnects.
• Strong knowledge of modern and emerging AI workloads, including LLMs, DLRMs, and large-scale training and inference systems.
• Demonstrated ability to translate workload characteristics and modeling results into actionable architectural design decisions.
• Proficiency in Python, C++, and PyTorch for modeling, analysis, and experimentation. 
• Excellent written, verbal, and presentation communication skills, with the ability to influence technical direction across teams.
• A collaborative mindset, intellectual curiosity, and resilience in tackling complex, open-ended system-level challenges. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Job Title: Principal Engineer, AI System Architect (Hardware)

The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a Technical Lead role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42852

What You’ll Do

• Technically Lead the architecture team with strong  direction, shaping system‑architecture strategy and advancing key innovations
• Conduct system-level architectural research for next-generation AI systems, spanning compute, memory, and interconnect/network subsystems.
• Develop and maintain analytical and simulation-based system modeling frameworks to evaluate AI workloads and identify performance, scalability, and efficiency bottlenecks at rack- and system-scale. 
• Analyze representative and emerging system-level architectural research (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power.  
• Drive architecture-level design decisions through quantitative modeling, design-space exploration, and performance/power projections. 
• Perform comparative studies of alternative system architectures, reporting performance and performance-per-watt metrics to guide strategic technology choices. 
• Collaborate closely with cross-functional teams in hardware architecture, memory, interconnect, and system engineering to align modeling insights with implementation realities.  
• Communicate architectural insights and recommendations through clear technical presentations and documentation.   
• Occasional domestic and international travel (<10%).

 What You Bring

• Ph.D. in Computer Science, Electrical Engineering, or a related field preferred,  with 15+ years of experience in system architecture for large-scale computing platforms, with a strong focus on AI workloads 
• Proven hands-on experience developing analytical and event-driven simulation models for system-level performance evaluation. 
• Deep understanding of AI system hardware architectures, including compute, memory hierarchies, and high-performance interconnects.
• Strong knowledge of modern and emerging AI workloads, including LLMs, DLRMs, and large-scale training and inference systems.
• Demonstrated ability to translate workload characteristics and modeling results into actionable architectural design decisions.
• Proficiency in Python, C++, and PyTorch for modeling, analysis, and experimentation. 
• Excellent written, verbal, and presentation communication skills, with the ability to influence technical direction across teams.
• A collaborative mindset, intellectual curiosity, and resilience in tackling complex, open-ended system-level challenges. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Principal, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab is seeking Principal CPU Architecture & Performance Engineer to lead the definition, analysis, and optimization of next-generation CPU microarchitectures (RISC-V core). This role is focused on end-to-end performance: from architectural trade-offs and workload characterization to micro-architectural modeling, simulation, and silicon bring-up correlation.

You will work closely with architecture, design, compiler, and system teams to drive performance and efficiency across a broad set of real-world workloads

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42918

• Define and evaluate CPU micro-architectural features for future cores (frontend, execution engine, memory hierarchy, interconnect).
• Lead performance analysis using simulators, RTL.
• Help develop and validate performance models (cycle-accurate, trace-driven, statistical).
• Characterize workloads (SPEC, server, client, AI/ML, cloud, internal traces) and translate findings into architectural requirements.
• Identify performance bottlenecks and propose data-driven optimizations.
• Drive architecture-to-implementation alignment with design team.
• Collaborate with compiler, OS, and system architects on cross-stack performance issues.
• Mentor senior and staff engineers; provide technical leadership across projects.
• Work leading to patents and publication

What You Bring

• Master’s with 18+ years of experience in Computer Engineering, Computer Science, or related field.
•  or PhD with 15+ years of experience preferred.
• 10+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC-V, ARM or X86 architectures.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Familiarity with compiler optimizations and hardware/software co-design.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Experience analyzing large performance datasets and traces.
• Proven ability (Tapeout / Patents /Publications) to influence architecture / micro architectural decisions through quantitative analysis.

Preferred Qualifications

• Background in power/performance/area (PPA) trade-off analysis.
• Experience with SIMD/Vectors.
• Experience with compiler optimizations and hardware/software co-design.
• Prior technical leadership at Senior Staff or Principal level. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

Advanced Circuit and Systems (ACAS) is looking for a highly skilled engineer that has strong background and hands-on experience on RFIC design. The candidate will be developing next-generation RF transceivers and mixed-signal circuits for

What You’ll Do

• Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS technologies.
• Lead efforts to perform chain and chip level design verification and production support tasks.
• Work closely with digital and software developers to develop an implementation that meets
• system requirements.
• Research in advanced wireless techniques for highly integrated RFICs

What You Bring

• Bachelor’s with 20+ years of experience or  Master's with 18+ years of experiences or PhD with 15+ years of experience in a related field.
• Hands-on experience in designing various RF/Analog integrated circuits, such as LNA, Mixer, RF VGAs, PA, VCO, etc., in deep sub-micron CMOS technologies.
• Ability to comprehend RF transceiver system level requirements and translate into circuit level specifications. Excellent problem solving and analytical skills are essential.
• Technical leadership, mentoring, and post-silicon validation expertise are essential.
• Specialized knowledge in high-speed I/Os (SerDes, DDR) or data converters is a bonus.
• Strong knowledge on IC design CAD tools such as Spectre, SpectreRF, Spice, Matlab, and/or ADS.
• Thorough understanding of the physical layout requirement and ability to perform the critical layouts.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

What You’ll Do

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Support trace-driven power modeling, aligned with C/SystemC workload traces.
• Perform synthesis-assisted calibration using average and worst-case power anchors when available.
• Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
• Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
• Contribute to scalable IP-wise composition for full-system power simulation.

What You Bring

• Bachelors degree 20+ years of experience or Masters degree 18+ years of experience.
• Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
• Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
• Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
• Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
• Familiarity with SystemC or transaction-level modeling.
• Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
• Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Preferred Qualifications

• Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
• Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
• Exposure to low-power design and thermal management.
• Exposure to power macromodeling, power estimation flows, or architectural power analysis.

Principal Engineer, SOC Design

What You’ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.  DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Job ID:  42866

Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy

• Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
• Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
• Reviews 3^rd party IPs including ARM cores, DDR controller, and UCIe PHY 
• Responsible for integrating the third part IPs and sub system at top level
• Work closely with architects and verification engineers to ensure sound design at SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

What You Bring

• Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
• Highly motivated with good verbal and written communication skills.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
• Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
• Good understanding of PPA (performance, power, and area) trade-offs.
• Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
• Experience in interfacing 3^rd party service companies for DFT/PI/PD.
• Good knowledge and experience in AMBA bus fabric, ARM cores.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Samsung Semiconductor is hiring now for a Senior CIS Application Engineer.  You will join a dynamic team focused on developing and validating cutting-edge CMOS Image Sensor (CIS) technologies and the complete imaging pipeline they power. Your expanded role will involve not just sensor characterization, but also establishing objective and subjective image quality standards. You’ll collaborate across design, process and product engineering to ensure that CIS devices meet stringent technical specifications and exceed end-user visual expectations across the entire system. This position offers opportunities to define holistic test methodologies and drive product innovation in advanced imaging systems.

What You'll Do

• Establish objective evaluation criteria and subjective perceptual measurement methodologies for the full imaging system (CIS devices, PKG, modules, and ISP output) under dark and light conditions.
• Conduct detailed characterization and performance analysis.
• Analyze test results to identify trends, anomalies, and potential root causes of image performance issues, spanning hardware defects to ISP.
• Work closely with design and process team to provide feedback and propose improvements for image sensor and overall system performance.
• Develop and automate test flows for consistent and efficient evaluation using standard programming languages and specialized IQV software tools (e.g., Imatest).
• Ensure compliance with relevant industry image quality standards.
• Communicate results effectively to cross-functional teams and management stakeholders.
• Act as the primary technical contact person for customers, addressing their technical questions and concerns.
• Serve as a bridge between the customer and internal engineering/product development teams, conveying customer feedback and advocating for necessary fixes or improvements.
• Diagnose and resolve complex technical issues promptly, often involving embedded hardware and software debugging in camera systems.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Job ID: 42887

 What You Bring

• Bachelor’s degree in Electrical Engineering, Physics, Optics, or related field with 5+ years of relevant industry experience, or Master’s with 3+ years or PhD with 0+ years of experience.
• Strong understanding of CIS operation principles, including pixel, readout chain, ADC behavior, and the full imaging pipeline (Optics, Sensor, ISP).
• Hands-on experience with image sensor characterization, test system operation, and standardized image quality lab environments (light booths, test charts).
• Knowledge of optical measurement techniques and evaluation under both dark and illuminated conditions.
• Proficiency in data analysis tools such as Python, MATLAB, or similar platforms, ideally paired with experience using professional IQV software like Imatest.
• Familiarity with industry standards for objective image quality measurement.
• Excellent analytical, problem-solving, and communication skills.
• A proactive mindset and strong attention to detail when working in cross-functional environments.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

Senior, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab is  seeking Senior CPU Architecture & Performance Engineer to contribute to performance analysis and microarchitectural optimization of current and next-generation CPU (RISC-V) cores. This role emphasizes hands-on analysis, modeling, and close collaboration with architects and design teams to improve performance across real-world workloads.

You will focus on executing well-defined performance studies, identifying bottlenecks, and helping translate architectural ideas into measurable performance gains

 Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42851

• Perform performance analysis for CPU microarchitectural features under guidance from Staff and Principal engineers.
• Run architectural simulations and analyze results (IPC, CPI stacks, latency and throughput metrics).
• Identify performance bottlenecks in frontend, execution engine, or memory subsystems.
• Assist in evaluating design trade-offs using trace-driven or cycle-accurate models.
• Characterize workloads and benchmarks (SPEC, server, client, internal traces).
• Develop scripts and tools to automate performance analysis.
• Work leading to patents and publication.

What You Bring

• Master’s, or PhD in Computer Engineering, Computer Science, or related field.
• 2+ years of experience in CPU microarchitecture and/or performance engineering.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Experience analyzing large performance datasets and traces.
• Familiarity with compiler optimizations and hardware/software co-design.

Preferred Qualifications

• Experience with RISC-V, ARM or X86 architectures.
• Background in power/performance/area (PPA) trade-off analysis.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Prior tapeout / patent / publication experience. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design.

Our team works hands-on with cutting-edge accelerator hardware, experimental memory systems, and emerging domain-specific languages (DSLs). We build and optimize a Triton-based software stack that pushes the limits of performance, efficiency, and scalability for modern LLM workloads.

We are looking for a Senior AI Systems Engineer with deep experience in high performance Triton kernel development on modern accelerators. In this role, you will design, analyze, and optimize performance-critical kernels used in large scale LLM inference and training pipelines. You will work closely with hardware architects, compiler engineers, and ML researchers to identify performance bottlenecks, interpret profiling data, and co-design solutions that span software and hardware boundaries.

This role is ideal for engineers who enjoy working close to the hardware stack while still reasoning deeply about model level abstractions.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Design, implement, and optimize high-performance Triton kernels for LLM workloads on existing accelerators.
• Analyze kernel performance using profiling tools; interpret metrics such as latency, throughput, occupancy, memory bandwidth, and compute utilization.
• Identify performance bottlenecks in kernel design (e.g., memory access patterns, synchronization, tiling strategies) and propose concrete optimizations.
• Work across the stack; from model architecture to kernel implementation—to ensure end-to-end performance efficiency.
• Collaborate with hardware and compiler teams on hardware–software co-design, providing feedback that influences future accelerator and DSL designs.
• Prototype and evaluate kernel optimizations using upcoming DSLs and experimental compiler flows.
• Contribute to the evolution of a Triton-based software stack used for cutting-edge research and production-grade experimentation.
• Document design decisions, performance trade-offs, and optimization strategies clearly for internal and external stakeholders.

What You Bring

• Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience.
• Strong experience writing high-performance Triton kernels for GPUs or other accelerators.
• Solid understanding of LLM fundamentals, including attention mechanisms, transformer architectures, and inference/training workflows.
• Deep knowledge of accelerator hardware architecture, including:  Memory hierarchies (HBM, SRAM, caches).
• Proven ability to read and interpret profiling data and performance counters.
• Experience diagnosing and resolving performance bottlenecks in kernel-level code.
• Strong systems programming skills in Python and low-level performance-oriented programming paradigms.
• Experience with hardware–software co-design or compiler-assisted optimization.
• Familiarity with FlashAttention, fused kernels, MoE kernels, and different attention mechanisms.
• Experience working with emerging or experimental domain-specific languages (DSLs) for accelerator programming.
• Background in ML systems, compilers, or performance engineering.
• Prior experience working with different accelerator backends (including but not limited to CUDA).
• Opportunity to work on cutting-edge accelerator hardware and experimental software stacks.
• Direct impact on the performance and design of next-generation AI systems.
• A highly collaborative environment spanning hardware, systems, and ML research.
• Flexibility to publish, prototype, and influence future hardware and software directions.
• Ability to work effectively in cross-functional, research-oriented environments.
• Strong analytical and problem-solving skills.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The Samsung Semiconductor Inc., Wireless Connectivity Software Engineering team is seeking highly motivated and enthusiastic Software Engineers to join our team in developing software infrastructure, framework, and protocol stack for 802.11 based WLAN chipsets. We are looking for engineers with expertise in MAC Layer concepts and firmware development. As a member of the WLAN Software team, you will be responsible for developing software modules for the data path and control path in MAC and physical layer of various WLAN chipsets.

Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy

Req: 42831

What You’ll Do

• Work with 802.11 WLAN chipsets, devices and protocols, including other networking devices
• Collaborate with wider teams to for end to end feature deliverables build and maintain production quality Firmware
• Design and develop modules in embedded firmware for Samsung’s Wireless Connectivity solutions
• Major focus will be implementing, unit testing and fixing issues various features of 802.11 MAC

What You Bring 

• Bachelor’s Degree in Engineering or Computer Science Discipline with 5+ years of relevant industry experience, or Master’s with 3+ years or PhD with 0+ years in field of wireless communication technologies.
• Excellent coding skills in C in embedded space for firmware development is critical.
• Ability to debug issues with low-level embedded software, custom/proprietary code and enhancements.
• WLAN standards, domain knowledge of Wi-Fi (IEEE 802.11) MAC protocols, WFA protocols and coexistence with other wireless technologies such as BT, UWB and cellular.
• Knowledge of OFDM, OFDMA principals, beam forming and RF concepts will be additional advantage.
• Understanding of QoS concepts and data path optimization algorithms.
• Understanding of the Linux Operating System, kernel and device driver development.
• Ability to use various debugging tools such as wireshark, testing tools such as WFA test beds, version control tools such as git.
• Knowledge of Python will be additional advantage
• Familiarity with other wireless technologies such as BT, Ultra Wide band and Cellular 4G/5G not required but preferred.
• Excellent coding skills in C programming languages.
• Strong understanding of MAC Layer concepts & physical layer (e.g., modulation analysis (OFDM, OFDMA)) Concepts.
• Experience in developing firmware for wireless communication protocols (WLAN).
• Fluency in using lab equipment such as network analyzers, WFA test beds, signal generators, power meters etc.
• Familiarity with WLAN standards & domain knowledge of Wi-Fi MAC/PHY Specifications.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

 What You’ll Do

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

Job ID: 42786

• NVMe or SAS SSD Firmware development
• Analyze, debug, and resolve firmware issues observed at domestic and international customer sites as well as at local and overseas development centers.
• Triage and root cause system, driver, and device interoperability issues at customer sites.
• OEM Spec gap analysis, firmware customization/feature development; collaborate with other engineering teams to analyze debug information and implement and deploy firmware patches.
• Need based business travel and stay at domestic and international customer sites as well as overseas development centers for extended periods of time (can be up to multiple weeks at a time)
• Assist customers by running or inspecting their tests at onsite locations

What You Bring

• BS in Computer/Electrical/Electronic Engineering or Computer Science, and 5 years of relevant experience in software or firmware or a MS in Computer/Electrical/Electronic Engineering or Computer Science with 3 years of relevant experience preferred. 
• Strong experience in C/C++ programming for embedded systems is required. 
• Strong experience with UART/JTAG/ICE debuggers, and protocol analyzers. 
• Familiarity with at least one of the storage protocols such as SAS / SATA / SCSI / FC / NVMe / PCIe protocols is required. 
• Hands on experience with UART/JTAG/ICE debuggers, firmware debugging and protocol analyzers. 
• Demonstrated ability to work as a team player, as part of a local and globally distributed team. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

We are looking for a Senior Engineer, Performance Architecture.  This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Model the architecture, performance, and power characteristics of Memory Centric Computing platforms
• Develop and optimize models to explore a large design space.
• Analyze various trade-offs within a design space, considering different architectural choices and workloads.
• Collaborate with architecture, design and software engineers to ensure that the PPA of modeled systems meet the requirements of our users
• Conduct research and development in emerging technologies and trends in AI/ML workloads and Memory Centric Computing architectures
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget

What You Bring

• BS in Computer/Electrical Engineering or Computer Science with 5+ years of working experiences in silicon development or MS in Computer/Electrical Engineering or Computer Science with 3+ years of relevant working experience or PhD and 0+ years of relevant working experience preferred.
• Strong background in computer architecture
• Experiences in developing and optimizing models for high-performance computing systems
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

What You’ll Do

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Support trace-driven power modeling, aligned with C/SystemC workload traces.
• Perform synthesis-assisted calibration using average and worst-case power anchors when available.
• Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
• Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
• Contribute to scalable IP-wise composition for full-system power simulation.

What You Bring

• Bachelors degree 5+ years of experience or Masters degree 3+ years of experience.
• Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
• Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
• Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
• Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
• Familiarity with SystemC or transaction-level modeling.
• Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
• Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Preferred Qualifications

• Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
• Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
• Exposure to low-power design and thermal management.
• Exposure to power macromodeling, power estimation flows, or architectural power analysis.

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

We are looking for a Senior Engineer, RTL Memory Centric Computing.  This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop IP for memory centric computing systems using Verilog, System Verilog and HLS
• Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.
• Collaborate with Verification engineers to design and develop test plans
• Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in microarchitecture and computer architecture
• 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs
• Experience in designing Memory Controller, NOC, Interconnect IP
• Experience in Memory Centric computing IP and  SOC integration
• Experience in AI/ML workloads.
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-VL1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

What You’ll Do

Samsung Display’s America R&D Lab is hiring for a Senior Systems Engineer, for a knowledgeable, self-driven individual contributor in field of display metrology and standardization. Our lab works closely with Samsung Display Co. (SDC), which supplies premium displays for smartphones, laptops, monitors, and TVs using industry leading technology. SDC is the first company in the world to mass produce flexible OLEDs, foldables and QD displays, creating the best displays that connect technology and people in a more valuable way.

This role is part of a dedicated team within a large global organization, advancing display metrology, product certifications, and standardization through collaboration with diverse stakeholders to deliver outcomes that directly impact company products.

This is an unique opportunity for a grounded, adaptable professional who is comfortable filling the gap, bringing patience and expertise to shape display eco-system over time.

We believe that innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy with 10-20% of domestic and international travel.

Reports to: Principal Engineer

• Develop industry-leading test methodology and solutions
• Develop display-related standards, ensure alignment with organizations, e.g: VESA, ICDM, SMPTE
• Compare and analyze display performance to standardization targets, and recommend actions.
• Develop display metrology test patterns and test protocols; propose to IEC and ICDM as appropriate.
• Publish in peer-reviewed papers, conferences, and industry magazines that advances the display ecosystems.
• Communicate complex technical concepts clearly and effectively to diverse audience..
• Complete other responsibilities as assigned.

What You Bring

• Minimum of Master’s of Science degree in Physics, Electrical, Optics, or Materials Engineering or related field OR PhD is preferred.
• 3-5 years of relevant industry experience.
• Required expertise with display metrology and related instruments (ie. Spectrometer, colorimeter)
• Experience in Python, Matlab (Octave), or C++
• Conversant with industry forums and standardization procedures is a strong plus.
• Travel internationally several times a year, such as conference presentation, internal standard meetings.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

What You’ll Do

Samsung Semiconductor is seeking a Senior Systems Engineer to lead the design, modeling, simulation, and experimental validation of high-performance optical products and precision lenses.

You will apply strong fundamentals in physics, optics, and mathematics, alongside hands-on experience in electro-optical prototyping and hardware integration. Your role involves advanced ray-tracing simulations for complex LiDAR systems to generate 3D point cloud data and ensure system-level performance.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy with an average of 15% travel per month

Reports to: Director

• Lead the design, modeling, and experimental validation of LiDAR sensors and precision optics.
• Optimize optical architectures using sequential and non-sequential ray-tracing tools (e.g., Zemax, LightTools, or Speos).
• Design high-precision lenses and validate the seamless integration of optical components.
• Develop detailed ray-tracing models for sophisticated LiDAR scanners (multi-beam, scanning mechanisms, and detectors) while assembling and aligning electro-optical setups.
• Simulate environmental interactions to produce accurate 3D point cloud data for algorithm verification and system validation.
• Script custom simulation tools in Python or other languages for error budgeting and performance analysis.
• Execute experimental measurements and data acquisition to drive iterative design improvements and technical reporting.
• Complete other responsibilities as assigned.

What You Bring

• Master’s degree with 3+ years experience or PhD in Physics, Optical Engineering, Electrical Engineering, or a related field.
• 3 + years in automotive semiconductor or sensor industries, focused on optical system design and manufacturing.
• Solid background in physics, optics, and applied mathematics.
• Proven expertise in optical design, modeling, and experimental validation.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

The engineer develops and extends the trace‑driven power/thermal simulation engine, integrating power macromodels, workload traces, and thermal solvers into a coherent, scalable simulation flow.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

What You’ll Do

• Implement and optimize trace‑driven power and thermal simulation engines.
• Integrate IP‑level power macromodels into system‑level simulation.
• Manage a time‑indexed simulation flow across power and thermal domains.
• Generate transient power maps and perform spatiotemporal hotspot analysis.
• Interface with reduced‑order thermal models and CFD‑calibrated solvers.
• Ensure simulation performance, scalability, and reproducibility.

What You Bring

• Bachelors degree 5+ years of experience or Masters degree 3+ years of experience.
• Strong C++ software‑engineering background.
• Experience building or extending simulation frameworks.
• Familiarity with discrete‑event or time‑stepped simulation architectures.
• Solid software‑design, debugging, and performance‑optimization skills.

Preferred Qualifications

• Experience with time‑indexed and event‑driven simulation.
• Knowledge of numerical methods or reduced‑order modeling.
• Exposure to data‑pipeline integration.

#LI-VL1

Staff, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab  is looking for  Staff CPU Architecture & Performance Engineer to drive detailed performance analysis and architectural optimization for current and next-generation CPU (RISC-V) cores. This role focuses on deep ownership of performance-critical micro-architectural domains, workload analysis, and data-driven recommendations that influence core architecture decisions.

You will work closely with architects, design, compiler, and system teams to evaluate trade-offs, identify bottlenecks, and improve performance across real-world workloads

 Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42850

• Own performance analysis for one or more CPU microarchitectural domains (e.g., frontend, execution engine, memory subsystem).
• Build, extend, and validate architectural performance models and simulators.
• Perform CPI/IPC breakdowns and root-cause performance bottlenecks.
• Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models.
• Characterize workloads and benchmarks (SPEC, server, client, AI/ML, internal traces).
• Translate performance data into clear architectural recommendations.
• Work leading to patents and publication.

What You Bring

• Master’s in Computer Engineering, Computer Science or related filed with 8+ years of experience or PhD in Computer Engineering, Computer Science, or related field with 5+ years of experience.
• 5+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC-V, ARM or X86 architectures.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Experience analyzing large performance datasets and traces.
• Familiarity with compiler optimizations and hardware/software co-design..
• Proven ability - prior tapeout experience.

Preferred Qualifications

• Background in power/performance/area (PPA) trade-off analysis.
• Experience / Familiarity with SIMD / Vectors / VME for AI inference workloads..
• Prior  leadership guiding junior engineers.
• Prior patent / publication experience. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Job Title: Staff Engineer, AI System Architect (Hardware)

What You’ll Do
The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Senior Staff AI System Architect who will play a key role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42917

• Conduct system-level architectural research for next-generation AI systems, spanning compute, memory, and interconnect/network subsystems.
  • Develop and maintain analytical and simulation-based system modeling frameworks to evaluate AI workloads and identify performance, scalability, and efficiency bottlenecks at rack- and system-scale.
  • Analyze representative and emerging AI workloads (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power.
  • Drive architecture-level design decisions through quantitative modeling, design-space exploration, and performance/power projections.
  • Perform comparative studies of alternative system architectures, reporting performance and performance-per-watt metrics to guide strategic technology choices.
  • Collaborate closely with cross-functional teams in hardware architecture, memory, interconnect, and system engineering to align modeling insights with implementation realities.
  • Communicate architectural insights and recommendations through clear technical presentations and documentation.
  • Occasional domestic and international travel (<10%).

 What You Bring

• Ph.D. in Computer Science, Electrical Engineering, or a related field, with 5+ years of experience in system architecture for large-scale computing platforms, with a strong focus on AI workloads.
  • Proven hands-on experience developing analytical and event-driven simulation models for system-level performance evaluation.
  • Deep understanding of AI system hardware architectures, including compute, memory hierarchies, and high-performance interconnects.
  • Strong knowledge of modern and emerging AI workloads, including LLMs, DLRMs, and large-scale training and inference systems.
  • Demonstrated ability to translate workload characteristics and modeling results into actionable architectural design decisions.
  • Proficiency in Python, C++, and PyTorch for modeling, analysis, and experimentation.
  • Excellent written, verbal, and presentation communication skills, with the ability to influence technical direction across teams.
  • A collaborative mindset, intellectual curiosity, and resilience in tackling complex, open-ended system-level challenges.  
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build.
• Understanding. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 

#LI-SF1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

Memory IO Lab is part of Samsung’s Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume. Memory IO’s vision is to provide memory interface technology solutions which can be adopted in DDR, LPDDR, GDDR, and more. We are an integral part of Samsung’s paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps.

Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy

What You'll Do

• Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES.
• Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary.
• Ownership of circuit and system specifications.
• Simulate designs with state-of-the-art CAD tools.
• Document designs and simulation results.

What You Bring

• BS 10+ years experience, MS 8+years of experience, PhD 5+ years experience in Electrical Engineering, Computer Science preferred. 
• 5+ years of experience working with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes.
• Prior experience in design of any one of the standard high speed interfaces like DDR, LPDDR, , GDDR, HBM I/O interface.
• Needs to be an expert in providing and understanding layout requirements of high speed circuits.
• Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design.
• Experience working closely with device/process team to define transistor specs
• The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
• Ability to troubleshoot and analyze complex problems.
• Excellent communication (written and verbal) and interpersonal skills
• Experience in high frequency clock distribution design, implementation, and analysis.
• Deep understanding of PPA (performance, power, and area) trade-offs.
• Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools
• Experience on silicon bring-up and automatic measurement using script
• Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus.
• Self-motivated problem-solver with an ability to work well in a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Join Samsung Semiconductor to guide the development and design evaluation of next‑generation semiconductor packages and memory devices. In this role as a Staff Engineer for Mechanical Simulation, you will partner with cross‑functional, multicultural teams to advance innovative packaging solutions, automate simulation workflows, and bridge the gap between numerical predictions and experimental validation.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy with 10-20% of domestic and international travel.

Reports to: Principal Engineer

What You’ll Do

• Perform advanced numerical modeling and simulation to evaluate and improve the performance and reliability of cutting‑edge semiconductor packages and memory devices.
• Provide mechanical and thermal design support throughout package‑ and system‑development stages—from concept and detailed modeling to qualification and reliability testing.
• Apply hands‑on expertise in mechanical and thermal modeling of micro‑electronic components, including interconnects, solder joints, BGAs, and advanced‑packaging architectures.
• Develop and maintain scripts for process automation (Python, MATLAB, or ANSYS APDL) to streamline pre‑processing, simulation, and post‑processing workflows for parametric and sensitivity studies.
• Leverage a solid understanding of semiconductor manufacturing, advanced‑packaging technologies, material properties, and associated design and reliability constraints.
• Design, execute, and interpret validation experiments that correlate and calibrate simulation models with empirical data.
• Contribute effectively both independently and as a member of cross‑functional, cross‑cultural, and globally distributed teams.

What You Bring

• Ph.D. in Mechanical Engineering, Materials Science, Physics, or a related field. (Equivalent combination of a Master’s degree and extensive professional experience also welcomed).
• 10+ years of hands‑on modeling and simulation experience in the high‑tech or semiconductor industry.
• Proven expertise with leading simulation tools such as ANSYS, Abaqus, HyperMesh, and their associated pre‑/post‑processing software.
• Proficiency in thermal‑analysis platforms Flotherm and Icepak, together with related utilities.
• Extensive experience in static and dynamic simulations, covering linear and nonlinear analyses that involve geometric and material non‑
• Deep knowledge of thermal analysis and cooling‑design strategies for advanced packaging solutions.
• In‑depth understanding of advanced semiconductor packaging, interconnect structures, and reliability‑modeling techniques.
• Strong technical‑writing skills, capable of producing clear, comprehensive documentation and communicating complex concepts to both technical and non‑technical audiences.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

Samsung Semiconductor is hiring now for a Staff Engineer, Memory Systems Architecture.  The conventional DRAM failure analysis was physical electrical FA and physical FA. But, in the era of Data center, it is easier to track the field failure information. With this data set, Fault management team’s role is finding DRAM failure mode, abnormality and failure rate projection.

You will be part of an incubation team working on in-field telemetry intended to transform the Customer Quality Experience for Samsung memory products. Fault Management is the future of quality to minimize system downtime within AI/ML hardware deployments and workloads of the future. We analyze trends and patterns from enormous memory fleet telemetry to bucketize failures and perform virtual root-cause analysis. Telemetry analysis helps us design solutions to proactively avoid system downtime. We conduct research and develop both in-house and collaboratively in the industry with the opportunity to publish our findings through whitepapers and conferences. We are looking for innovative and passionate thinkers who can work in a start-up environment and are excited to shape the future of data centers around the world. Join us in our mission!

What You'll Do

• Based on the knowledge of SOC controller and memory operation including RAS feature, find and recommends better solution to mitigate the field DRAM failure rate.
• Needs to communicate better ECC scheme to customers based on Samsung DRAM failure mode(DQ and burst)
• Interface with customers to establish the value add of enabling in-field fault management architecture
• Contribute to the standardization of DRAM/HBM failure logging in the OCP.
• Propose and develop platform RAS (Reliability Availability Serviceability) algorithms for memory fault management such as page offlining, hPPR and conduct POC with known failure DIMMs in the real server and application.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Job ID: 42886

 What You Bring

• Bachelor’s degree with 10+ years of relevant industry experience, or Master’s with 8+ years or PhD with 5+ years hardware fault management, reliability, data center fleet management experience or related technical field preferred. (Must)
• Knowledge of platform memory subsystem, platform RAS (Reliability Availability Serviceability) such as ECC, page offlining, hPPR and hardware sparing.
• ECC design and verification and reverse engineering experience.
• Understanding on the address mapping between CPU and memory.
• Memory controller register modification.
• Linux kernel commit experience.
• DRAM and HBM failure mode understanding.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

We are looking for a Senior Engineer, RTL Memory Centric Computing.  This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop IP for memory centric computing systems using Verilog, System Verilog and HLS
• Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.
• Collaborate with Verification engineers to design and develop test plans
• Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in microarchitecture and computer architecture
• 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs
• Experience in designing Memory Controller, NOC, Interconnect IP
• Experience in Memory Centric computing IP and  SOC integration
• Experience in AI/ML workloads.
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-VL1

What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design  to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms.

This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design.

• Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm).
• Optimize SRAM designs for performance, power and area (PPA) and yield.
• Develop custom layouts and perform physical design verifications (e.g., DRC, LVS).
• Evaluate trade-offs between speed, power, and area to meet design targets.
• Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification.
• Work with product and test engineers to develop test plans and support silicon bring-up.
• Mentor Junior engineers, providing guidance on SRAM design techniques and best practices.
• Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance.
• Contribute to patents, technical papers, or industry conferences to advance SRAM technology.

What You Bring

• Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. 
•  Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes.
• Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.).
• Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths.
• Familiarity with timing analysis, power analysis, and design for manufacturability (DFM).
• Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc.
• Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks.
• Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams.
• Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond).
• Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling).
• Background in silicon debug and root-cause analysis.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change. 

#LI-SF1

What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Layout to lead the development of next-generation SRAM solutions.

• Lead the development and execution of full-custom SRAM memory layout and sign-off verification flows (including compiler automation where applicable).
• Collaborate closely with circuit designers to translate schematics into efficient, high-performance physical layouts, own floor planning, placement, routing, and tape-out.
• Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power, yield, and manufacturability.
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification.
• Debug and resolve layout issues efficiently, including process-specific challenges in advanced nodes.
• Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques, design-rule compliance, and knowledge sharing.
• Develop automation scripts (Perl, Tcl, SKILL, etc.) to improve productivity.
• Address reliability concerns such as EM/IR drop, soft errors, and process variability. 
• Work cross-functionally with circuit, architecture, verification, and foundry/process teams to ensure first-pass silicon success and support product integration

What You Bring

• Bachelor's degree with 10+ years of experience in custom SRAM, memory compiler and IC physical layout design or master's degree 8+ years of experience strongly preferred. 
• 3 year’s experience in leadership of management role preferred.
• Extensive experience in SRAM layout design in advanced process nodes (e.g., 3nm, 2nm, or below).
• Demonstrated ability to lead, mentor, and manage a team of layout engineers. 
• Strong project management skills to handle complex schedules and cross-functional collaboration. 
• Strong proficiency with industry-standard EDA tools: 
• Candence Virtuoso (or Custom Compiler/IC Compiler) for custom/analog layout. 
• Physical verification tools for DRC/LVS/ERC flows. 
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification. 
• Experience with RC extraction, parasitic reduction, and memory-specific verification. 
• Scripting/automation skills (Perl, Tcl, SKILL, etc.) are highly valued. 
• Proven ability to drive layout quality, constraints, and closure while collaborating in global, cross -functional teams. 
• Prior work on high-speed, low-power SRAM in leading-edge nodes preferred. 
• Mentoring or technical leadership experience preferred. 
• Understanding of SRAM architecture, timing, power analysis, and yield optimization preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are looking for a dynamic, self-motivated, experienced engineer to architect and lead functional test coverage and test methodologies for NVMe SSDs.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Manage Enterprise server infrastructure, execute Customer Qual tests and debug failures
• Execution of enterprise SSD qualifications in customer systems.
• Communicate with team lead to understand qualification processes and test plans. Report status of qualifications and manage customer expectations.
• Coordinate  with internal team and customer test engineers to execute qual plans as per schedule. Teams will be both local and remote.
• Triage test failures and do a first level FA. Design and execute experiments to root cause defects and verify fixes in coordination with development teams.
• Provide feedback to functional test teams on issues seen in customer quals to better functional test coverage.
• Contribute in Triaging customer field issues and provide support for timely resolution of customer issues.
• Identify automation opportunities and help Automation team to continue to improve and add to the existing framework.

What You Bring

• BS in Computer Science or related technical field with 10+ years of system level testing or development of enterprise servers and enterprise storage systems experience or MS with 8+ years preferred.
• Experience with at least storage protocol like NVMe/PCIe, SAS, SATA, Fibre Channel
• Familiar with one of protocol analyzers like LeCroy, SerialTek, or Xgig System or device level performance analysis
• Proficiency in server operating systems especially system debug tools such as system logs.
• Knowledge of enterprise storage/server system technologies.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, Test execution and bug management tools.
• Scripting experience such as in Perl, Shell or Python
• Experience with SSD or HDD testing
• NetApp/HPE/Dell/IBM System Experience
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop black-box functional test coverage and test methodologies for NVMe SSD's.
• Debug, triage failures and work with FW Team to reproduce problems, design and run experiments.
• Analyze customer field issues and improve Functional test coverage where gaps are identified.
• Provide guidance to the Automation team and assist with test coverage integration into the existing framework.
• Must be able to work with local US and international customers and OEMs.

What You Bring

• Bachelors and 10+ yrs, Masters and 8+ yrs’ with focus in Computer Science, Computer Engineering, Electrical Engineering or equivalent.
• Strong programming experience, demonstrated proficiency in scripting languages such as Python, Bash, Linux shell scripts etc.
• Excellent verbal and written communication skills.
• Ability to work individually and in teams.
• Prior NVMe, PCIe knowledge or experience with one or more of the following storage-related technologies: NVM Express, PCI Express, NAND Flash/FTL .
• Knowledge of Enterprise storage/server systems, and proficiency in Linux.
• Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, test execution and bug management tools.
• Relevant hands-on experience in embedded software or firmware development/testing, including storage devices or other embedded platforms.
• Familiarity and experience with agile development methodologies and practices, particularly in AI/ML-focused environments, is preferred.
• Hands-on experience with PCI protocol analyzers.
• Demonstrated ability to work as a team player, as part of a local and globally distributed team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

We are currently seeking a Thermal Engineer. The position will be responsible for the thermal analysis and validation of thermal technologies for Samsung advanced semiconductor products. The ideal candidate will have a strong fundamental background in heat transfer, fluid dynamics, and thermal simulation with the implementation of thermal solutions in enterprise electronics.

Location: Daily onsite presence at our San Jose, CA in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

What You’ll Do

• Develop reduced-order thermal models and rapid thermal analysis methods to guide  architecture and development of memory products.
• Execute high-fidelity and comprehensive thermal analysis and data validation at both the semiconductor component and system levels.
• Provide rapid steady-state and transient simulation solutions for semiconductor products.
• Collaborate with cross-functional internal teams and external partners to resolve complex thermal challenges.

What You Bring

• Bachelors degree in Mechanical Engineering (or related Physical Science) with 5+ years of experience or Masters degree Mechanical Engineering (or related Physical Science) with 3+ years of experience preferred.
• Proven self-discipline and professional maturity to execute independent research and meet rigorous milestones with a strong sense of accountability for both personal and collective goals in a fast-paced, on-site environment.
• Deep knowledge and experience in Thermal Engineering.
• Expertise in FloTHERM and familiarity with other CFD tools.
• Excellent technical writing and verbal communication skills for collaboration, documentation, and presentations. 

Preferred Qualifications:

• Fundamental understanding of IC chip/package architectures and thermal design constraints.
• Working experience in SiP (System in Package) thermal analysis.
• PhD degree in Thermal Engineering. 
• Minimum of 2 years of direct industry experience preferred.
• Familiarity with Artificial Intelligence applications.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high-speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

itD is seeking a Diagnostic Software Engineer to design, develop, and validate embedded diagnostic solutions that support system reliability, performance, and hardware-software integration. The ideal candidate will bring deep experience in embedded systems development and low-level programming, along with a proven track record of debugging complex hardware/software interactions and delivering high-quality, production-ready solutions.

Location: Hybrid – 4 days onsite (5 days as needed) in San Jose, CA
Pay Range: $34 - $34.61 (hourly)

We provide comprehensive medical benefits, a 401k plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship.

Responsibilities:

• Develop and maintain embedded diagnostic software for hardware systems and device drivers
• Debug and resolve complex issues across hardware and software layers, including kernel and application levels
• Validate and test embedded systems to ensure reliability, performance, and compliance with requirements
• Collaborate with cross-functional teams to support hardware bring-up and system integration
• Implement and support communication protocols such as I2C, SPI, UART, PCIe, and GPIO
• Analyze system performance and troubleshoot defects using kernel-level debugging tools
• Contribute to continuous improvement of development and validation processes

Internal Responsibilities:

• Attend regular internal practice community meetings.
• Collaborate with your itD practice team on industry thought leadership.
• Complete client case studies and learning material (blogs, media material).
• Build out material to contribute to the Digital Transformation practice.
• Attend internal itD networking events (in person and virtual).
• Work with leadership on career fast-track opportunities.

Required Qualifications and Skills:

• Proficient in C programming
• Experience with hardware and device driver development, including Linux hardware bring-up
• Experience developing, debugging, and validating embedded systems and device drivers
• Hands-on experience with protocols such as I2C, SPI, UART, PCIe, and/or GPIO

Preferred Qualifications and Skills:

• Experience troubleshooting software defects from kernel modules to applications
• Familiarity with Layer 2/3 network protocols
• Proficiency with kernel debugging tools such as GDB and KGDB

Education:

• Bachelor’s degree in a relevant field or equivalent work experience required

What You’ll Do:

• Design a wide array of structural components and integration of flight-critical electromechanical actuation systems from concept through experimental  flight testing
• Design mechanisms and own kinematic layouts for flight control systems
• Design detailed metallic parts and assemblies to support actuation and propulsion integration
• Own the prototype development process; requirements, design, BOM, procurement, assembly, test, etc.
• Perform initial  structural analysis and hand calculations to verify component margins, load paths, and interface requirements
• Interface with suppliers to select COTS solutions where appropriate (mounts, fasteners, brackets, etc.)
• Create and review technical drawings, plans, and specifications
• Support requirements development and documentation
• Collaborate with our multi-disciplinary engineering team

What You Need:

• 5+ years of engineering experience
• Bachelor's degree in Mechanical Engineering
• Exposure to integrating or designing flight critical systems
• Proficient in CAD (Solidworks, NX, etc.) - NX preferred
• Ability to manage CAD and complex assemblies  in Team Center
• Proficient in load analysis, free body diagrams, and FEA
• Experience designing complex metallic parts and weldments
• Fluent in GD&T and creating manufacturing drawings
• Familiarity with aerospace hardware standards
• Hands-on experience in multiple technical fields especially those related to carbon composite and metallic structures
• Ability to communicate effectively and clearly

Bonus Qualifications:

• Bachelor’s degree in Aerospace, Mechanical, or Electrical Engineering (or equivalent)
• Knowledge of, and experience within, electric powertrain systems or aerospace systems.
• Familiarity with simscape
• Experience designing mechanisms for flight control systems
• Thorough understanding of electro-mechanical actuators 
• Thorough understanding of engineering product development including design phases, manufacturing processes and global supply chain management.
• Familiarization with Atlassian Jira and Confluence for task management and collaborative documentation.
• Experience supporting vehicle development from concept/prototype aircraft phase through certification and mass production
• Part 23 Certification Experience and/or experience working with ARP4754A.

At Archer, we aim to attract, retain, and motivate talent with the skills and leadership needed to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s strategy. For this position, we are targeting a base pay range of $144,000 - $198,000. Actual compensation offered will be determined by job-related knowledge, skills, and experience.        
                

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

What You’ll Do:

As a strong AI and ML fundamentalist who is an expert at developing cutting-edge AI solutions to complex problems, you will develop code that eventually integrates into production and be responsible for:

• Design, implement, and evaluate novel machine learning and deep learning algorithms.
• Iterate on AI model development; starting from the data needed for training, architecture, input/output representations, evaluation, and deployment. 
• Collaborate with other researcher engineers to prototype and validate complex solutions from academic literature.
• Conduct experiments to benchmark new techniques and evaluate model behavior.
• Develop tools and frameworks to support scalable and reproducible research and development.
• Communicate research findings to leadership in a concise, and convincing manner.
• Stay current with the latest developments in AI/ML and identify relevant innovations.
• Assist in transitioning research prototypes into production-ready systems.

What You Need:

• M.S or PhD degree in Computer Science, or Computer Engineering with strong emphasis on AI and ML.
• Enjoys solving less-defined and complex problems
• Familiarity with good SW practices and development, including code quality, version control, etc.
• Very strong with ML frameworks such as Pytorch, or Tensorflow
• Good understanding of Transformer architectures, attention mechanisms, multi-modal foundation models, diffusion policies, fine-tuning, model distillation, mixture of experts, and other similar topics.
• Has strong ability to debug and determine requirements for AI models in terms of data, training, and evaluation.
• Is up to date with research literature and recent ML techniques and methodologies.

Bonus Qualifications:

• Experience with Reinforcement Learning, self-supervised training, and imitation learning is a plus.
• Experience developing VLA (Vision Language Action) models for robotic manipulation and mobility is a plus.
• Experience developing production AI models is a plus.
• Publications at top conferences are a plus.

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $160,000.00 - $180,000.00 Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is proud to be an Equal Opportunity employer committed to diversity and inclusivity in the workplace. All aspects of employment are decided on the basis of merit, qualifications, and business needs. We do not discriminate based upon race, color, religion, sex, sexual orientation, age, national origin, disability status, protected veteran status, gender identity or any other characteristic protected by federal, state or local laws.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

What You’ll Do:

As a Staff AI and ML fundamentalist who is an expert at developing cutting-edge AI solutions to complex problems, you will develop code that eventually integrates into production and be responsible for:

• Design, implement, and evaluate novel machine learning and deep learning algorithms.
• Iterate on AI model development; starting from the data needed for training, architecture, input/output representations, evaluation, and deployment. 
• Collaborate with other researcher engineers to prototype and validate complex solutions from academic literature.
• Conduct experiments to benchmark new techniques and evaluate model behavior.
• Develop tools and frameworks to support scalable and reproducible research and development.
• Communicate research findings to leadership in a concise, and convincing manner.
• Stay current with the latest developments in AI/ML and identify relevant innovations.
• Assist in transitioning research prototypes into production-ready systems.

What You Need:

• M.S or PhD degree in Computer Science, or Computer Engineering with strong emphasis on AI and ML.
• Enjoys solving less-defined and complex problems
• Familiarity with good SW practices and development, including code quality, version control, etc.
• Very strong with ML frameworks such as Pytorch, or Tensorflow
• Good understanding of Transformer architectures, attention mechanisms, multi-modal foundation models, diffusion policies, fine-tuning, model distillation, mixture of experts, and other similar topics.
• Has strong ability to debug and determine requirements for AI models in terms of data, training, and evaluation.
• Is up to date with research literature and recent ML techniques and methodologies.

Bonus Qualifications:

• Experience with Reinforcement Learning, self-supervised training, and imitation learning is a plus.
• Experience developing VLA (Vision Language Action) models for robotic manipulation and mobility is a plus.
• Experience developing production AI models is a plus.
• Publications at top conferences are a plus.

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $190,000 - $240,000 Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is proud to be an Equal Opportunity employer committed to diversity and inclusivity in the workplace. All aspects of employment are decided on the basis of merit, qualifications, and business needs. We do not discriminate based upon race, color, religion, sex, sexual orientation, age, national origin, disability status, protected veteran status, gender identity or any other characteristic protected by federal, state or local laws.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

What we do  

You’ll join a software engineering team building internal AI solutions that support teams across The Trade Desk. We leverage large language models, retrieval‑augmented generation (RAG), agentic systems, and enterprise platforms like Microsoft Copilot and Anthropic Claude to improve productivity, streamline workflows, and reduce operational friction.

Our team also plays a key role in AI enablement across the company—supporting teams as they adopt Copilot, Claude and similar tools, designing and deploying custom AI agents, and guiding partners through their AI journey from idea to impact.

As a Senior AI Engineer on this team, you’ll be an end-to-end owner—collaborating closely with stakeholders, identifying opportunities, and delivering tools that make a real impact. We’re a nimble, fast-paced, and highly collaborative group that thrives on transforming the way teams operate and driving greater value across The Trade Desk.

What you’ll do: 

Some of the work that you will be doing to help us deliver on our mission is:

• Design and deploy intelligent agentic systems that integrate large language models (LLMs) with enterprise data, tools, and workflows using frameworks like LangChain, LlamaIndex, and Semantic Kernel.
• Develop Retrieval-Augmented Generation (RAG) applications using tools like Azure AI Search, vector databases, and secure enterprise connectors to deliver contextual insights.
• Build and deploy agents using Microsoft Copilot, Copilot Studio, Anthropic Claude, and similar platforms to help teams operationalize solutions within enterprise guardrails.
• Build and iterate on conversational agents that solve real-world problems, meet stakeholder needs, and deliver measurable business value.
• Deliver high-impact features by collaborating across teams, leading through ambiguity, and aligning technical solutions with business goals.
• Drive quality and performance through automated testing, monitoring, and data-driven evaluation of success criteria, user adoption, and operational efficiency.
• Mentor teammates and contribute to a culture of innovation, technical excellence, and continuous learning.

Who you are: 

• You have a Bachelor’s/Master’s level degree in computer science or relevant engineering-related field or equivalent experience.
• You have 8-10+ years of software engineering experience, including 1-2+ years working on AI-powered systems or products.
• You are proficient in Python and comfortable with additional languages such as C#, SQL, or TypeScript/React.
• You’re excited about AI enablement, including helping teams adopt platforms like Microsoft Copilot, Anthropic Claude and Copilot Studio, building agents, and guiding others through their AI journey.
• You have a good foundational knowledge of or hands-on experience with LLM orchestration frameworks (e.g., LangChain, LlamaIndex, Semantic Kernel) and prompt engineering using LLM APIs.
• You have experience productionizing applications and implementing CI/CD pipelines to ensure reliable, scalable deployments.
• You are skilled in data ingestion and transformation using APIs, ETL pipelines, and connectors, and familiar with vector databases and retrieval strategies.
• You communicate clearly across technical and non-technical audiences and thrive in a collaborative, cross-functional environment.
• You are a fast learner who adapts quickly to new technologies and solves complex problems with creativity and pragmatism.

#LI-TP1

A variety of technical opportunities is one of the best things about working at The Trade Desk as a software engineer, which is why we do not expect you to know every technology we use when you start. What we care about is that you can learn quickly and find solutions to complex problems using the optimum tools for the job. What you know is less important than how well you learn and innovate. We are not seeking engineers who know all the answers; we need engineers who can invent answers no one has thought of yet and find answers to the questions yet to be asked. 

The Trade Desk does not accept unsolicited resumes from search firm recruiters. Fees will not be paid in the event a candidate submitted by a recruiter without an agreement in place is hired; such resumes will be deemed the sole property of The Trade Desk. The Trade Desk is an equal opportunity employer. All aspects of employment will be based on merit, competence, performance, and business needs. We do not discriminate on the basis of race, color, religion, marital status, age, national origin, ancestry, physical or mental disability, medical condition, pregnancy, genetic information, gender, sexual orientation, gender identity or expression, veteran status, or any other status protected under federal, state, or local law.

[LA JOBS ONLY] The Trade Desk will consider qualified applicants with criminal histories for employment in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring, Ordinance No. 184652.

[SF JOBS ONLY] Pursuant to the San Francisco Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

#LI-TP1

What You’ll Do:

As a Principal AI and ML fundamentalist who is an expert at developing cutting-edge AI solutions to complex problems, you will develop code that eventually integrates into production and be responsible for:

• Design, implement, and evaluate novel machine learning and deep learning algorithms.
• Iterate on AI model development; starting from the data needed for training, architecture, input/output representations, evaluation, and deployment. 
• Collaborate with other researcher engineers to prototype and validate complex solutions from academic literature.
• Conduct experiments to benchmark new techniques and evaluate model behavior.
• Develop tools and frameworks to support scalable and reproducible research and development.
• Communicate research findings to leadership in a concise, and convincing manner.
• Stay current with the latest developments in AI/ML and identify relevant innovations.
• Assist in transitioning research prototypes into production-ready systems.

What You Need:

• M.S or PhD degree in Computer Science, or Computer Engineering with strong emphasis on AI and ML.
• Enjoys solving less-defined and complex problems
• Familiarity with good SW practices and development, including code quality, version control, etc.
• Very strong with ML frameworks such as Pytorch, or Tensorflow
• Good understanding of Transformer architectures, attention mechanisms, multi-modal foundation models, diffusion policies, fine-tuning, model distillation, mixture of experts, and other similar topics.
• Has strong ability to debug and determine requirements for AI models in terms of data, training, and evaluation.
• Is up to date with research literature and recent ML techniques and methodologies.

Bonus Qualifications:

• Experience with Reinforcement Learning, self-supervised training, and imitation learning is a plus.
• Experience developing VLA (Vision Language Action) models for robotic manipulation and mobility is a plus.
• Experience developing production AI models is a plus.
• Publications at top conferences are a plus.

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $270,000.00 - $340,000.00 Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is proud to be an Equal Opportunity employer committed to diversity and inclusivity in the workplace. All aspects of employment are decided on the basis of merit, qualifications, and business needs. We do not discriminate based upon race, color, religion, sex, sexual orientation, age, national origin, disability status, protected veteran status, gender identity or any other characteristic protected by federal, state or local laws.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.