Role

We are looking for a Sr Staff Software Development Engineer to join our ZPA datapath team. This is a hybrid role based in San Jose (3 days in office), reporting to the Director, Engineering. As a core technical expert, you will drive the design, development, and optimization of critical network applications and protocols. You will leverage your deep expertise in C/C++ and Linux to build scalable, high-performance network solutions that secure and streamline enterprise data across cloud environments.

What you’ll do (Role Expectations)

• Develop and optimize network applications and protocols using C/C++
• Design efficient data structures for network data processing and handle system-level programming in Linux environments
• Analyze network performance to identify issues and implement optimization solutions
• Collaborate with teams to define requirements, design architectures, and integrate network solutions
• Conduct code reviews, testing, and debugging to ensure robust and reliable software

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.
• You operate with urgency. You understand that in a high-growth environment, speed and quality are not mutually exclusive. You have a relentless focus on execution and a bias for action, delivering high-impact results quickly to win for the customer and the team.
• You are a problem-solver. You seek out challenges because you are energized by finding solutions, knowing that solving the hard problems delivers the biggest impact.
• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.
• You lead with integrity. You do the right thing, even when it’s hard. You hold yourself and others to a high standard of accountability and build trust by matching your words with consistent, transparent action.

What We’re Looking for (Minimum Qualifications)

• 8+ years of experience in a distributed and enterprise-scale environment
• Strong knowledge of C programming specifically for network-related data handling and processing
• Expertise in Linux environments, including system-level programming, scripting, and troubleshooting
• Experience with networking protocols and traffic management technologies (e.g. TCP/IP, HTTP/HTTPS, SSL/TLS, QUIC)
• Strong knowledge in one of the cloud platforms like AWS, Azure, or GCP

What Will Make You Stand Out (Preferred Qualifications)

• Experience in L3 protocols, routing, BGP
• Experience in Cloud-based Networking
• Ability to stay current with industry trends and propose enhancements to improve system reliability, scalability, and network efficiency

#LI-YC2 #LI-Hybrid

About the Company

DiDi's autonomous driving unit was established in 2016 with the mission of developing Level 4 autonomous driving (AD) technology to make transportation safer and more efficient. In August 2019, the unit became an independent company, DiDi Autonomous Driving, dedicated to advanced AD R&D, product application, and business expansion. We believe integrating AD technology into a shared-mobility fleet will generate immense social value. By leveraging DiDi's specialized technology, operational expertise, and integrated ecosystem, we are positioned to build and operate a highly efficient, user-oriented autonomous fleet.

• Perform optimization on simulation software under the guidance of profiler.
• Identify and resolve algorithm deficiencies that affects simulation determinism.
• Implement new simulation capabilities that fits new hardware.

• PhD, Master’s students or senior undergraduate students majoring in Computer Science or a related field.
• Strong C++ development skills with experience in performance-critical applications.
• Deep understanding of computer architecture.
• Great communication skills that fosters cross-team collaboration.
• Familiarity with robotics (perception, motion planning) is a plus.
• Experience with GPU/CUDA programming is a bonus.
  

The hourly rate for the Intern position in the selected city is $46.

I acknowledge that prior to submitting this application, I have read and accepted the Privacy Notice for California Residents which is available on https://v.didi.cn/AQnxlBa

About The Company

DiDi's autonomous driving unit was established in 2016 with the mission of developing Level 4 autonomous driving (AD) technology to make transportation safer and more efficient. In August 2019, the unit became an independent company, DiDi Autonomous Driving, dedicated to advanced AD R&D, product application, and business expansion. We believe integrating AD technology into a shared-mobility fleet will generate immense social value. By leveraging DiDi's specialized technology, operational expertise, and integrated ecosystem, we are positioned to build and operate a highly efficient, user-oriented autonomous fleet.

About The Role

We are seeking a Software Engineer /Sr. Software Engineer to join our team and develop the core decision-making and motion planning systems for our autonomous vehicles. In this role, you will be responsible for creating the algorithms that enable smooth, safe, and intelligent navigation in complex environments. You will tackle challenges across the full motion planning stack, from high-level behavioral reasoning to low-level trajectory optimization.

Responsibilities

• Design and implement the core Behavioral Planning logic that determines the vehicle's high-level actions (e.g., lane changes, merges, yields, and interactions with other agents).
• Develop and optimize the motion planning algorithms that execute behavioral decisions, integrating Geometry Reasoning (path) and Speed Reasoning (velocity) into a cohesive trajectory.
• Architect and enhance the geometry system for generating geometrically feasible and compliant paths.
• Architect and refine the velocity system for generating context-aware, comfortable, and safe velocity profiles.
• Model complex driving scenarios and agent interactions to create a robust world model for the behavioral planner.
• Design different costs for trajectory ranking to trade off ETAs, comfort and safety of the vehicle behaviors.
• Conduct in-depth analysis, testing, and debugging of the system's performance in various scenarios, leading root cause investigations.
• Collaborate with Prediction, Perception, and Control teams to ensure a seamless flow from environmental understanding to physical vehicle motion.
  
  

Qualifications

• B.S./M.S. in Computer Science, Robotics, or a related field.
• Experience in autonomous systems, robotics, or automotive software development.
• Strong proficiency in C++ for implementing complex, real-time algorithms.
• Solid understanding of robotics fundamentals, including decision-making, motion planning, control theory, trajectory ranking, search and optimization algorithms etc.
• Related experience in one or more of the following: behavioral planning, motion planning, behavior and world environment reasoning, trajectory ranking and cost design.
  
  

Preferred Qualifications

• PhD or internship experience related to robotics planning system designs.
• Knowledge of vehicle dynamics and longitudinal/lateral control systems.
• Solid understanding of machine learning principles, reinforcement learning and related algorithms.
  
  

The base salary range for this position is $129,189-$214,776 for Software Engineer and $148,594-247,038 for Sr. Software Engineer, annually in addition to bonus, equity and benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

I acknowledge that prior to submitting this application, I have read and accepted the Privacy Notice for California Residents which is available on https://v.didi.cn/AQnxlBa

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop and maintain highly interactive, large-scale and complex web-based visual analytics tools on AI/ML workloads.
• Design and implement creative and performant visualizations to assist in diagnosing issues or uncovering optimization opportunities in AI/ML inference and serving.
• Collaborate closely with hardware architects and compiler engineers to define, design, and implement effective visualization solutions enhancing their workflow.
• Develop high-performance visualization workflows by integrating independent graphics modules with micro-services to handle asset optimization, ensuring a non-blocking experience on the client.
• Continuously seek improvements to existing tools and develop new approaches to meet fast-evolving requirements.
• Stay up-to-date with the latest advancements in web development and visualization techniques.
• Contribute to the development of the documentation and user guides.
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• An innate drive to clarify deep technical complexity, balancing creative visualization with engineering rigor to build analytical tools that make interdependent hardware and software models intuitive without sacrificing logical precision.
• Strong experience in full-stack visual analytics software development, with a focus on building scientific or infrastructure visualization tools. Experience in AI model visualization integrated with PyTorch is a plus.

• Strong proficiency in modern frontend technologies like React and backend technologies like Node.js or Python-based frameworks. Experience in graph-based UI is a plus.
• Proven experience in WebGL/WebGPU based frameworks such as three.js or deck.gl. GLSL experience is a plus. Experience in WebAssembly with C++ is a plus.
• Excellent problem-solving skills and ability to think critically and creatively.

• Excellent communication and interpersonal skills.
• Ability to work independently and as part of a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

Role

We are looking for a Staff Software Development Engineer - DevSecOps to join our team in a hybrid capacity in San Jose, CA, reporting to the Director, Software Development Engineering. Our Engineering team built the world’s largest cloud security platform from the ground up, and we keep building. You will support internal product teams in managing CI/CD pipelines, strengthening security practices, and maintaining shared engineering systems to enable organizations worldwide to harness speed and agility with a cloud-first strategy.

What you’ll do (Role Expectations)

• Build and manage CI/CD systems to deploy critical applications across hybrid cloud environments including AWS, GCP, and proprietary clouds

• Support internal product teams with CI/CD pipelines, automations, and tools like GitLab, GitHub, Jenkins, ArgoCD, and security scanning solutions

• Secure code, applications, and infrastructure using security scanning tools such as SonarQube, Snyk, Coverity, and CheckMarx

• Administer and optimize critical DevSecOps applications while monitoring build metrics with tools like Grafana, Prometheus, and CloudWatch

• Communicate progress to stakeholders through Jira, technical documentation, and clear status updates

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.

• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.

• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.

• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.

• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• 5+ years of professional experience including hands-on experience managing cloud environments such as AWS, GCP, or private clouds

• Proficiency in application development or automation using OOP languages like C/C++, Java, Python, or Go, plus exposure to container orchestration and automation tools

• Familiarity with application security testing methodologies and experience using tools like SonarQube, Snyk, Coverity, or CheckMarx

• Experience designing and managing GitOps-based pipelines using GitLab, GitHub, and CI/CD automation tools like Jenkins or GitHub Actions

• Bachelor’s degree in Computer Science or a related field, or equivalent practical experience

What Will Make You Stand Out (Preferred Qualifications)

• Experience with AI and ML tools in day to day DevSecOps activities

• Experience writing and developing yaml based CI/CD Pipelines and knowledge of build tools like makefiles, gradle, npm, or maven

• Experience with Networking, Load Balancers, Firewalls, and Web Security

#LI-Hybrid #LI-KM9

What You’ll Do

Samsung Display’s America R&D Lab is hiring for a Senior Systems Engineer, for a knowledgeable, self-driven individual contributor in field of display metrology and standardization. Our lab works closely with Samsung Display Co. (SDC), which supplies premium displays for smartphones, laptops, monitors, and TVs using industry leading technology. SDC is the first company in the world to mass produce flexible OLEDs, foldables and QD displays, creating the best displays that connect technology and people in a more valuable way.

This role is part of a dedicated team within a large global organization, advancing display metrology, product certifications, and standardization through collaboration with diverse stakeholders to deliver outcomes that directly impact company products.

This is an unique opportunity for a grounded, adaptable professional who is comfortable filling the gap, bringing patience and expertise to shape display eco-system over time.

We believe that innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy with 10-20% of domestic and international travel.

Reports to: Principal Engineer

• Develop industry-leading test methodology and solutions
• Develop display-related standards, ensure alignment with organizations, e.g: VESA, ICDM, SMPTE
• Compare and analyze display performance to standardization targets, and recommend actions.
• Develop display metrology test patterns and test protocols; propose to IEC and ICDM as appropriate.
• Publish in peer-reviewed papers, conferences, and industry magazines that advances the display ecosystems.
• Communicate complex technical concepts clearly and effectively to diverse audience..
• Complete other responsibilities as assigned.

What You Bring

• Minimum of Master’s of Science degree in Physics, Electrical, Optics, or Materials Engineering or related field OR PhD is preferred.
• 3-5 years of relevant industry experience.
• Required expertise with display metrology and related instruments (ie. Spectrometer, colorimeter)
• Experience in Python, Matlab (Octave), or C++
• Conversant with industry forums and standardization procedures is a strong plus.
• Travel internationally several times a year, such as conference presentation, internal standard meetings.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-MD1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD's with 10+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop the verification infrastructure and automation environment involved in build, simulation, regression and triages.
• Lead the verification for IP blocks of an AI accelerator by working with architects and RTL engineers.
• Create direct or random testbench, define verification scope and test plans for both functional and performance validation, close the verification quality metrics.
• Provide comprehensive documentation of verification strategy and ensure test environment is easy to use.
• Mentor junior engineers when necessary
• Work cross-functionally in debugging failures with design, compiler and simulation engineers

What You Bring

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• Strong background in SoC or IP verification and test bench development using UVM, System Verilog, C/C++ and scripting languages such as Perl/Python.
• Experience verifying at multiple levels of logic from scratch, starting from complex IP blocks to dies to SoCs to full system testing
• Understanding RTL and strong overall debugging skills
• Prior experience with computational logic, interconnect networks and/or memory system is desirable
• Strong background in microarchitecture and computer architecture preferably in the area of AI accelerators
• Knowledge of FPGA and emulation platforms preferred
• Strong analytical and problem-solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

#LI-VL1

Job Title: Staff Engineer, AI System Architect (Hardware)

What You’ll Do
The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Senior Staff AI System Architect who will play a key role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42917

• Conduct system-level architectural research for next-generation AI systems, spanning compute, memory, and interconnect/network subsystems.
  • Develop and maintain analytical and simulation-based system modeling frameworks to evaluate AI workloads and identify performance, scalability, and efficiency bottlenecks at rack- and system-scale.
  • Analyze representative and emerging AI workloads (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power.
  • Drive architecture-level design decisions through quantitative modeling, design-space exploration, and performance/power projections.
  • Perform comparative studies of alternative system architectures, reporting performance and performance-per-watt metrics to guide strategic technology choices.
  • Collaborate closely with cross-functional teams in hardware architecture, memory, interconnect, and system engineering to align modeling insights with implementation realities.
  • Communicate architectural insights and recommendations through clear technical presentations and documentation.
  • Occasional domestic and international travel (<10%).

 What You Bring

• Ph.D. in Computer Science, Electrical Engineering, or a related field, with 5+ years of experience in system architecture for large-scale computing platforms, with a strong focus on AI workloads.
  • Proven hands-on experience developing analytical and event-driven simulation models for system-level performance evaluation.
  • Deep understanding of AI system hardware architectures, including compute, memory hierarchies, and high-performance interconnects.
  • Strong knowledge of modern and emerging AI workloads, including LLMs, DLRMs, and large-scale training and inference systems.
  • Demonstrated ability to translate workload characteristics and modeling results into actionable architectural design decisions.
  • Proficiency in Python, C++, and PyTorch for modeling, analysis, and experimentation.
  • Excellent written, verbal, and presentation communication skills, with the ability to influence technical direction across teams.
  • A collaborative mindset, intellectual curiosity, and resilience in tackling complex, open-ended system-level challenges.  
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build.
• Understanding. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 

#LI-SF1

Staff, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab  is looking for  Staff CPU Architecture & Performance Engineer to drive detailed performance analysis and architectural optimization for current and next-generation CPU (RISC-V) cores. This role focuses on deep ownership of performance-critical micro-architectural domains, workload analysis, and data-driven recommendations that influence core architecture decisions.

You will work closely with architects, design, compiler, and system teams to evaluate trade-offs, identify bottlenecks, and improve performance across real-world workloads

 Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42850

• Own performance analysis for one or more CPU microarchitectural domains (e.g., frontend, execution engine, memory subsystem).
• Build, extend, and validate architectural performance models and simulators.
• Perform CPI/IPC breakdowns and root-cause performance bottlenecks.
• Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models.
• Characterize workloads and benchmarks (SPEC, server, client, AI/ML, internal traces).
• Translate performance data into clear architectural recommendations.
• Work leading to patents and publication.

What You Bring

• Master’s in Computer Engineering, Computer Science or related filed with 8+ years of experience or PhD in Computer Engineering, Computer Science, or related field with 5+ years of experience.
• 5+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC-V, ARM or X86 architectures.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Experience analyzing large performance datasets and traces.
• Familiarity with compiler optimizations and hardware/software co-design..
• Proven ability - prior tapeout experience.

Preferred Qualifications

• Background in power/performance/area (PPA) trade-off analysis.
• Experience / Familiarity with SIMD / Vectors / VME for AI inference workloads..
• Prior  leadership guiding junior engineers.
• Prior patent / publication experience. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The engineer develops and extends the trace‑driven power/thermal simulation engine, integrating power macromodels, workload traces, and thermal solvers into a coherent, scalable simulation flow.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

What You’ll Do

• Implement and optimize trace‑driven power and thermal simulation engines.
• Integrate IP‑level power macromodels into system‑level simulation.
• Manage a time‑indexed simulation flow across power and thermal domains.
• Generate transient power maps and perform spatiotemporal hotspot analysis.
• Interface with reduced‑order thermal models and CFD‑calibrated solvers.
• Ensure simulation performance, scalability, and reproducibility.

What You Bring

• Bachelors degree 5+ years of experience or Masters degree 3+ years of experience.
• Strong C++ software‑engineering background.
• Experience building or extending simulation frameworks.
• Familiarity with discrete‑event or time‑stepped simulation architectures.
• Solid software‑design, debugging, and performance‑optimization skills.

Preferred Qualifications

• Experience with time‑indexed and event‑driven simulation.
• Knowledge of numerical methods or reduced‑order modeling.
• Exposure to data‑pipeline integration.

#LI-VL1

Job Title: Principal engineer, AI Serving Framework Architect (Software)

What You’ll Do    

The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a key role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42853

• As a Tech Lead, leading research teams in Korea and proposing technical direction
• Research on dynamic scheduling methodologies for maximizing AI inference performance in multi-rack scale memory-centric systems, comprised of heterogeneous compute-capable memory and hierarchical memory
• Investigating methods to accelerate search operations in RAG’s vector DB and AI Agent’s knowledge-graph by leveraging compute-capable memory
• Studying strategies for optimally placing KVCache and a vector DB in hierarchical memory to minimize frequent SSD accesses and reduce IO stalls
• Proposing SW design for implementing the derived optimization algorithms on open-source platforms such as vLLM

What You Bring

• PhD in Computer Science or a related field with 10+ years of experience in AI Serving Framework for large-scale computing, with focusing on the AI workloads. 
• Led a project to build and optimize a Large Language Model (LLM) Inference Software Stack on a multi-rack scale system to deliver AI Inference services to over 100,000 users. 
• Extensive experience in designing AI Inference Software Stacks for heterogeneous devices.In-depth understanding of the internal architecture and operation mechanisms of inference engines such as vLLM. 
• Proficiency in AI Inference System Profiling and optimization. 
• Knowledge and practical experience with future AI workloads, including reasoning models, multi-modal solutions, AI agents, and world models. 
• Strong understanding of compute, memory, and networking bottlenecks in AI systems. 
• Required skillsets: PyTorch, Python, and C++ 
• A collaborative mindset, curiosity, and resilience in solving complex challenges. 
• Excellent verbal, presentation, and written communication skills. 
• (Nice to have) Native or fluent Korean speakers are preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build. Understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change 

#LI-SF1

Job Title: Principal Engineer, AI System Architect (Hardware)

 What You’ll Do
The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a Technical Lead role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42852

• • Technically Lead the architecture team with strong  direction, shaping system‑architecture strategy and advancing key innovations
  • Conduct system-level architectural research for next-generation AI systems, spanning compute, memory, and interconnect/network subsystems.
• Develop and maintain analytical and simulation-based system modeling frameworks to evaluate AI workloads and identify performance, scalability, and efficiency bottlenecks at rack- and system-scale. 
• Analyze representative and emerging AI workloads (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power.  
• Drive architecture-level design decisions through quantitative modeling, design-space exploration, and performance/power projections. 
• Perform comparative studies of alternative system architectures, reporting performance and performance-per-watt metrics to guide strategic technology choices. 
• Collaborate closely with cross-functional teams in hardware architecture, memory, interconnect, and system engineering to align modeling insights with implementation realities.  
• Communicate architectural insights and recommendations through clear technical presentations and documentation.   
• Occasional domestic and international travel (<10%).

 What You Bring

• Ph.D. in Computer Science, Electrical Engineering, or a related field preferred,  with 15+ years of experience in system architecture for large-scale computing platforms, with a strong focus on AI workloads 
• Proven hands-on experience developing analytical and event-driven simulation models for system-level performance evaluation. 
• Deep understanding of AI system hardware architectures, including compute, memory hierarchies, and high-performance interconnects.
• Strong knowledge of modern and emerging AI workloads, including LLMs, DLRMs, and large-scale training and inference systems.
• Demonstrated ability to translate workload characteristics and modeling results into actionable architectural design decisions.
• Proficiency in Python, C++, and PyTorch for modeling, analysis, and experimentation. 
• Excellent written, verbal, and presentation communication skills, with the ability to influence technical direction across teams.
• A collaborative mindset, intellectual curiosity, and resilience in tackling complex, open-ended system-level challenges. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Job Title: Principal Engineer, AI System Architect (Hardware)

The Architecture Research Lab (ARL) focuses on addressing fundamental system-level bottlenecks in modern AI, particularly in memory capacity/bandwidth and system-scale communication. By leveraging Samsung’s world-class memory technologies, ARL explores and defines next-generation AI system architectures that deliver step-function improvements in performance, efficiency, and scalability.
We are seeking a Principal AI System Architect who will play a Technical Lead role in bridging AI workloads, system architecture, and hardware design. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung’s long-term AI platform strategy.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42852

What You’ll Do

• Technically Lead the architecture team with strong  direction, shaping system‑architecture strategy and advancing key innovations
• Conduct system-level architectural research for next-generation AI systems, spanning compute, memory, and interconnect/network subsystems.
• Develop and maintain analytical and simulation-based system modeling frameworks to evaluate AI workloads and identify performance, scalability, and efficiency bottlenecks at rack- and system-scale. 
• Analyze representative and emerging system-level architectural research (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power.  
• Drive architecture-level design decisions through quantitative modeling, design-space exploration, and performance/power projections. 
• Perform comparative studies of alternative system architectures, reporting performance and performance-per-watt metrics to guide strategic technology choices. 
• Collaborate closely with cross-functional teams in hardware architecture, memory, interconnect, and system engineering to align modeling insights with implementation realities.  
• Communicate architectural insights and recommendations through clear technical presentations and documentation.   
• Occasional domestic and international travel (<10%).

 What You Bring

• Ph.D. in Computer Science, Electrical Engineering, or a related field preferred,  with 15+ years of experience in system architecture for large-scale computing platforms, with a strong focus on AI workloads 
• Proven hands-on experience developing analytical and event-driven simulation models for system-level performance evaluation. 
• Deep understanding of AI system hardware architectures, including compute, memory hierarchies, and high-performance interconnects.
• Strong knowledge of modern and emerging AI workloads, including LLMs, DLRMs, and large-scale training and inference systems.
• Demonstrated ability to translate workload characteristics and modeling results into actionable architectural design decisions.
• Proficiency in Python, C++, and PyTorch for modeling, analysis, and experimentation. 
• Excellent written, verbal, and presentation communication skills, with the ability to influence technical direction across teams.
• A collaborative mindset, intellectual curiosity, and resilience in tackling complex, open-ended system-level challenges. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Principal, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab is seeking Principal CPU Architecture & Performance Engineer to lead the definition, analysis, and optimization of next-generation CPU microarchitectures (RISC-V core). This role is focused on end-to-end performance: from architectural trade-offs and workload characterization to micro-architectural modeling, simulation, and silicon bring-up correlation.

You will work closely with architecture, design, compiler, and system teams to drive performance and efficiency across a broad set of real-world workloads

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42918

• Define and evaluate CPU micro-architectural features for future cores (frontend, execution engine, memory hierarchy, interconnect).
• Lead performance analysis using simulators, RTL.
• Help develop and validate performance models (cycle-accurate, trace-driven, statistical).
• Characterize workloads (SPEC, server, client, AI/ML, cloud, internal traces) and translate findings into architectural requirements.
• Identify performance bottlenecks and propose data-driven optimizations.
• Drive architecture-to-implementation alignment with design team.
• Collaborate with compiler, OS, and system architects on cross-stack performance issues.
• Mentor senior and staff engineers; provide technical leadership across projects.
• Work leading to patents and publication

What You Bring

• Master’s with 18+ years of experience in Computer Engineering, Computer Science, or related field.
•  or PhD with 15+ years of experience preferred.
• 10+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC-V, ARM or X86 architectures.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Familiarity with compiler optimizations and hardware/software co-design.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Experience analyzing large performance datasets and traces.
• Proven ability (Tapeout / Patents /Publications) to influence architecture / micro architectural decisions through quantitative analysis.

Preferred Qualifications

• Background in power/performance/area (PPA) trade-off analysis.
• Experience with SIMD/Vectors.
• Experience with compiler optimizations and hardware/software co-design.
• Prior technical leadership at Senior Staff or Principal level. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Senior, CPU Architecture & Performance Research Engineer

What You’ll Do

Architecture Research Lab is  seeking Senior CPU Architecture & Performance Engineer to contribute to performance analysis and microarchitectural optimization of current and next-generation CPU (RISC-V) cores. This role emphasizes hands-on analysis, modeling, and close collaboration with architects and design teams to improve performance across real-world workloads.

You will focus on executing well-defined performance studies, identifying bottlenecks, and helping translate architectural ideas into measurable performance gains

 Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42851

• Perform performance analysis for CPU microarchitectural features under guidance from Staff and Principal engineers.
• Run architectural simulations and analyze results (IPC, CPI stacks, latency and throughput metrics).
• Identify performance bottlenecks in frontend, execution engine, or memory subsystems.
• Assist in evaluating design trade-offs using trace-driven or cycle-accurate models.
• Characterize workloads and benchmarks (SPEC, server, client, internal traces).
• Develop scripts and tools to automate performance analysis.
• Work leading to patents and publication.

What You Bring

• Master’s, or PhD in Computer Engineering, Computer Science, or related field.
• 2+ years of experience in CPU microarchitecture and/or performance engineering.
• Strong understanding of:
• Out-of-order execution, branch prediction, pipelines, and speculation
• Cache coherence, memory systems, prefetching, and NUMA effects
• Hands-on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Experience analyzing large performance datasets and traces.
• Familiarity with compiler optimizations and hardware/software co-design.

Preferred Qualifications

• Experience with RISC-V, ARM or X86 architectures.
• Background in power/performance/area (PPA) trade-off analysis.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Prior tapeout / patent / publication experience. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• You approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

What You’ll Do

Lead cutting‑edge research on next‑generation AI system architectures. The role is responsible for end‑to‑end co‑design of AI workloads, system‑level modeling, hardware platforms, and high‑performance processors that leverage Samsung’s advanced memory technologies to eliminate capacity, bandwidth, and large‑scale communication bottlenecks.

Location: Daily onsite presence at our San Jose Headquarters in alignment with our Flexible Work policy

AI System Architecture Leadership

• Define system‑level architectures that solve memory‑capacity, bandwidth, and interconnect challenges for large AI workloads (e.g., large language models, recommendation systems).
• Build and maintain analytical and event‑driven simulation frameworks for compute‑memory‑network performance at rack scale.
• Conduct design‑space exploration and quantitative trade‑off studies (performance, power, cost) to guide architecture decisions.
• Partner with SAIT HQ teams to align modeling insights with real‑world AI system implementations.

RISC‑V CPU Architecture Leadership

• Architect high‑performance, out‑of‑order RISC‑V CPU cores that serve as host processors for AI computing systems.
• Drive IPC‑focused feature path‑finding; lead micro‑architecture research through performance‑model simulation and workload analysis.
• Produce detailed micro‑architecture specifications and guide cache/memory hierarchy design for optimal AI workload execution.

Research & Innovation Management

• Lead a multidisciplinary research team, set technical roadmaps, and ensure delivery of high‑impact publications.
• Present architectural insights and strategic recommendations to senior leadership and external partners.

What You Bring

• Education: Ph.D. in Computer Science, Electrical Engineering, or a related field.
• Experience: 10 + years in system‑level architecture research or large‑scale computing platform design, with a strong focus on AI workloads.
• Technical Expertise:
  • Performance modeling, event‑driven simulation, and quantitative analysis of compute‑memory‑interconnect systems.
  • Deep knowledge of modern CPU/accelerator architectures (RISC‑V, ARM, x86) and heterogeneous integration.
  • Proven ability to design rack‑scale AI system architectures that address memory, bandwidth, and interconnect constraints.
  • Proficiency with transaction‑level modeling (TLM) and event‑driven simulation for compute‑memory‑network co‑design.
  • Experience in large‑scale design‑space exploration and PPA (performance, power, area/cost) trade‑off analysis.
  • Expertise in architecture and micro‑architecture design of out‑of‑order CPUs.
  • Hands‑on experience with simulation tools and programming languages such as Python and C++.
• Communication Skills: Excellent written and verbal communication; proven ability to deliver technical presentations to senior stakeholders. 

Preferred Experience

• Proven track record of publishing high‑impact research papers.
• Experience influencing product roadmaps through architectural recommendations.
• Strong collaborative history with cross‑functional teams (hardware, software, memory technology). 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

 What You’ll Do

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

Job ID: 42786

• NVMe or SAS SSD Firmware development
• Analyze, debug, and resolve firmware issues observed at domestic and international customer sites as well as at local and overseas development centers.
• Triage and root cause system, driver, and device interoperability issues at customer sites.
• OEM Spec gap analysis, firmware customization/feature development; collaborate with other engineering teams to analyze debug information and implement and deploy firmware patches.
• Need based business travel and stay at domestic and international customer sites as well as overseas development centers for extended periods of time (can be up to multiple weeks at a time)
• Assist customers by running or inspecting their tests at onsite locations

What You Bring

• BS in Computer/Electrical/Electronic Engineering or Computer Science, and 5 years of relevant experience in software or firmware or a MS in Computer/Electrical/Electronic Engineering or Computer Science with 3 years of relevant experience preferred. 
• Strong experience in C/C++ programming for embedded systems is required. 
• Strong experience with UART/JTAG/ICE debuggers, and protocol analyzers. 
• Familiarity with at least one of the storage protocols such as SAS / SATA / SCSI / FC / NVMe / PCIe protocols is required. 
• Hands on experience with UART/JTAG/ICE debuggers, firmware debugging and protocol analyzers. 
• Demonstrated ability to work as a team player, as part of a local and globally distributed team. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation.  This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions.

Location:  Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month.

Reports to: Team leader/Head of Custom SoC Solutions Team

What You’ll Do

Customer Requirement Definition and Architecture Design:

• Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI).
• Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN).

Architecture Exploration and Validation:

• Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC).
• Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy.

Technical Collaboration and Leadership:

• Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases.
• Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and

 What You Bring

• Bachelor’s Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master’s and 8+ years of experience. 
• 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus)
• Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems).
• Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols.
• In-depth knowledge of Power Management and low-power design techniques.
• Experience with SoC-level Clock, Reset, and Power Domain architecture.
• Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification).
• Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues.
• Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients.
• Proficiency in scripting languages such as Python/Perl
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-VL1

The Technology Enabling Development Lab (TED) Our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

Location:  Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Design and development of high performance firmware and software for cutting-edge enterprise SSD products.
• Debug, optimize, and validate SSD firmware on complex embedded multi-core architectures.
• Support customer qualification and adoption of SSD products.
• Participate in ground-breaking advanced SSD storage development and research projects.

What You Bring

• BS in Computer/Electrical Engineering or Computer Science with 3+ years of working experiences in silicon development or MS in Computer/Electrical Engineering or Computer Science with 1+ years of relevant working experience or PhD and 0+ years of relevant experience in storage firmware development is required.
• Strong programming experience and demonstrated proficiency in C/C++ for embedded systems, including development of algorithms, manipulation of complex data structures, and implementing highly optimized code, is required.
• Relevant hands on experience in embedded software or firmware development, including storage devices or other embedded platforms is required.
• Experience with one or more of the following storage related technologies: NVM Express, PCI Express, SAS, SCSI, NAND Flash/FTL, Fibre Channel, SATA, eMMC, or UFS is beneficial.
• Experience with ARM or equivalent embedded multi-core microprocessor architectures is required.
• Hands on experience with JTAG/ICE debuggers and protocol analyzers is required.
• Some scripting experience in one of Python/Perl/Javascript is desired.
• Familiarity and experience with modern agile software development methodologies and practices is preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-SF1

What you’ll do:

• Architect and lead the team managing Archer’s lab integration environments supporting validation and verification activities, handling quality evaluations, human factor evaluations and test pilot training.
• Collaborate cross-functionally with internal groups and suppliers to integrate, instrument and maintain configuration of simulation models in a real-time, integrated hardware-in-the-loop environments .
• Own end-to-end configuration of simulation environments (e.g., SIL, HIL, CeRT, Iron Bird), including data analysis and simulation correlation with flight test data.
• Develop and optimize simulation pipelines including CI/CD integration for automated deployment, execution, and monitoring.
• Integrate third-party software/hardware systems into cohesive simulation architectures.
• Set technical standards, provide mentorship, and foster a collaborative and high-performance engineering culture.
• Guide the design and build of graphical user interfaces to control the real-time simulation environment.
• Lead task decomposition, technical planning, and debugging of complex issues across real-time and distributed systems.
• Influence tool architecture in support of lab configuration and automation

What you need:

• 9+ years of experience in simulation software development and systems integration.
• Bachelor's or higher degree in Aerospace, Software, Electrical Engineering, Computer Science, or a related field.
• Seasoned technical lead for an engineering team; providing guidance in planning and execution.
• Advanced proficiency in C/C++ and Python.
• Very experienced  in MATLAB/Simulink.
• Extensive experience developing real-time HIL test infrastructures.
• Proven ability to develop simulation tools with a focus on usability, modularity, and performance.
• Expert of communication standards and protocols (RS-422/485, CAN/CAN-FD, ARINC-429, Ethernet, TCP/IP, USB etc…)
• Experience prototyping Graphical User Interfaces based on user feedback.

• Knowledgeable with software engineering practices including CI/CD (GitHub Actions, Jenkins), test-driven development, and agile methodologies.
• Strong problem-solving and debugging skills with a proactive, solutions-oriented mindset.
• Comfortable working in cross-disciplinary teams and mentoring junior engineers.
• Comfortable leading Agile/SCRUM methodologies and tools throughout the organization
• Familiarity with Tool Qualification Levels TQL

Preferred Qualifications

• Experience with aerospace, spacecraft, or robotics systems—including modeling of flight dynamics, sensor-actuator loops, or avionics.
• Proficiency in the NI software suite (LabVIEW, VeriStand).
• Experience developing and troubleshooting custom code (i.e. plugins, logical devices, custom devices) for real-time OS
• Background in simulation infrastructure for VTOL, rotorcraft, or autonomous vehicles.
• Understanding of control theory, GNC algorithms, and physics-based modeling.
• Hands-on experience with HIL/SIL test rigs, hardware communication protocols, and test instrumentation.
• Exposure to regulatory frameworks (FAA, DoD, NASA) and test certification environments.
• Startup or fast-paced development experience is a plus.
• Experience automating and executing test plans.
•  Experience with DO-178 and other aviation standards  
• Familiarity with fault injection methodologies.
• Familiarity with lab equipment such as oscilloscopes, logic analyzers and protocol analyzers.

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $170,000 - $215,000. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Role 

We are looking for a Sr. Staff Production Engineer to join our team. This role is available as a hybrid opportunity 3 days a week in San Jose, CA or as a remote position, reporting to Production Engineering in the Cloud Infrastructure & Operations department. Join Zscaler to be a force multiplier for the reliability of a global platform protecting over 15 million users. 

In this role, you will provide the technical vision and hands-on execution to drive an "automation-first" culture across the company. By maturing our observability and architectural standards, you will directly reduce our Mean Time to Mitigate (MTTM) and shape the scalability of our globally distributed, multi-cloud infrastructure.

What you’ll do (Role Expectations)

• Design and implement highly available, scalable infrastructure across AWS, Azure, GCP, and bare-metal environments
• Drive an "automation-first" culture by writing code (Python/Go) to eliminate manual toil and build self-healing systems
• Implement and maintain sophisticated observability (Prometheus, Grafana, OpenTelemetry), define SLIs/SLOs, and establish error budgets
• Act as a lead Incident Commander (TDO on-call), develop response playbooks, and conduct deep-dive post-incident analyses
• Partner with Engineering and partner teams to conduct operability reviews

Who You Are (Success Profile)

• You act like an owner with a bias for action and integrity.
• You are a pragmatic builder obsessed with creating, iterating, and shipping.
• You champion simplicity by distilling complex problems into clear, actionable plans.
• You are data-driven, valuing evidence over assumptions.
• You think at scale, building solutions and processes built to last a high-growth global organization.

What We’re Looking for (Minimum Qualifications)

• 8+ years of experience managing reliability, scalability, and availability for large-scale production services
• Deep expertise in programming (e.g., Python, Go, or C/C++)
• Strong background in networking protocols, Linux/FreeBSD systems, and distributed architecture
• Experience in high-stakes incident management and participation in a 24/7 on-call rotation
• Proficiency in leveraging ITIL frameworks and incident data to drive service maturity through systematic problem management and technical operability reviews

What Will Make You Stand Out (Preferred Qualifications)

• Extensive experience with public cloud (AWS, Azure, GCP) and Infrastructure-as-Code (Ansible, Terraform)
• Experience with chaos engineering and disaster recovery planning at scale
• Expertise in global routing (BGP) and traffic tunneling (GRE, IPSec) with a deep understanding of L7 proxy architectures (HAProxy), DNS at scale, and OS networking stack internals

#LI-Hybrid

#LI-CM3

What you’ll do:

• Perform low/mid/high fidelity aerodynamic simulations of Archer eVTOL aircraft
• Develop linear/non-linear aerodynamic models to predict aircraft behavior and performance throughout the flight envelope
• Analyze experimental data (either from flight test or wind tunnel) to identify sources of model errors, validate, and improve aerodynamic models of the vehicle
• Develop efficient methods to feed flight test data back into aerodynamic simulation models of various fidelity and complexity
• Contribute to the development of Archer aerodynamic software stack, improving methods and workflows
• Coordinate with other cross-functional teams and pilots for flight simulator aerodynamic modeling updates and issue resolution

What you need:

• BS / MS / PhD in Aerospace Engineering or a related field

• 2+ years of experience with BS, or 1+ years of experience with MS, or 1+ years of experience with PhD modeling rotorcraft, tiltrotor, eVTOL aerodynamics at full-vehicle level
• Strong understanding of fundamentals of fixed-wing and rotorcraft aerodynamics, performance, stability & control 
• Experience in eVTOL and/or multicopter vehicle aerodynamics design and analysis, including 6 DoF vehicle trimming and trajectory optimization
• Experience with gradient-based and gradient-free optimization techniques
• Experience with surrogate modeling techniques (like Kriging methods) and statistical analysis
• Experience with experimental data processing and reduction techniques
• Proficiency in Python programming
• Experience with software development, object-oriented, version control best practices, as well as Git, CICD, Conda

• Excellent work planning and issue resolution skills
• Strong technical, written, and verbal communication skills
• Ability to work in groups and individually
• Experience in a fast-paced design environment

Bonus Qualifications:

• Experience with developing, training, and optimizing neural networks or other machine learning models in the context of aerodynamic modeling
• Experience with wind tunnel and flight test campaigns planning, execution, and data processing, ideally matured on rotorcraft, tiltrotor, eVTOL program
• Work experience with rotorcraft comprehensive analysis tools, such as RCAS or CAMRAD2
• Work experience with NASA Overflow and Fun3D CFD software, including meshing
• Experience utilizing high-performance computing (HPC) to parallelize workflows

• Familiarity with conventional airplane Part 23/25 or rotorcraft Part 27/29 certification basis and test methods

• Familiarity with ASTM standards for fixed wing and rotorcraft
• Familiarity with Matlab/Simulink, and Fortran/C++ coding

At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy. For this position we are targeting a base pay between $140,000 - $190,000. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.

Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis.

Astera Labs’ firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems.

Job Description

• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance.
• Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic Qualifications 

• Strong academic and technical background in electrical or computer engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Required Experience 

• ≥3 Years experience leading a team in a “lead by example” manner—planning sprints, assigning tasks based on individuals’ strengths and career aspirations, providing constructive/encouraging feedback, maintaining a “dashboard” view of project status, chipping into shore up gaps in execution as needed.
• ≥5 Years hands-on experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Good understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred Experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Familiarity with PCIe compliance standards and the ability to follow and be involved in compliance and standard consortiums.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, clock recovery and SerDes link budgets.
• Experience with PAM4 SerDes is a huge bonus!

We are looking for a Staff Golang Developer to join our Platform Convergence team. This is a hybrid role based in either San Jose, CA or Bellevue, WA (3 days a week), reporting to the Sr. Director of Software Engineering within the Engineering department. You will bring your vision and passion to a team of architects and engineers building the world’s largest cloud security platform. You will help organizations worldwide harness speed and agility through a cloud-first strategy and a robust multitenant architecture.

What you’ll do (Role Expectations)

• Design, and implement scalable, high-performance backend services and APIs using Go while integrating with PostgreSQL, MySQL, MongoDB, and Redis
• Ensure code quality through unit, integration, and performance testing while monitoring and optimizing system performance
• Partner with external teams to deliver integrated solutions and ensure seamless system functionality across the platform
• Drive project success by contributing to Agile/Scrum processes, including sprint planning and retrospectives
  
  

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful
• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution
• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact
• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust
• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose
  
  

What We’re Looking for (Minimum Qualifications)

• 5+ years of experience with proficiency in Golang, including expertise in concurrency, parallelism, GRPC, and Protobuf
• Skilled in building large-scale distributed systems, RESTful API design, and web frameworks like Gin and Echo
• Hands-on experience with Docker, Kubernetes, and cloud platforms such as AWS, GCP, or Azure
• Solid understanding of SQL and NoSQL databases along with CI/CD pipeline implementation
• Exceptional problem-solving skills and attention to detail for designing robust technical solutions
  
  

What Will Make You Stand Out (Preferred Qualifications)

• Experience with systems languages like Rust or C/C++, particularly in performance-critical environments
  
  

#LI-Hybrid #LI-JM1

Role 

We are looking for a Sr. Staff SWE to join our Zero Trust Exchange department.  This is a Hybrid role based onsite in San Jose three days a week, reporting to the Sr. Manager, Software Development Engineering.

As a key member of the engineering team, you will implement new ZCC tunnel features and modularize existing code to drive greater stability and performance across our platform.

What you’ll do (Role Expectations)

• Implement high-impact ZCC tunnel features that enhance connectivity and security for our global user base
• Lead the modularization of existing code into libraries to improve system maintainability and architectural stability
• Integrate memory-safe Rust language components where applicable to advance our commitment to robust and secure engineering

Who You Are (Success Profile)

• You act like an owner by taking full accountability for outcomes and navigating seamlessly between high-level strategy and hands-on execution.
• You are a dedicated problem-solver who is energized by complex challenges and finding solutions that deliver significant impact.
• You are customer-obsessed, anchoring every technical decision in solving real-world problems for both internal and external stakeholders.
• You are driven by innovation and a deep curiosity for how things work, always seeking more secure and scalable ways to build technology.
• You think at scale, connecting your day-to-day work to the larger mission and building solutions designed to support a high-growth, global organization.

What We’re Looking for (Minimum Qualifications)

• Advanced proficiency in C/C++ with experience building high-performance systems
• Tunneling and/or VPN experience
• Strong foundational knowledge of networking protocols and infrastructure
• Proven ability to design and write secure, scalable code in a professional environment

What Will Make You Stand Out (Preferred Qualifications)

• Professional experience developing with the Rust programming language
• Direct experience working within the VPN application domain or similar network security technologies

#LI-JM1 #LI-Hybrid

We are looking for a Sr. Staff Software Development Engineer to join our Zero Trust Exchange department. This is a hybrid role based in San Jose (3 days per week in-office), reporting to Sr. Manager, Software Development Engineering.

The Zscaler Client Connector (ZCC) team plans to modularize existing code into individual and separate libraries so that they can be better integrated into cross-platform releases, well unit tested and shared with other teams within the company. We are looking for engineers with C/C++ skillset who can work on this ambitious project.

What you’ll do (Role Expectations)

• Modularize existing and new ZCC code into separate libraries
• Write well maintained and unit-testable code
• Use state-of-the-art technologies for better scalability and memory safety

Who You Are (Success Profile)

• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. You adapt to what’s needed, navigating seamlessly between high-level strategy and hands-on execution.
• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.
• You operate with urgency. You understand that in a high-growth environment, speed and quality are not mutually exclusive. You have a relentless focus on execution and a bias for action, delivering high-impact results quickly to win for the customer and the team.
• You are a pragmatic builder. You are obsessed with creating, iterating, and shipping. You aren't afraid to roll up your sleeves and build the first version yourself, balancing the drive for technical excellence with the need to deliver value to users quickly.
• You champion simplicity. You are skilled at distilling complex problems, user needs, and technical concepts into clear, simple, and actionable plans. You are a precise communicator who brings clarity and focus to every interaction.

What We’re Looking for (Minimum Qualifications)

• Extensive professional experience with C/C++ client development
• Strong foundational knowledge of networking protocols and systems
• Proven experience developing for Windows plus one or more additional platform
• Practical experience with VPN technologies and architectures

What Will Make You Stand Out (Preferred Qualifications)

• Hands-on experience with the Rust programming language
• Deep network-level experience building highly scalable systems

#LI-Hybrid #LI-JM1

We are looking for a macOS/iOS Developer based in San Jose, CA (Hybrid), reporting to the Sr. Manager of Software Engineering.. You will be a key driver on the Mobile team, developing cross-platform client applications for MacOS and iOS that securely steer traffic to the world’s largest cloud security platform. Your vision and technical expertise will enable organizations worldwide to harness speed and agility through a cloud-first strategy, directly impacting a global footprint of over 65 million users.

What you’ll do (Role Expectations)

• Develop high-performance macOS and iOS applications and frameworks that serve as the gateway to our global cloud security platform
• Partner with product managers to translate complex requirements and design mockups into clean, high-quality code
• Take accountability for the performance, quality, and responsiveness of applications to ensure a seamless user experience
• Uphold and evolve engineering excellence by maintaining rigorous code quality, standards, and automation practices
• Act as a technical point of escalation to troubleshoot and resolve complex customer issues with speed and precision

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.
  
  
• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.
  
  
• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.
  
  
• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.
  
  
• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• 4+ years of professional software development experience specializing in Objective C, SWIFT, or C++
• Technical understanding of the Mac networking stack, networking protocols, and modern architectural design patterns
• Proven experience working with RESTful APIs, offline storage, multi-threading, and performance tuning
• Extensive knowledge of the Mac/iOS ecosystem and the standard libraries used for common engineering tasks
• Demonstrated ability to translate product requirements into high-quality, scalable technical solutions

What Will Make You Stand Out (Preferred Qualifications)

• Professional familiarity with PKI, network security technologies, cloud message APIs, or Apple Push Notifications
  
  

#LI-Hybrid #LI-JM1

Overview

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 10 + years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, executing validation plans for complex SoC designs. 

Required Experience:

• Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet.
• Familiarity with Electrical Compliance section of PCIe Base Spec and CEM Spec
• Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ, CDR, etc and concepts such as PAM4
• Experience in PRBS testing and optimization of high-speed PCIe data links over short, med, and long channels
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops
• Hands-on experience with signal integrity, especially as it relates to PCIe testing, Channel Loss budgeting, and de-embedding
• Working knowledge of C or C++ for embedded FW, experience using git-based version control such as github
• Familiarity with PCIe standards and both NRZ and PAM-4 signaling
• Working knowledge of common serial data specifications such as I2C, SPI, etc
• Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is $185,000 USD - $230,000 USD. Your base salary will be determined based on your experience and the pay of employees in similar positions. 

The Role and Its Impact 

Our Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications, providing critical signal conditioning for high-speed connectivity in AI infrastructure. The firmware you develop will manage complex system and IP integration, SERDES configuration, link training sequences, and diagnostic capabilities for these devices deployed in data centers worldwide. 

As a Principal Engineer in our Signal Connectivity Engineering group, you'll contribute to firmware that directly impacts the performance and reliability of Ethernet connectivity solutions powering AI infrastructure globally. Working closely with the SoC software, transceiver module software, and system validation teams, you'll take ownership of feature development and rollout, software integration testing, and customer debug activities. Working at the intersection of embedded systems and high-speed Ethernet connectivity, you'll collaborate closely to bring these systems to production. 

We're a startup, and this role reflects that reality. You'll have responsibilities spanning firmware development, customer engagement, debug and validation support, and cross-functional coordination. We're looking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. 

This position offers strong mentorship opportunities as you work alongside experienced engineers and help bring products from development through customer deployment. 

Level is negotiable based on experience and qualifications. 

Location 

This is an on-site position based in our San Jose, CA office. 

Core Responsibilities 

Firmware Development & Debug 

• Develop and maintain embedded firmware for Ethernet retimers and gearboxes, from low-level hardware abstraction through customer-facing APIs 
• Drive Layer 1 PHY and SERDES debug activities, including link bring-up issues, signal integrity problems, and interoperability failures 
• Support complex IP integration efforts across multiple subsystems within the SoC 
• Implement and optimize link training sequences, equalization tuning, and diagnostic features 
• Assist with software quality gates and validation criteria at each development phase 

Product Rollout & Customer Integration 

• Partner with the software lead to drive product rollout activities from development through production deployment 
• Support customer integration efforts through firmware customization, debug assistance, and technical guidance 
• Investigate field-reported issues and coordinate resolution with internal teams 
• Develop and maintain SDK/API interfaces that enable customer platform integration 

Cross-Functional Collaboration 

• Work extensively with digital SoC teams to understand hardware behavior, register interfaces, and IP integration requirements 
• Collaborate with field applications engineers to support customer bring-up and resolve deployment issues 
• Partner with platform applications teams to ensure firmware meets system-level requirements 
• Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases 
• Provide regular project updates on progress, risks, dependencies, and technical challenges 

What You Bring 

Required Qualifications: 

• BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field 
• 10+ years of embedded C/C++ firmware development in resource-constrained environments 
• Deep understanding of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware design 
• Experience with Layer 1 PHY firmware, SERDES bring-up, or SDK/API development for networking devices 
• Strong proficiency with Linux development tools: gcc/clang, make, bash scripting, gdb, and git 
• Excellent verbal and written communication skills; ability to explain complex technical concepts clearly 
• Demonstrated problem-solving ability and systematic debugging approach on real hardware 
• Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment 

Highly Valued Skills: 

• Experience with PMA, FEC, or related PHY-layer subsystems beyond the PMD/SERDES 
• Familiarity with NIC or switch management software, for system test purposes 
• Exposure to SAI (Switch Abstraction Interface) or OpenBMC 
• Experience with Python for test automation, data analysis, or general scripting 
• Hands-on experience building and maintaining Jenkins CI/CD pipelines and automated test infrastructure 
• Background in retimer or gearbox firmware/API, active electrical cables, or high-speed Ethernet connectivity 
• Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, BERT, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar 
• Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin 
• Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments 
• Experience with RTOS, device drivers, or coroutines 
• Prior technical lead, mentorship, or team lead experience 

Compensation 

Salary range is $185,000 USD - $203,000 USD depending on experience, level, and business need. This role will include a discretionary bonus, competitive equity package, comprehensive health/dental/vision coverage, professional development opportunities, and a culture that values technical excellence, collaboration, and innovation.

Job Description

The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
• Minimum 8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).
• Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience developing embedded firmware for PCIe products.
• MQX RTOS or ThreadX Development or enablement.
• High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
• High level of proficiency in Python for automating pre-processors/post-processors and FW QC.
• Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.
• Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).
• Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces
• Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc

Preferred Experience

• Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC)
• Experience with industry forums and collaboration workgroups such as OCP and OpenBMC

The base salary range is $203,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description

We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
  required, and a Maser’s is preferred.
• ≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or
  Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
  customer meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in US and start immediately.

Required Experience

• Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI
• Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
• Experience in developing infrastructure and tests in a hybrid directed and constrained random
  environments
• Must be able to work independently to develop test-plans, and related test-sequences in UVM to
  generate stimuli and work collaboratively with RTL designers to debug failures.
• Develop user-controlled random constraints in transaction-based verification methodology. Experience
  writing assertions, cover properties and analyzing coverage data
• Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.
• Must have prior experience on verification with firmware to control and configure the SerDes and related components.

Preferred Experience

• SW debugging for Mix-Signal based designs.
• Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.
• Experience with FPGA-based verification/emulation.

Overview: 

The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance.

Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs.

Basic Qualifications:

•  Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
•  ≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
•  Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead
• Required experience
• Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet
• Strong problem-solving skills, ability to solve problems independently
• Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

•  Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
•  Familiarity with PCIe or Ethernet especially Electrical Compliance sections
•  Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
•  Working knowledge of C or C++ for embedded FW
•  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
•  Working knowledge of common serial data specifications such as I2C, SPI, etc
•  Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
•  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is USD 203,00 - USD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job Description

We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
• Familiar with high-speed load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with using Advantest 93k ATE platform.
• Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.
• Experience in running External loopback at wafer sort.
• Familiarity with modern databases

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.
• Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion.
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Basic qualifications 

• Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥12 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Required experience 

• Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
• Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget. Experience with PAM4 SerDes is a huge bonus!
• Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
• Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.

The base salary range is $205,000.00 USD – $255,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

Overview: 

As a Senior Principal Validation Engineer, you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets.

You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction.

This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives before production.

Key Responsibilities:

• Design, develop, and execute validation plans. Own end‑to‑end post‑silicon characterization and validation strategies, translating product requirements into measurable test objectives, pass/fail criteria, and schedules.
• Drive design reviews and specification alignment. Participate in architecture and design‑spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.
• Lead hands‑on test execution and bring‑up. Perform silicon bring‑up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time‑to‑data.
• Build and maintain automation frameworks. Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed‑signal test benches.
• Debug and optimize system performance. Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs.
• Root‑cause cross‑domain failures. Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system‑level tests; coordinate with design, package, and firmware teams to implement fixes.
• Collaborate with cross‑functional teams. Work closely with mixed‑signal design, firmware, system engineering, and manufacturing to deliver detailed results, root‑cause analyses, optimization recommendations, and formal validation/compliance reports.
• Document findings and improve methodologies. Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base.
• Develop test software and platform integrations. Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites.
• Measure and communicate impact. Define key validation metrics, track coverage and defect trends, and present data‑driven conclusions to stakeholders to influence product direction and release decisions.

Basic Qualifications

• Education — Bachelor of Science in Electrical Engineering required; Master’s degree preferred to demonstrate advanced technical depth and specialization.
• Experience — At least ten years of hands‑on experience in mixed‑signal, high‑speed lab environments, executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real‑time oscilloscopes, sampling scopes, TDRs, and VNAs.
• Software Skills — Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.
• Retimer Expertise — Practical experience bringing up and debugging retimers, including equalization tuning, pass‑through operation, clocking strategies, and reset and link sequencing.
• High‑Speed Signaling Knowledge — Deep understanding of NRZ and PAM4 architectures and the ability to investigate jitter sources, CDR and PLL behavior, equalization techniques such as DFE, CTLE, and FFE, as well as crosstalk and power integrity issues.
• Post‑Silicon Validation — Proven track record in post‑silicon validation and bring‑up of high‑speed PHYs or retimers, with experience developing characterization flows and validating silicon against specifications.
• Circuit Block Familiarity — Solid working knowledge of key high‑speed building blocks including PLLs, CTLE, DFE, transmitter equalization, and PAM4 signaling fundamentals.
• Analytical Problem Solving — Exceptional troubleshooting skills with the ability to isolate and narrow complex, multi‑layer failures across analog, digital, firmware, and package domains.
• Communication — Excellent written and verbal communication skills for clear documentation of findings, presentation of root cause analyses, and collaboration with cross‑functional teams.

Preferred Experience:

• Mixed‑signal system testing and validation — Demonstrated experience in end‑to‑end mixed‑signal system testing, characterization, validation, and compliance activities, including developing test plans, executing characterization flows, and producing formal compliance reports.
• Signal integrity instrumentation and techniques — Hands‑on proficiency with signal integrity test equipment and methodologies, including BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, and advanced probing techniques for channel and package analysis.
• Ethernet standards familiarity — Working knowledge of IEEE 802.3 family standards and practical experience validating Ethernet PHYs, link training, autonegotiation, and compliance testing across relevant speeds and media types.
• Serial protocol expertise — Practical understanding of common serial interfaces such as I2C, I3C, SPI, UART, and other control/status buses used for device bring‑up, firmware interaction, and system integration.
• Cross‑discipline collaboration — Proven ability to translate SI/PI simulation results into testable lab plans, collaborate with design and firmware teams to close the loop on issues, and document findings that drive design or process improvements.

Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.

The base salary range is USD 205,00 - USD 255,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Overview

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Senior Silicon Validation Engineer to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. 

Basic Qualifications 

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred. 
• ≥3 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. 
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision. 
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind! 
• Proven track record solving problems independently. 

Required Experience 

• Familiarity with DDR4/5 memory standards and DIMM configuration, experience in system testing, characterization, margin analysis and optimization 
• Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ 
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration 
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis. 
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope/high-speed probe, and VNA 

Preferred Experience 

• Hands-on experience with signal integrity, especially as it relates to multi-rank DDR and DDR termination schemes 
• Working knowledge of C or C++ for embedded FW 
• Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops 
• Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working with internal SoC HW/FW teams to improve memory calibration and tuning sequences 
• Working knowledge of common serial data specifications such as I3C, I2C, SPI, etc 
• Knowledge of memory subsystem compliance and RAS is a plus. 
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc. 
• Knowledge of simulation tools such as MATLAB, Keysight ADS, PLTS for data analysis and modeling of signal integrity issues. 

Job Description

We are looking for Senior SoC Verification/Validation Engineer who are passionate about bringing next-generation SoCs to life on industry-leading emulation platforms. You will play a critical role in validating complex SoCs for AI connectivity and cloud infrastructure, ensuring functionality and performance well before silicon tape-out.

Basic Responsibilities

• Play a key role in developing complex SOCs for AI connectivity and cloud infrastructures 
• Bring up and validate high-speed serial interfaces such as PCIe, Ethernet and UALink, and overall SoC functionality 
• Collaborate closely with Architecture, Design, Verification, and SW/FW teams to define and execute functional/performance validation plans
• Develop C/C++ FW and tests to validate and execute all test plan items 
• Build tools and methodologies to validate and debug all HW and SW/FW issues on the emulation platform

Required Qualification

• BS/MS in Electrical Engineering, Computer Engineering or related field.
• 5+ years of hands-on experience in pre-silicon verification/validation.
• Strong hands-on experience in running and debugging SOC simulation.
• Protocol knowledge in high-speed protocols such as PCIe, UALink and/or Ethernet is essential
• Proficiency in programming and scripting languages (System Verilog, C/C++, Python) 
• Strong debugging and analytical skills
• Excellent communication skills and ability to work independently with minimal supervision.
• Currently based locally or open to relocation.

Preferred Experience: 

• Bring up and validation experience using the industry standard emulation platforms (Palladium or Zebu) 
• Hands-on experience in running and debugging SOC simulation and emulation platforms.

The base salary range is $165,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

Job Description:
At Astera Labs, we are looking for motivated Senior / Tech Lead Post-Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• ≥3 years’ experience testing, supporting or developing complex SoC/silicon products and high-speed IO/SerDes electrical interface for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, preferably as a tech lead.

Required Experience:

• Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3x Ethernet.
• Strong problem-solving skills, ability to solve problems independently.
• Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, and both NRZ and PAM4 signaling.
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
• Familiarity with PCIe or Ethernet especially Electrical Compliance sections
• Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
•  Working knowledge of C or C++ for embedded FW
•  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
•  Working knowledge of common serial data specifications such as I2C, SPI, etc
•  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $148,500 USD - $165,000 USD for Senior level, and $175,000 USD - $195,000 USD for Staff level.

Role Overview As a Sr. Principal DSP Architect, you will be the technical visionary leading the definition and development of next-generation Digital Signal Processing (DSP) architectures. Your focus will be on high-speed PAM4 (Pulse Amplitude Modulation 4-level) systems and coherent/direct-detect optical transceivers. You will bridge the gap between theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond.

Key Responsibilities

• Architectural Leadership: Lead the definition of DSP micro-architecture for high-performance ASICs, focusing on low-power, high-throughput data paths.
• Algorithm Development: Design, model, and simulate advanced DSP algorithms for:
• Adaptive Equalization (FFE, DFE, MLSE).
• Forward Error Correction (FEC).
• Clock and Data Recovery (CDR).
• Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) compensation.
• Modeling & Simulation: Develop bit-accurate and performance-accurate models using Python, MATLAB, or C++ to validate architectural choices against Bit Error Rate (BER) targets.
• Cross-Functional Collaboration: Work closely with Analog Mixed-Signal (AMS) designers to optimize the ADC/DAC interface and with RTL teams to ensure power-efficient hardware implementation.
• Performance Trade-offs: Conduct rigorous Power, Performance, and Area (PPA) analysis to balance complex DSP requirements with the thermal and size constraints of optical modules (e.g., QSFP-DD, OSFP).
• Standards Contribution: Represent the company in industry standards bodies (IEEE 802.3, OIF) to influence future optical communications protocols.

Required Qualifications

• Education: PhD or MS in Electrical Engineering, Communication Theory, or a related field.
• Experience: 12+ years of experience in DSP design, specifically for high-speed SerDes or optical communications.

Technical Deep Dive:

• Expertise in PAM4 signaling and the associated challenges (non-linearity, SNR requirements).
• Deep understanding of Digital Filter Design (FIR, IIR) and adaptive signal processing.
• Experience with high-speed ADC/DAC architectures and their impact on DSP performance.
• Tooling: Proficiency in MATLAB/Simulink, Python (NumPy/SciPy), and SystemC.
• Silicon Success: A proven track record of taking complex DSP architectures from concept through tape-out to high-volume production.

Preferred Skills

• Experience with Coherent Optical technologies (QAM, polarization multiplexing).
• Knowledge of Machine Learning applications in DSP for non-linearity compensation.
• Familiarity with hardware description languages (Verilog/SystemVerilog) and the synthesis flow

About Astera Labs

Astera Labs is a rapidly growing semiconductor company redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions—built on PCIe®, CXL™, Ethernet, and custom fabrics—enable seamless data movement across compute, memory, and storage. As part of our team, you'll help validate the silicon that powers the world's most advanced AI platforms.

Role Overview

As an Entry-Level System Validation Engineer on the Taurus team, you will validate Astera Labs' Taurus Ethernet Smart Cable Modules and Taurus ASICs. You'll work on chip bring-up, system-level debug, and interoperability testing across real-world AI server and networking platforms, collaborating closely with electrical validation, firmware, and product applications teams.

Key Responsibilities

• Execute system validation test plans for Taurus Ethernet Smart Cable Modules.
• Perform chip bring-up and debug for Taurus ASICs in lab environments using oscilloscopes, protocol analyzers, BERTs, and network switches
• Validate high-speed interconnects and AI fabrics in custom silicon, including signal integrity, link training, FEC stats, and protocol compliance
• Collaborate with electrical validation, firmware, and product applications teams to root-cause issues and drive resolution
• Document validation results, debug findings, and contribute to bring-up notes and test reports

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• Strong academic foundation in circuit analysis, signals and systems, electromagnetics, or high‑speed digital design through coursework and labs
• Familiarity with PCIe®, CXL™, or Ethernet standards
• Familiarity with fundamental signal‑integrity concepts such as eye diagrams, jitter, noise, impedance, and transmission lines
• Exposure to electrical lab equipment (e.g., oscilloscopes, logic analyzers, network analyzers)
• Experience using scripting or programming languages such as Python, MATLAB, TCL, or C/C++
• Comfortable working with lab tools and debugging hardware
• Strong analytical and communication skills

Preferred Skills

• Exposure to post-silicon validation or bring-up of connectivity IP blocks
• Knowledge of signal integrity analysis and eye diagram interpretation
• Familiarity with Linux systems, shell scripting, and version control (Git)
• Understanding of AI workloads and how interconnect bandwidth impacts performance

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
• Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
• Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Overview: 

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Description:

We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic Qualifications:

• Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)
• Experience in working with RF testing and characterization
• Knowledge of spectrum analyzers, vector network analyzers (VNA), and other RF test equipment
• Have gone through at least one cycle of full product development life cycle
• Strong academic/technical background in electrical or computer engineering; bachelor’s is required; MS preferred
• Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
• Digital and analog circuit level understanding for DUT.
• Excellent team player with great communication skills
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required Experience:

• Detail-oriented monitoring of device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs
• Experience with RF calibration techniques and de-embedding methodologies
• Experience with RF parameter measurements including S-parameters, insertion loss, return loss, and signal integrity analysis
• Hands-on work with Advantest 93k ATE platform (SmartScale/ExaScale) including test program updates for wafer sort and final test solutions
• Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions
• Energetic work mindset to meet the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred Experience:

• Hands-on product/package qualification
• Partnering with Fabs on process development and yield improvement initiatives
• Collaboration with silicon validation teams to ensure device performance meets production requirements
• Firmware development in C/C++, scripting in Python, or other equivalent programming languages

Job Description:

We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic Qualifications:

• Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)
• Experience in working with PCIe Gen3 and above
• Have gone through at least one cycle of full product development life cycle
• Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred
• Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
• Digital and analog circuit level understanding for DUT.
• Excellent team player with great communication skills
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required Experience:

• Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions
• Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.
• Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs
• Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions
• Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred Experience:

• Working with silicon validation teams to ensure device performance meets production requirements.
• Firmware development in C/C++, scripting in Python, or other equivalent programming experience.
• Hands on experience in product/package qualification

As an Astera Labs Technical Lead Lab Validation Engineer, you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions.  You will:

• Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions.  Collaborate with design, validation, and system engineering teams as needed.
• Modify device firmware to test out engineering theories leading to potential fixes or production screens.
• Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems.
• Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability.
• Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports.
• Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures.
• Develop and run stress tests and margining experiments to identify weak design or process corners.
• Provide feedback on system-level integration challenges for retimers and PCIe switches (e.g., board layout, equalization tuning, firmware interactions).
• Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing.
• Document debug findings, propose design/process/test improvements, and contribute to FA methodologies.
• Participate in new product development process to ensure readiness for customer returns before products are launched. Collaborating in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts.

Basic qualifications:

• Minimum of a Bachelor’s in Electrical Engineering while a Master’s degree is preferred. 
• Minimum of 10 years relevant experience of which 5 years’ is hands-on mixed high-speed lab experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA.
• Python programming.
• Deep understanding of PCIe protocol (up through Gen6), retimer architecture, and SerDes signal integrity.
• Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing).
• Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures).
• Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity.
• Experience in post-silicon validation and bring-up of high-speed PHYs or retimers.
• Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures.
• Strong written and verbal communication skills.

Preferred experience (ideal candidate has some of this, but OJT is also possible):

• C (not C++).
• Experience with optics.
• Experience with chip-level security and RAS features.
• ATE (Automated Test Equipment) Advantest V93K.
• Understanding of system-level architecture for servers, storage, and AI/ML platforms where PCIe retimers/switches are deployed.

Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.

The base salary range is $160,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.

Key Responsibilities

• Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
• Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
• Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
• Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
• Work with RTL designers to troubleshoot and resolve design issues.
• Drive verification strategy and methodology for SoCs in server and networking applications.

Required Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred).
• 8+ years of experience in SoC verification, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
• Familiarity with verification of switching architectures, including packet processing and forwarding engines.
• Excellent communication skills and ability to work independently with minimal supervision.

Preferred Qualifications

• Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
• Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
• Knowledge of Ethernet/PCIe switching and central buffer architectures.
• Experience with emulation platforms and hardware-software co-verification

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Job Description:

As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products.  You will be working on projects from conception to the final production stage at contract manufacturer.

The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices.  At the same time we welcome candidates with deep experience in smaller areas with the desire to learn.  Depending on your experience, you may be focusing on design/validation or automation/manufacturing.

Key Responsibilities

• Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.
• Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product
• Bring-up newly manufactured boards and develop the first level of software.
• Isolate and perform root-cause analysis of reported failures
• Support new platform software and hardware features
• Coordinate with the hardware engineering team on bring-up schedules and feature delivery
• Participate proactively in design discussions, design review, and project management
• Work independently as well as in team roles, mentor younger team members

Basic Qualifications/Required Experience

• Bachelor’s in CS/CE or equivalent experience.
• 8+ years of Experience in subset of diagnostic, hardware bring-up, test or manufacturing automation
• Knowledge of modern software development 
• Proficiency in Python, C/C++

Preferred experience

• Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing
• Ability to read schematic/layout
• System debug experience
• Embedded programming and good knowledge of OS internals (Linux/Unix)
• Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.
• Experience with DDR5

The base salary range is $203,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Figure is an AI Robotics company developing a general purpose humanoid. Our Humanoid is designed for corporate tasks targeting labor shortages and jobs that are undesirable or unsafe. We are based in San Jose, CA and require 5 days/week in-office collaboration. 

We are seeking a Robotics Integration Engineer to drive system-level integration and validation across hardware, firmware, controls, AI, perception, and software. You will plan, execute, and oversee subsystem integration and full-system bring-up, ensuring reliable performance and consistency across the entire robot ecosystem. This is a highly technical, hands-on role focused on debugging, root cause analysis, and validating system functionality to make humanoid robots perform reliably in the real world.

Responsibilities: 

• Integrate and validate system-level changes across hardware, controls, behavior, AI, and perception subsystems.
• Architect and execute bring-up, validation, and end-of-line (EOL) test processes for humanoid robots.
• Develop test tools and automation scripts in C++ and Python to streamline integration and data analysis.
• Design and run validation plans that stress full-robot functionality across real-world use cases.
• Debug and triage cross-disciplinary issues spanning mechanical, electrical, firmware, and software systems.
• Collaborate with design, controls, behaviors and software teams to define testable behaviors and verify subsystem performance.
• Instrument robots using diagnostic tools (oscilloscopes, logic analyzers, telemetry logs) to characterize performance and identify failure modes.
• Build dashboards, metrics, and reports to track system performance and fleet health over time.
• Document integration workflows, test results, and lessons learned to improve future build efficiency.
• Contribute to the automation of regression testing and continuous validation across the robot fleet.

Requirements: 

• Bachelor’s or Master’s degree in Robotics, Electrical Engineering, Mechanical Engineering, Computer Science, or a related field.
• 3–5+ years of experience working with complex robotic or electromechanical systems.
• Proficiency in C++ and Python for software development, scripting, and debugging.
• Strong system-level understanding across hardware, firmware, and software layers.
• Experience with Linux, Git, and standard diagnostic tools (oscilloscope, multimeter, log analyzers).
• Hands-on experience validating real-time control systems, behaviors, or perception pipelines.
• Ability to thrive in a fast-paced, lab-focused R&D and production environment.

Bonus Qualifications: 

• Experience with humanoid or legged robots.
• Familiarity with ROS2, behavior trees, or motion planning frameworks.
• Background in hardware bring-up, calibration systems, or production-level validation.
• Exposure to high-reliability or safety-critical robotic systems.

The US base salary range for this full-time position is between $170,000 - $250,000 annually.

The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended. 

Role 

We are looking for a Software Engineer (Reliability) to join our team in San Jose, CA, reporting to the Vice President of Engineering. This is a hybrid role three days a week onsite within the Service Platform Automation department.

You will build and operate the orchestration and reliability automation that manages ZIA’s fleet lifecycle at massive scale. This is a high-ownership role: you will design and implement orchestration workflows and the supporting services needed for safe, deterministic, idempotent fleet operations—while helping the team evolve toward AI-first execution and operations.

What you’ll do (Role Expectations)

• Replace legacy Python/Ansible with a centralized, deterministic orchestration platform, refactoring automation into modular, well-defined workflows while retiring external dependencies and nested logic

• Engineer execution patterns with retries, idempotency, rate limits/backpressure, and safe rollbacks/compensation designs aligned to global fleet capacity

• Implement safe rollouts using segmentation, canaries, and automated health checks to limit blast radius during fleet-wide upgrades and remediation

• Add strong observability and auditability (metrics, traces, replayable histories), participate in on-call rotation, and drive software based fixes to reduce toil following post-incident reviews

• Integrate AI/LLM capabilities to accelerate legacy code migration and enhance safe operational outcomes through intelligent triage, correlation, and automated runbook generation

Who You Are (Success Profile)

• You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environment, seeing ambiguity not as a hindrance, but as the raw material to build something meaningful.

• You act like an owner. Your passion for the mission fuels your bias for action. You operate with integrity because you genuinely care about the outcome. True ownership involves leveraging dynamic range: the ability to navigate seamlessly between high-level strategy and hands-on execution.

• You are a problem-solver. You love running towards the challenges because you are laser-focused on finding the solution, knowing that solving the hard problems delivers the biggest impact.

• You are a high-trust collaborator. You are ambitious for the team, not just yourself. You embrace our challenge culture by giving and receiving ongoing feedback—knowing that candor delivered with clarity and respect is the truest form of teamwork and the fastest way to earn trust.

• You are a learner. You have a true growth mindset and are obsessed with your own development, actively seeking feedback to become a better partner and a stronger teammate. You love what you do and you do it with purpose.

What We’re Looking for (Minimum Qualifications)

• BS/MS in Computer Science or a related technical field with 5+ years of experience building and operating production-grade software systems

• Strong proficiency in backend/systems languages (Go, Java, C++, or Rust) with the ability to write high-quality, maintainable code

• Deep experience designing and operating distributed systems, including concurrency, failure handling, performance optimization, and data modeling

• Proven track record of building automation using REST APIs and Swagger with strong guarantees for idempotency, verification, and safe rollout patterns

• Hands-on experience with cloud platforms (AWS/GCP, GKE, Cloud SQL etc.) and proficiency in containerization and CI/CD workflows using Docker and GitLab

What Will Make You Stand Out (Preferred Qualifications)

• Experience with Temporal (or similar platforms) to architect large-scale fleet systems for patching, upgrades, and remediation using deterministic, health-gated workflows and replay-safe designs

• Testing discipline for orchestration and state machines, including E2E harnesses, determinism verification, fault injection, and chaos engineering to ensure system reliability

• Proficiency in PostgreSQL, including SQL development and schema management, to power high-scale, stateful management-plane services and workflows

#LIHybrid #LI-BH1

What you’ll do:

• Work on the verification and validation of safety-critical software components for the Platform Software components in accordance with DO-178C standards.
• Design, develop, and document comprehensive test plans, test cases, and test procedures derived from high-level and low-level software requirements.
• Execute Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) testing to verify platform software algorithms and low-level drivers.
• Identify, document, and track software defects using automated tracking systems; collaborate with embedded developers to analyze root causes and verify fixes.
• Develop and maintain automated test scripts and frameworks (C/C++, Python) to improve testing efficiency and coverage.
• Design and execute tests to verify software fault detection and diagnostic algorithms, including system faults, component failures, and sensor anomalies.
• Participate in software audits and reviews to ensure all verification activities comply with DO-178C certification requirements.

General

• Excellent verbal and written interpersonal communication
• Excellent Organizational skills
• Collaborative mindset
• Passion for learning and problem solving

What you need:

• 3+ years of experience in a related field
• At least a BS in Electrical Engineering, Computer Engineering, Computer Science, or related degree
• Strong knowledge of C/C++ for code analysis and scripting languages (like Python) for test automation.
• Familiarity with safety critical software development and verification standards (DO-178C, ISO 26262, ASIL) to high criticality levels (DAL-A/B or ASIL C/D)
• Hands-on experience through the Full Software Verification Life Cycle, including requirement traceability and verification reporting.
• Experience testing low-level communication protocols (CAN, RS-422/485, ARINC-429, SPI, I2C, Ethernet).
• Working knowledge of a Real Time Operating Systems (RTOS)
• Familiarity with diverse tools and technologies used for the development, testing and analysis
• Demonstrated experience with hardware debugging and lab equipment use (oscilloscopes, logic analyzers, power supplies). 

Bonus qualifications

• Using unit test framework for coverage metrics to support certification objectives.

Please note that this job description is intended to provide a general overview of the position and does not include an exhaustive list of responsibilities and qualifications At Archer we aim to attract, retain, and motivate talent that possess the skills and leadership necessary to grow our business. We drive a pay-for-performance culture and reward performance that supports the Company’s business strategy . For this position we are targeting a base pay between $140,000 - 170,000. Actual compensation offered will be determined by factors such as job-related knowledge, skills, and experience.Archer is committed to working with and providing reasonable accommodations to job applicants with physical or mental disabilities, and those with sincerely held religious beliefs. Applicants who may require reasonable accommodation for any part of the application or hiring process should provide their name and contact information to Archer’s People Team at people@archer.com. Reasonable accommodations will be determined on a case-by-case basis. By applying, you agree to be bound by our candidate privacy policy.