This role is for one of the Weekday's clients

Salary range: Rs 400000 - Rs 1200000 (ie INR 4-12 LPA)

Experience: 2+ yrs

Location: Bengaluru

Job Type: Full-Time

We are looking for a skilled SoC Integration Engineer to join our VLSI engineering team and contribute to the integration of complex System-on-Chip (SoC) designs. The ideal candidate will have strong expertise in SoC Integration, Verilog, and SpyGlass, with a solid understanding of RTL integration, design validation, and quality checks across multiple IPs.

In this role, you will collaborate closely with Design, Verification, Physical Design, and DFT teams to integrate and validate SoC components, ensure design quality, resolve integration challenges, and support successful tape-outs. You will play a key role in delivering scalable, high-quality SoC solutions while adhering to industry best practices and advanced design methodologies.

Requirements

Key Responsibilities

• Integrate multiple IP blocks into complex SoC designs while ensuring seamless functionality and compatibility.
• Perform RTL integration using Verilog and maintain clean, modular, and reusable design structures.
• Execute lint, structural, and quality checks using SpyGlass to identify and resolve design issues.
• Analyze and resolve integration, connectivity, clocking, and reset-related issues across SoC subsystems.
• Collaborate with Design, Verification, DFT, and Physical Design teams throughout the SoC development lifecycle.
• Validate design constraints and ensure compliance with project-specific integration guidelines.
• Support synthesis, timing, and implementation teams during design handoff and integration reviews.
• Debug RTL integration issues and perform root cause analysis to ensure timely resolution.
• Participate in design reviews, documentation, and continuous process improvement initiatives.
• Ensure high-quality deliverables that meet project timelines, design standards, and tape-out requirements.

What Makes You a Great Fit

• Strong hands-on experience as a SoC Integration Engineer working on complex semiconductor designs.
• Proficiency in Verilog for RTL integration, debugging, and design validation.
• Hands-on experience with SpyGlass for linting, structural analysis, and design quality checks.
• Good understanding of SoC architecture, IP integration, clock/reset architecture, and RTL design methodologies.
• Familiarity with CDC (Clock Domain Crossing) analysis and resolution techniques is an added advantage.
• Exposure to Synopsys Design Compiler and synthesis flows is preferred.
• Strong debugging, analytical, and problem-solving skills with attention to design quality.
• Ability to collaborate effectively with cross-functional engineering teams in a fast-paced development environment.
• Good communication skills and the ability to manage multiple integration activities simultaneously.
• Passion for delivering high-quality, scalable SoC solutions with a focus on engineering excellence and continuous improvement.