· Configure and integrate Arm processor IP (e.g., Cortex-M series) and associated subsystem components including bus interconnects, memory controllers, and peripheral IP

· Define and implement subsystem-level RTL integration, ensuring correct connectivity, clocking, and reset architecture across all subsystem components

· Collaborate with SoC architects to translate subsystem requirements into a coherent RTL implementation

· Work closely with the verification team to define and develop comprehensive testplans covering subsystem functionality, processor interfaces, and IP integration

· Author and review design specifications and integration guides for the processor subsystem

· Identify and resolve integration issues across IP boundaries, including protocol, clocking, and reset domain crossings

· Support synthesis and timing closure for the processor subsystem in coordination with the physical design team

· Participate in design reviews and contribute to continuous improvement of design and integration methodologies

· Support bring-up and debug activities for the processor subsystem on post-silicon hardware

· Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

· 7+ years of experience in ASIC/SoC design with a focus on processor subsystem integration

· Strong proficiency in RTL design and integration using SystemVerilog or VHDL

· Experience working with AMBA bus protocols (AHB, APB, AXI) in the context of subsystem integration

· Demonstrated experience collaborating with verification teams on testplan definition and functional coverage

· Familiarity with industry-standard EDA tools for RTL compile and simulation (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)

· Familiarity with synthesis flows and static timing analysis in the context of processor subsystems

· Experience with Arm Corstone or similar processor subsystem reference designs, including hands-on configuration and integration of Arm processor IP (Cortex-M series or similar)

· Knowledge of low-power design techniques and their application within processor subsystems

· Familiarity with Arm tools such as Socrates, Configuration Wizard, or similar IP configuration tools

· Experience with scripting languages (e.g., Python, Tcl, Perl) for design automation and EDA tool flows

· Experience with UPF-based power-aware design flows

· Background in satellite IoT, embedded communications, or similarly constrained application domains

· Experience with post-silicon bring-up and debug of processor subsystems

• Lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes

• Develop and enhance STA methodologies across the full RTL-to-GDS flow, including early timing estimation, feasibility checks, synthesis and place-and-route optimization, signoff criteria, and post-route ECO strategies

• Architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA and runtime efficiency

• Drive signoff correlation and closure using PrimeTime and related tools (PT-SI, PTPX, PT-ECO)

• Debug timing constraints, resolve timing correlation issues, and develop effective timing closure strategies

• Explore and deploy data-driven and ML-assisted techniques to improve STA automation, predict and prioritize timing risk, and guide optimization across blocks and full-chip

• Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity

• Continuously refine workflows and introduce new technologies to ensure robust, PPA-optimized timing solutions across all product lines

• Provide timing closure guidance and mentorship to design and physical design engineers

• BS or MS in Electrical or Computer Engineering, or equivalent industry experience

• 8+ years of industry experience in STA and timing methodology, focused on high-performance and low-power designs at advanced technology nodes

• Deep knowledge of STA tools and techniques, including noise, crosstalk, OCV, AOCV, POCV, and LVF analysis

• Fluency with PrimeTime and related signoff tools (PT-SI, PTPX, PT-ECO), with extensive hands-on experience driving signoff correlation and closure

• Strong expertise in debugging timing constraints and resolving timing correlation issues across complex SoC designs

• Experience with MMMC analysis, timing ECO flows, and late-stage timing closure techniques

• Proficiency in writing robust, production-quality scripts in Tcl, Python, and/or Perl for CAD utilities and flow components

• Solid knowledge of clock tree synthesis (CTS) and its interaction with timing analysis

• Excellent communication and collaboration skills for cross-functional, multi-project environments

• Experience with advanced process nodes (7nm, 5nm, or below)

• Familiarity with low-power design methodologies and their timing implications (DVFS, power gating)

• Exposure to interface protocol timing (DDR, PCIe, USB, SerDes)

• Experience applying ML or data-driven methods to EDA flow optimization

• Background in satellite communication, 5G, or IoT SoC design

• Lead physical design implementation from floorplanning through GDSII sign-off for complex SoC blocks and full-chip designs

• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), and routing

• Drive physical design closure meeting PPA (Power, Performance, Area) targets across all design corners

• Collaborate with the STA team to analyze and resolve timing violations through ECO-driven optimization

• Conduct and resolve physical verification (DRC, LVS, ERC) issues in partnership with the signoff team

• Develop and maintain physical design scripts, flows, and automation in Tcl/Python

• Work with foundry process design kits (PDKs) and ensure design rule compliance on advanced nodes

• Support integration of hard macros, memory compilers, and analog IP into top-level designs

• Analyze and optimize signal integrity, including crosstalk and noise effects

• Contribute to physical design methodology development and mentor junior engineers

• Minimum 8+ years of experience in physical design of complex digital ASICs or SoCs

• Deep expertise in Cadence Innovus, with broad familiarity with other P&R tools such as Synopsys ICC2

• Strong experience in floorplanning, power planning, placement, CTS, and routing for multi-million gate designs

• Deep knowledge of timing-driven physical design and working with STA engineers for timing closure

• Experience with physical verification tools (Mentor Calibre, Synopsys ICV) and DRC/LVS debug

• Proficiency in scripting (Tcl, Python) for flow development and automation

• Solid understanding of low-power design techniques (clock gating, power domains, UPF/CPF)

• Experience with advanced process nodes and associated PDK constraints

• Strong problem-solving skills and attention to detail in a deadline-driven environment

• Experience with 7nm or sub-7nm process nodes

• Exposure to custom digital or mixed-signal IC physical design

• Familiarity with signal integrity analysis tools and methodology

• Experience with hierarchical physical design flows for very large SoCs

• Background in satellite, 5G, or IoT chip design

• Lead EM/IR drop analysis for complex SoC designs at block and full-chip levels across all process corners

• Define and implement power delivery network (PDN) strategy to meet EM/IR sign-off requirements

• Perform static and dynamic IR-drop analysis and work with physical design teams to implement power grid improvements

• Analyze electromigration violations and develop mitigation strategies for metal and via connections

• Collaborate with physical design engineers to optimize power grid density, via stacking, and decap placement

• Develop and maintain EM/IR analysis flows, scripts, and automation infrastructure

• Work with foundry design rules and reliability specifications to ensure sign-off compliance

• Define power intent (UPF/CPF) requirements and validate implementation against power management intent

• Provide power analysis results and recommendations to design leadership and cross-functional teams

• Document EM/IR methodology guidelines, best practices, and sign-off reports

• Minimum 8+ years of experience in EM/IR analysis and power integrity for complex ASICs or SoCs

• Hands-on proficiency with industry-standard EM/IR tools such as Cadence Voltus, Synopsys RedHawk, or equivalent

• Deep understanding of power delivery network design, power grid analysis, and IR-drop mitigation techniques

• Strong knowledge of electromigration physics, EM rules, and reliability analysis methodologies

• Experience with both static and dynamic power analysis including vectorless and vector-based approaches

• Solid understanding of low-power design techniques and their interaction with power integrity

• Proficiency in scripting (Tcl, Python) for EM/IR flow development and result automation

• Familiarity with advanced process node design rules and foundry reliability specifications

• Excellent ability to communicate complex analysis results clearly to cross-functional teams

• Experience with 7nm or sub-7nm EM/IR sign-off requirements

• Exposure to thermal analysis and electro-thermal co-simulation

• Familiarity with package-level power integrity and chip-package co-design

• Experience with advanced power management architectures (DVFS, multiple voltage domains, retention)

• Background in satellite communication, 5G, or high-reliability IoT chip design

• Define and implement end-to-end DFT architecture and strategy for complex SoC designs, including scan, MBIST, BIST, and JTAG/IEEE 1149.x

• Insert and verify scan chains, compression logic, and test wrappers using industry-standard DFT tools

• Own the full ATPG lifecycle: verification, coverage analysis, pattern generation, and ATE bring-up

• Perform fault simulation and analyze test coverage metrics to meet manufacturing test requirements

• Collaborate with physical design teams to optimize scan chain ordering, routing, and test timing

• Define and implement memory BIST (MBIST) and logic BIST (LBIST) strategies for embedded memories

• Work with ATE teams to develop test programs and validate tester compatibility

• Develop DFT automation scripts and integrate DFT flows into the overall design implementation flow

• Perform DFT sign-off verification and resolve DRC/functional issues related to DFT logic

• Document DFT specifications, methodology guidelines, and test coverage reports

• MS/PhD or equivalent experience in Electrical Engineering or a related field

• Minimum 8+ years of hands-on experience in Design-for-Test (DFT) for complex digital ASICs or SoCs

• Hands-on experience with industry-standard DFT tools such as Synopsys DFT Compiler, Tessent, or equivalent

• Strong expertise in scan insertion, ATPG pattern generation (stuck-at, transition, IDDQ), and fault simulation

• Experience with compression architectures (EDT, DFTMAX) and advanced DFT techniques

• Working knowledge of MBIST architectures and embedded memory test strategies

• Familiarity with JTAG/IEEE 1149.1, IEEE 1500, and IEEE 1687 (iJTAG) standards

• Proficiency in scripting (Tcl, Python, Perl) for DFT flow automation and analysis

• Experience collaborating with physical design and STA teams for scan chain closure

• Strong understanding of digital design fundamentals and RTL design practices

• Passion for mentoring engineers and scaling technical excellence across a team

• Experience with IEEE P1838 (3D-IC test standards) or die-to-die interface test

• Exposure to at-speed test methodologies, on-chip clock control for at-speed test, and diagnosis flows for yield improvement

• Experience with system-level test and in-system test (IST) approaches

• Familiarity with ATE platforms (Advantest, Teradyne) and test program development

• Expertise in using programming languages and AI tools for test flow automation

• Background in satellite communication, 5G NR, or IoT SoC designs

• Develop embedded firmware in C/C++ for SoC systems
• Work with real-time operating systems and multi-threaded applications
• Implement low-level drivers and hardware interfaces
• Debug system-level issues involving hardware and software interaction
• Interface with FPGA designs, including register access, control paths, and data movement
• Collaborate closely with FPGA and hardware teams

• • Data Ingestion and Pipeline Development

  ◦ Design and build data ingestion pipelines from sensors including IMUs, accelerometers, gyroscopes, microphones, and other environmental sensors

  ◦ Handle raw sensor data: cleaning, labeling, synchronization, and storage

  ◦ Build tools to collect, version, and manage training datasets at scale

  • Model Development and Training

  ◦ Develop and train ML models for classification, regression, anomaly detection, and signal processing tasks

  ◦ Select appropriate model architectures for each problem and hardware target

  ◦ Fine-tune pre-trained models for domain-specific tasks and data distributions

  ◦ Design and run experiments to evaluate and compare model performance

  • TinyML and Embedded Deployment

  ◦ Optimize models for deployment on microcontrollers and edge processors such as ARM Cortex-M, RISC-V, and DSPs

  ◦ Apply quantization, pruning, and knowledge distillation to reduce model size and inference latency

  ◦ Use frameworks including TensorFlow Lite Micro, Edge Impulse, ONNX Runtime, and ExecuTorch

  ◦ Integrate ML inference into embedded firmware written in C, C++, or Rust

  ◦ Profile and optimize memory usage, power consumption, and real-time performance

  • Hybrid LLM Integration

  ◦ Design hybrid architectures that combine on-device lightweight models with LLM-based reasoning

  ◦ Build pipelines that route tasks between edge inference and cloud or edge-hosted LLM components

  ◦ Evaluate trade-offs in latency, accuracy, and power between on-device and LLM-assisted approaches

  • Software Embedding and Systems Integration

  ◦ Write clean, well-tested embedded software that integrates ML inference into real-time systems

  ◦ Work with RTOS environments such as FreeRTOS and Zephyr, as well as bare-metal firmware

  ◦ Collaborate with hardware and firmware teams to co-optimize the full system stack

  • Documentation and Reporting

  ◦ Document design decisions, pipeline configurations, model benchmarks, and deployment procedures

  ◦ Prepare technical reports and presentations for internal teams and stakeholders

  ◦ Stay current with developments in TinyML, embedded AI, and edge computing and bring relevant innovations into the team

  • Collaboration and Support

  ◦ Work closely with cross-functional teams including hardware engineers, firmware developers, and data scientists

  ◦ Provide technical support during hardware bring-up, system integration, and field testing

  ◦ Participate in design reviews and contribute constructive feedback across the stack

• • Experience with RTOS platforms such as FreeRTOS or Zephyr

  • Familiarity with MCU families including NXP, STM32, ESP32, or similar

  • Experience designing hybrid edge-LLM pipelines or integrating small language models on device

  • Background in feature extraction techniques such as FFT, filter banks, and wavelet transforms

  • Experience with hardware-aware neural architecture search or AutoML for edge targets

  • Familiarity with Rust for embedded or systems programming

  • Prior work on products in wearables, robotics, industrial sensing, or IoT

• Design DC/DC converter power stages including switching device selection, filter design, driver circuits, and magnetics.
• Develop battery management and charge regulation circuits with appropriate safety, cycle-life, and charging-profile considerations.
• Perform control-loop modeling and compensation for analog and digitally controlled power supplies.
• Design fault-protection circuits including overcurrent break, current clamp, overvoltage clamp, crowbar, and foldback protection.
• Implement current, voltage, and temperature sensing circuits with filtering, threshold triggers, and ADC integration.
• Perform component derating analysis and design for radiation tolerance across all power subsystems.
• Develop load accounting, mode-based power consumption estimates, and concept-of-operations power budgets.
• Design power distribution networks with DC load switches, telemetry, and protection for multiple subsystem loads.
• Collaborate with PCB layout engineers on power supply layout optimization (loop area minimization, noise reduction, switching node management).
• Support FPGA and digital teams with power supply sequencing, support circuitry, and power integrity requirements.

• Experience with satellite or spacecraft power subsystems (PDU, BMS, BCR, solar array interfaces).
• Background in lithium-ion battery performance, safety, and packaging considerations.
• Experience with motor-drive design and inductive-load drivers (solenoids, magnetorquers).
• Familiarity with orbit-geometry analysis for power-balance and eclipse-cycle planning.
• Understanding of solar panel I-V characteristics, harvesting topologies, and degradation modeling.
• Supply-chain awareness including long-lead component identification and pre-buy strategies.

• SPICE-based circuit simulation (LTSpice, PSpice, or equivalent)
• Altium Designer (schematic capture)
• HyperLynx PI (power integrity analysis)
• MATLAB or Python for control-loop modeling and power budget analysis

• Develop PCB stack-ups for complex mixed-signal, power, and RF designs with appropriate impedance control.
• Perform component placement optimized for signal integrity, thermal management, and manufacturability.
• Route high-speed digital interfaces (SERDES, DDR, LVDS) with impedance-controlled transmission lines.
• Implement power distribution plane design with attention to current density, loop area, and decoupling strategy.
• Apply mixed-signal layout techniques with proper analog, digital, and RF isolation and partitioning.
• Create and maintain footprint libraries and serve as Altium librarian for the program.
• Manage design-rule and constraint creation including clearances, lengths, impedance targets, vias, and creepage/clearance requirements.
• Produce layout documentation including fabrication drawings, assembly drawings, layer stack tables, and manufacturing notes.
• Address RF parasitic effects through ground fencing, stitching vias, partitioning, and shielding techniques.
• Coordinate with fabrication and assembly vendors for DFM reviews and manufacturing handoff.

• Experience with aerospace or space-grade PCB layouts and qualification requirements.
• Background in RF/microwave PCB layout including matching networks and transmission-line structures.
• Familiarity with signal integrity and power integrity simulation tools (HyperLynx, Sigrity).
• Experience with Zuken CR-8000 or other enterprise PCB CAD tools.
• Knowledge of high-speed signal attenuation, dispersion, and copper-loss mechanisms.
• Experience with flex and rigid-flex PCB design.

• Altium Designer (primary layout tool)
• Zuken CR-8000
• HyperLynx (SI/PI review support)
• ODB++ and CAM output tools

• Develop UVM-based verification environments including agents, scoreboards, and bit-accurate reference models.
• Create and maintain a reusable, extendable UVM framework supporting multiple FPGA targets and device configurations.
• Write verification plans derived from requirements specifications and architectural documents.
• Develop functional coverage models and drive coverage closure for all FPGA designs.
• Perform RTL simulation using industry-standard tools.
• Implement clock-domain crossing verification and timing/stability analysis.
• Apply lint and static-analysis tools to identify design issues early in the development cycle.
• Support hardware bring-up by creating tests that model and recreate hardware interactions in simulation.
• Document verification results, coverage metrics, and test plans with clear technical writing.
• Collaborate with FPGA designers and system engineers to refine requirements and close verification gaps.

• Experience verifying designs for space, aerospace, or high-reliability applications.
• Familiarity with formal verification tools.
• Background in embedded software interaction with FPGA firmware.
• Experience with continuous integration workflows for verification regressions.
• Proficiency in Python, TCL, or shell scripting for test automation and infrastructure.
• Exposure to DFMEA and high-reliability digital design review processes.

• Industry-standard RTL simulators (e.g., VCS, QuestaSim, or equivalent)
• UVM verification methodology
• Lint and CDC analysis tools
• Python/TCL scripting for automation

• Design and implement RTL in SystemVerilog or VHDL for satellite avionics FPGAs across a variety of FPGA platforms.
• Develop AXI Memory-Mapped and AXI-Stream protocol implementations for inter-subsystem communication.
• Perform FPGA resource and size estimation including logic, memory, and DSP budgeting.
• Implement clock-domain-crossing (CDC) design techniques and verify timing closure across designs.
• Design clock/reset tree architectures and manage timing-closure strategies for complex multi-clock designs.
• Develop SPI, I²C, GPIO, and other low-speed peripheral interfaces alongside high-speed transceiver links.
• Apply fault-tolerant digital design techniques including TMR, ECC, scrubbing, and SEE mitigation.
• Perform synthesis and place-and-route using vendor toolchains, including custom placement constraints.
• Support board bring-up by developing configuration, interface verification, and debug test sequences.
• Collaborate with digital design, power, and PCB layout engineers to ensure FPGA support circuitry meets requirements.

• Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based, anti-fuse architectures).
• Background in signal processing (FFT, FIR/IIR filters) and DSP integration.
• Experience with transceiver design and high-speed serial communications on FPGAs.
• Exposure to DAC/ADC interfaces and mixed-signal digital handling.
• Experience with satellite or spacecraft FPGA applications.
• Proficiency in Python or TCL scripting for automation and build infrastructure.

• FPGA vendor toolchains (synthesis, place-and-route, timing analysis)
• RTL simulation tools (e.g., VCS, QuestaSim, or equivalent)
• Python, TCL, or shell scripting for build automation
• Makefiles for FPGA build workflows

• Assemble and rework prototype PCBs including surface-mount, fine-pitch, and through-hole soldering.
• Build cable and wire-harness assemblies including crimping, routing, strain-relief, and connectorization.
• Operate electronic test equipment (oscilloscopes, multimeters, logic analyzers, spectrum analyzers) for board-level testing.
• Support board bring-up activities by assisting engineers with lab setups, instrumentation, and measurements.
• Perform board modifications (cut-and-jump, component replacement, rework) per engineering change orders.
• Maintain lab equipment calibration schedules and ensure instrumentation is in working order.
• Follow ESD-safe handling procedures and maintain ESD-controlled workspaces.
• Create and maintain build documentation and assembly records.
• Support environmental test preparation and execution (thermal, vibration, shock).
• Assist with sub-contractor coordination for fabrication and assembly when required.

• IPC-A-610 and/or J-STD-001 certification (or willingness to obtain).
• Experience with space-grade or high-reliability hardware assembly and workmanship standards.
• Background in cable and harness assembly (IPC/WHMA-A-620).
• Experience with X-ray inspection, conformal coating, or staking procedures.
• Familiarity with environmental test equipment and procedures.
• Experience supporting qualification and acceptance test campaigns.

• IPC-A-610 and/or J-STD-001 certification (or willingness to obtain).
• Experience with space-grade or high-reliability hardware assembly and workmanship standards.
• Background in cable and harness assembly (IPC/WHMA-A-620).
• Experience with X-ray inspection, conformal coating, or staking procedures.
• Familiarity with environmental test equipment and procedures.

• Own schematic design and component selection for digital avionics boards, from concept through flight qualification.
• Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces with proper timing closure.
• Develop clocking architectures including PLL configuration, jitter management, and clock distribution networks.
• Perform power budgeting and system-level power allocation across board subsystems.
• Apply radiation-tolerant design techniques including SEU/SEE mitigation, TID considerations, and appropriate component derating.
• Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout requirements.
• Drive board bring-up activities including configuration, interface verification, and structured debugging.
• Participate in design reviews and cross-functional integration with RF, power, thermal, and mechanical teams.

• Experience with satellite or spacecraft avionics design and qualification (EM/QM/FM build cycles).
• Background in non-volatile memory technologies (Flash, MRAM, FRAM) and in-system programmability.
• Exposure to power supply design and power integrity analysis for digital boards.
• Experience with design for radiation reliability and single-event effects mitigation at the board level.
• Familiarity with signal integrity simulation tools (HyperLynx SI/PI, Ansys, ADS).

• Altium Designer (schematic capture and layout review)
• HyperLynx SI, SI/PI, and Full-Wave (signal and power integrity)
• SPICE-based circuit simulation
• FPGA vendor toolchains (for interface bring-up and debug)

• Perform component-level thermal analysis including junction temperature calculation, hot-spot identification, and heat-path evaluation.
• Develop thermal models using analytical methods and simulation tools for steady-state and transient conditions.
• Evaluate and recommend cooling strategies (conduction, convection, radiation, heat spreading) for avionics boards.
• Assess temperature effects on component aging, reliability, and derating requirements.
• Analyze thermomechanical degradation risks including CTE mismatch, solder fatigue, and connector stress.
• Perform system-level thermal budgeting and define thermal interface requirements across subsystems.
• Evaluate environmental thermal loads from orbit-induced temperature swings and operational heat dissipation.
• Select materials based on thermal conductivity, expansion properties, and long-term reliability.
• Validate thermal models with empirical measurements and test data from EM and QM builds.
• Collaborate with electrical, mechanical, and reliability engineers for integrated thermal solutions.
• Document thermal requirements, design guidelines, and analysis results.

• Experience with satellite or spacecraft thermal analysis and orbital thermal environments.
• Background in thermal cycling test planning and correlation of simulation to test results.
• Familiarity with Ansys IcePak specifically.
• Experience with system-level thermal budgets and interface management.
• Knowledge of PCB material properties and their thermal behavior.
• Understanding of reliability implications of thermal stress on electronics.

• Ansys IcePak (or equivalent thermal simulation tool)
• MATLAB or Python for analytical modeling
• CAD tools for geometry import and model setup

• Perform board-level reliability simulations using Ansys Sherlock and related analysis tools.
• Develop and execute HALT/HASS test strategies for avionics boards.
• Conduct Mean Time To Failure (MTTF) modeling and life-prediction analysis for board assemblies.
• Perform Weibull analysis and reliability-distribution modeling from test and field data.
• Develop DFMEA/FMEA and integrate findings into design cycles.
• Identify infant-mortality characteristics and develop early-life failure reduction strategies.
• Create stress screening plans covering thermal, vibration, and electrical overstress.
• Perform component derating analysis aligned with reliability standards for space applications.
• Evaluate electronic components for radiation tolerance (TID, SEE, SEU, SEL, SET, SEB) in collaboration with design engineers.
• Analyze semiconductor manufacturing processes and their impact on radiation performance.
• Document reliability results, methods, and recommendations clearly for design teams.
• Collaborate with design, manufacturing, and test teams to improve long-term system robustness.

• Experience with satellite or spacecraft hardware reliability analysis.
• Background in radiation effects analysis and component qualification for space.
• Familiarity with Weibull analysis tools and accelerated-life testing methods.
• Experience interpreting radiation test reports and vendor lot-specific performance data.
• Knowledge of IPC and ECSS reliability standards.
• Understanding of PCB manufacturing processes and their reliability implications.

• Ansys Sherlock (board-level reliability simulation)
• MATLAB or Python for statistical analysis and modeling
• Reliability prediction tools (FIDES, MIL-HDBK-217, or equivalent)