This role is for one of the Weekday's clients

Min Experience: 4+ years

Location: Bengaluru

JobType: full-time

We are looking for a talented and detail-oriented DFT (Design for Test) Engineer with 4–8 years of experience in semiconductor design and test engineering. In this role, you will be responsible for implementing and validating Design-for-Test (DFT) architectures for complex System-on-Chip (SoC) designs, ensuring high manufacturing test coverage, quality, and reliability.

The ideal candidate will have strong expertise in SoC DFT methodologies, with hands-on experience in MBIST (Memory Built-In Self-Test) and LBIST (Logic Built-In Self-Test) implementation. You will collaborate closely with RTL, design, verification, physical design, ATPG, and manufacturing teams throughout the chip development lifecycle to deliver high-quality silicon.

This role offers the opportunity to work on advanced semiconductor technologies, solve challenging design problems, and contribute to next-generation SoC products used across a wide range of applications.

Requirements

Key Responsibilities

• Design, implement, and integrate DFT architectures for complex SoC designs.
• Develop and maintain DFT strategies that improve testability while minimizing area, timing, and power overhead.
• Implement and validate MBIST architectures for embedded memories across multiple SoC subsystems.
• Develop and integrate LBIST solutions to improve logic test coverage and support in-system testing.
• Perform scan insertion, scan chain planning, and DFT logic integration into RTL and gate-level designs.
• Generate and validate ATPG patterns to achieve high fault coverage for manufacturing tests.
• Analyze DFT-related timing, coverage, and implementation issues, and work with design teams to resolve them.
• Collaborate with physical design teams to ensure successful DFT implementation while meeting timing and routing constraints.
• Support silicon bring-up, production testing, and failure analysis by debugging manufacturing test issues.
• Review DFT architecture specifications, test plans, and design documentation to ensure compliance with quality standards.
• Work closely with cross-functional engineering teams to optimize DFT methodologies and improve overall product quality.

Required Skills & Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• 4–8 years of hands-on experience in DFT engineering for semiconductor or SoC development.
• Strong expertise in SoC DFT implementation and verification.
• Proven experience with MBIST architecture, integration, and validation.
• Strong knowledge of LBIST implementation and test methodologies.
• Solid understanding of scan architecture, scan compression, boundary scan, JTAG, and IEEE test standards.
• Experience with ATPG generation, fault simulation, and test coverage analysis.
• Good understanding of digital design fundamentals, RTL design, Verilog/SystemVerilog, and synthesis flows.
• Familiarity with timing closure, physical design constraints, and DFT-aware implementation.
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication and collaboration skills with cross-functional engineering teams.

Good-to-Have Skills

• Experience working on SoC architecture and integration.
• Exposure to advanced semiconductor process nodes.
• Knowledge of low-power DFT techniques and power-aware testing.
• Familiarity with scripting languages such as Tcl, Perl, or Python for DFT automation.
• Understanding of silicon validation, yield improvement, and production test optimization.
• Experience with industry-standard EDA tools for DFT implementation and ATPG.
• Knowledge of functional verification and simulation methodologies.
• Exposure to safety-critical or automotive semiconductor standards is an advantage.