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Sobre este puesto de Design Verification Engineer en Weekday AI

Weekday AI · Presencial · Hyderabad, Telangana, India

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟱𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭-𝟱𝟬 𝗟𝗣𝗔)

Experience: 7+ yrs

Location: Hyderabad, Telangana, India

Job Type: Full-time

We are looking for an experienced Senior Full-Chip Verification Engineer to contribute to the development and verification of next-generation NAND Flash Memory technologies. The role combines full-chip verification leadership, SystemVerilog/UVM-based verification, circuit simulation, cross-functional technical collaboration, and AI-assisted engineering.

The ideal candidate will have strong expertise in full-chip verification, verification planning, testbench development, SystemVerilog, and UVM, along with the ability to lead multidisciplinary teams and contribute to architectural and verification decisions.

Requirements

Key Responsibilities

  • Contribute to the development of next-generation NAND Flash Memory through verification and optimisation of memory and logic circuits.
  • Own and lead full-chip verification activities, including verification planning, execution, tracking, coverage, and completion criteria.
  • Develop comprehensive verification strategies aligned with product and architectural requirements.
  • Design and maintain scalable SystemVerilog-based testbenches for full-chip verification.
  • Implement verification environments using UVM and industry-standard verification methodologies.
  • Evaluate key product features and collaborate with multidisciplinary teams to identify technical risks and recommend architectural decisions.
  • Lead and coordinate verification activities across design, architecture, circuit, layout, and other engineering functions.
  • Analyse verification results, identify failures and coverage gaps, and drive issues through resolution.
  • Use circuit simulation tools such as XA, HSPICE, HSim, FineSim, or similar simulators as required.
  • Define verification criteria, methodologies, schedules, milestones, and deliverables for full-chip projects.
  • Track verification progress and communicate risks, dependencies, and status to relevant stakeholders.
  • Contribute to verification methodology improvements, automation, reusable environments, and engineering best practices.
  • Leverage AI-assisted coding and AI tools to automate verification workflows, tools, build processes, and design-analysis activities.
  • Identify opportunities to apply Artificial Intelligence to improve build efficiency, verification productivity, and engineering workflows.
  • Drive innovation and continuous improvement across future memory-generation development programs.
  • Provide technical leadership and mentoring to verification engineers where required.
  • Prepare technical documentation and communicate complex verification concepts clearly to technical and cross-functional stakeholders.

What Makes You a Great Fit

  • 6–8 years of proven experience in semiconductor verification, with strong experience in full-chip or complex IP verification.
  • Strong knowledge of full-chip verification methodologies, planning, execution, coverage, and verification criteria.
  • Proven hands-on expertise in SystemVerilog and testbench development.
  • Strong practical knowledge of UVM and modern verification methodologies.
  • Broad understanding of IP verification and semiconductor design verification processes.
  • Experience with circuit simulation tools such as XA, HSPICE, HSim, FineSim, or equivalent.
  • Ability to lead and coordinate multifunctional engineering teams in a project environment.
  • Strong analytical and problem-solving skills with the ability to understand complex technical issues.
  • Experience evaluating technical features and contributing to architecture and design decisions.
  • Demonstrated ability to use AI-assisted coding, automation, or AI engineering tools to improve development, verification, or analysis efficiency.
  • Strong understanding of verification automation and workflow optimisation.
  • Excellent written and verbal communication skills, with the ability to explain complex technical concepts to diverse stakeholders.
  • Strong interpersonal, collaboration, ownership, and leadership skills.
  • Experience working on memory, NAND Flash, or related semiconductor technologies would be an advantage.
  • Bachelor's, Master's, or Ph.D. degree in Electrical Engineering or a related technical discipline, or equivalent professional experience.
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