Curious about how cutting-edge hardware actually comes to life? We're looking for someone who’s excited to dive into the core of next-gen systems and help make them real. In this role, you’ll validate high-speed interfaces, solve complex system-level puzzles, and collaborate across teams to shape the future of AI/ML computing. If firmware, hardware, and hands-on debugging sound like your kind of fun — let’s chat!

This role is hybrid and based in Vancouver, Canada. 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You love bringing hardware to life and enjoy the thrill of solving tricky problems across the hardware–firmware boundary.
• You’re hands-on in the lab and comfortable with tools like oscilloscopes, protocol analyzers, and JTAG — digging deep doesn’t scare you.
• You’re comfortable jumping into unfamiliar problems and figuring things out — whether it’s in the lab or in firmware.
• You’re curious, collaborative, and excited to work on technology that pushes the boundaries of performance.

What We Need

• Someone to take the lead in validating our next-gen PCIe interfaces — from controller to PHY, and everything in between.
• A strong collaborator who can work across hardware, firmware, and software teams to bring up new features and solve problems.
• A sharp debugger who’s comfortable triaging issues across hardware, firmware, and software layers.
• A detail-oriented thinker who thrives in fast-paced environments and enjoys seeing ideas come to life in real systems.

What You Will Learn

• How to work at the cutting edge of compute — validating next-gen hardware and making it production-ready.
  How different pieces of a system come together — from multi-die chiplets to firmware integration and beyond.
  How to use advanced tools and techniques to debug and tune complex system interactions.
  How to shape emerging technology in a collaborative, fast-moving engineering environment.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an AI Processor IP Product Engineer to be the technical bridge between our cutting-edge AI processor technology and customer success. You'll guide customers through the integration of our advanced AI processors, RISC-V CPUs, and chiplet solutions into their SoCs, ensuring optimal performance and accelerated time-to-market. If you thrive in customer-facing roles and want to shape the deployment of revolutionary AI hardware across the industry, join our team.

This role is hybrid, based out of Toronto, Canada or Vancouver, Canada.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with deep technical expertise in ASIC design and IP integration.
• Experienced problem-solver who excels at debugging complex system-level issues and silicon bring-up.
• Strong communicator who builds trusted relationships while managing technical engagements across the support lifecycle.
• Passionate about enabling customer success and translating complex technical concepts into actionable guidance.

What We Need

• 3-5 years in the semiconductor industry with a degree in EE or related field.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Strong background in analog/digital design tools, silicon validation, and system-level debug.
• Proven track record in customer-facing engineering roles with excellent communication skills.

What You Will Learn

• How to integrate state-of-the-art AI processors and chiplet architectures into diverse customer SoCs.
• Advanced debugging techniques spanning pre-silicon simulation to post-silicon validation.
• Strategies for influencing product roadmaps through direct customer feedback and technical insights.
• The full spectrum of IP productization—from technical documentation to customer training and support processes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This role sits at the intersection of embedded systems, silicon validation, and advanced networking. You'll work with best-in-class IP from leading vendors and in-house designs, bringing up and validating these IPs in silicon, and building robust validation infrastructure that ensures performance, interoperability, and reliability at scale.

This role is hybrid, based out of Toronto, Canada, Vancouver Canada, Santa Clara, California or Austin, Texas.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Passionate about low-level software that brings hardware to life—seeing it run on real systems never gets old.
• Drawn to complex, cross-disciplinary problems at the intersection of hardware and software.
• Excited by high-speed networking challenges like SerDes tuning, link training, and Ethernet MAC/PHY.
• Have pride in hands-on debugging and working across teams to make systems fast, reliable, and ready for the real world.

What We Need

• A passion for breaking and fixing complex hardware-software systems.
• Comfort with designing tests that push things to their limits: functional, performance, integration—you name it.
• Experience in lab work—system bring-up, running experiments, and working with emulation tools.
• A love for writing firmware and scripts to automate testing, dig into issues, and keep things running smoothly.

What You Will Learn

• What it means to shape AI acceleration hardware from the ground up—starting at first principles.
• How to validate complex Ethernet IP from simulation all the way to production silicon.
• The mastery of collaborating with world-class silicon, systems, and software teams to tackle frontier engineering challenges.
• How to define the networking architecture that will power the next era of AI platforms.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Role Overview

As a Principal Product Applications Engineer at Astera Labs, you will be at the forefront of enabling the world's leading cloud service providers and server/network OEMs to successfully deploy connectivity solutions. This high-impact role sits at the intersection of cutting-edge silicon, firmware, and customer success—where you'll tackle complex technical challenges that push the boundaries of AI infrastructure connectivity.

You will serve as a trusted technical advisor to strategic customers, guiding them through design-in, bring-up, and optimization of Astera Labs products. With a strong firmware orientation, you'll dive deep into embedded systems, debug intricate firmware-hardware interactions, and drive issues to resolution across the full stack. Your insights from the field will directly influence product roadmaps and engineering priorities, making you a critical bridge between customers and our R&D teams.

This is an opportunity to work on industry-defining connectivity products that power next-generation data centers and AI platforms—all within a fast-paced, hypergrowth environment where your contributions have immediate and visible impact.

Key Responsibilities

• Customer Technical Engagement
  • Provide expert technical guidance to tier-1 customers throughout the design-in lifecycle, from early evaluation through production deployment
  • Build trusted relationships with customer engineering teams, serving as the go-to resource for product integration
  • Deliver technical presentations, training sessions, and design reviews to accelerate customer success
• Firmware Debug & Issue Resolution
  • Investigate and reproduce customer-reported issues involving firmware, silicon, hardware design, and system-level interactions
  • Drive root cause analysis and coordinate cross-functional teams to deliver timely resolutions
  • Develop firmware-based tools, scripts, and utilities to streamline debug and validation workflows
• Technical Collateral & Knowledge Sharing
  • Create high-quality application notes, integration guides, and technical documentation for internal and external audiences
  • Provide actionable feedback to product, firmware, and silicon teams to continuously improve products and customer experience
  • Contribute to the development of reference designs and best practices for product deployment
• Lab Validation & Bring-Up
  • Execute hands-on silicon and system bring-up activities, including firmware validation and performance characterization
  • Utilize lab equipment such as protocol analyzers, high-speed oscilloscopes, and traffic generators to diagnose complex issues
  • Support interoperability testing across diverse customer platforms and configurations

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of experience in product applications, field applications, or systems engineering roles supporting complex semiconductor products
• Strong firmware development and debugging skills, including proficiency in embedded C and Python
• Experience with high-speed interfaces such as PCIe Gen5/6/7 or Ethernet
• Demonstrated ability to triage and resolve multi-layer issues spanning silicon, firmware, and system environments
• Excellent written and verbal communication skills with a track record of producing clear technical documentation

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related field
• Experience with Ethernet products, retimers, or PCIe connectivity solutions
• Hands-on experience with protocol analyzers, high-speed oscilloscopes, and BERTs
• Background working directly with cloud service providers, server OEMs, or networking equipment manufacturers
• Understanding of data center architectures including servers, AI platforms, JBOGs/JBODs, and network switches
• Familiarity with physical layer concepts and signal integrity fundamentals

The base salary range for this role is CAD 180,000 – CAD 205,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for a performance bonus, equity, and benefits.

Software Engineer, Senior

Shift4 is expanding globally and we are looking for a key software developer to join our innovative Software Engineering team! This opportunity involves designing, developing and deploying Shift4’s Commerce Engine payment solution that delivers a modern and integrated payment processing experience at Retail, Restaurant, and Hotel merchants.

The focal point of the solution consists of well-designed and highly functional business apps deployed on custom payment hardware. We have an ambitious product roadmap for this platform and are looking to expand the team with the best and brightest to ensure we continue to drive the industry with our innovative solutions and change the basis of competition.

This role is onsite and can be based at either of the following Shift4 locations:  Las Vegas, NV, U.S.A. or Vancouver, BC, Canada

Relocation assistance may be available. 

Responsibilities

• Translate high-level requirements to actionable tasks and deliverables.
• Contribute to architecture and design in a multiplatform ecosystem.
•  Design and build distributed software services for transaction processing.
•  Produce high quality software that is unit tested, code reviewed, and continuously integrated.
•  Collaborate with the Quality assurance team in test planning and test coverage.
•  Collaborate with DevOps and CI/CD in operational visibility, triaging incidents, and deployment planning.
• A disciplined approach to development, code review, testing, documentation and code structure in a team environment.
• Actively participate in growing and coaching fellow team members.
• Understand future business goals from Product Owners and make sure architecture and system design can support those goals.
• Build proof-of-concepts to validate architectural and design choices and evangelize those technical choices to other teams.
• Able to understand, diagnose and then solve deep technical and performance issues across the product.
• Provide development support to resolve any issues with technical systems and applications.

Qualifications

• 5+ years of Software Engineering experience in Coding, Designing and Developing software.
• Proficient in C and exposure to Object Oriented languages like C++, Java, Python or Kotlin.
• Adept in gathering and interpreting requirements, translating requirements into system definitions and solutions and creating detailed documentation.
• Ability to write modular, maintainable code with unit tests ensuring complete code coverage and adhering to coding standards.
• Troubleshoot and resolve complex issues in embedded systems to debug and optimize system performance.
• Experience with Code repository management, code merge and quality checks, continuous integration and automated deployment and management using tools like Jenkins, Git.
• Experience working in an agile environment and familiarity with Jira, Confluence etc.
• Excellent communication skills and a quick problem solver.
• Bachelor's degree in Computer Science, Software Engineering or equivalent. Experience in lieu of a degree may be considered. 

Preferred Skills:

• Previous experience in the cards and payments industry is positive but not mandatory.
• Expertise around Point of Sale, Payment SDKs, and POS hardware experience is a big plus.

#LI-BN1

At Astera Labs, we design cutting-edge connectivity solutions that power the world’s largest cloud service providers, server, and networking OEMs. As a Platform Engineer, you’ll play a pivotal role in building and supporting the platforms that enable these products to thrive in real-world deployments through. 

You’ll create and maintain tools that make our products seamless to integrate, highly debuggable, and delightful to use for both customers and internal engineering teams. Your work will span software, systems, and silicon – developing automation, diving into labs with state-of-the-art equipment, and collaborating closely with customers to solve the toughest technical challenges. Beyond execution, you’ll influence product direction by driving innovation, providing feedback to design teams, and streamlining validation and deployment processes. 

This is a high-impact, hands-on role at the intersection of hardware and software, where curiosity, creativity, and technical depth come together to define the next generation of data center infrastructure. 

Basic Qualifications 

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or Computer Science. 
• 5+ years of experience in software development with C, C++, C#, and/or Python. 
• Entrepreneurial mindset with a customer-first attitude and a bias toward action. 

Required Experience 

• Building and maintaining complex applications using .NET technologies (e.g., WPF, Avalonia, Blazor, MAUI). 
• Strong background in C and Python programming for tool development, automation, and system interaction. 
• Hands-on silicon/system bring-up and debug experience in customer environments. 
• Proficiency with lab equipment such as traffic generators, analyzers, and high-speed oscilloscopes. 
• Excellent technical writing skills for clear, concise documentation (datasheets, app notes, internal guides). 

Preferred Experience 

• Front-end technologies (React, Angular, Node.js). 
• Cloud development platforms (Azure, AWS). 
• Experience with high-speed I/O products (PCIe, Ethernet Switches). 
• Familiarity with data center architectures: servers, storage (JBOD/JBOG), and networking gear. 

What You’ll Gain 

• Impact: Influence the design and usability of products deployed at hyperscale. 
• Breadth: Work across hardware, firmware, and software layers. 
• Growth: Collaborate with world-class engineers and customers solving real-world challenges at scale. 
• Innovation: Freedom to prototype, improve, and bring new ideas into production. 

The base pay range for this role is between $140,000 and $175,000. Your actual base pay will depend on variables that may include your background, qualifications, and experience. 

Role Overview 

Astera Labs is seeking System Validation Engineers across multiple levels to lead post‑silicon bring‑up and system validation for high‑performance PCIe and CXL memory expansion products used in AI and cloud data centers. You will design and execute validation plans, automate data‑centric test flows, drive root‑cause investigations across silicon, firmware, hardware, and systems, and work directly with customers to validate real world performance and interoperability. 

This role is based in our Vancouver office, which is a strategic growth hub for Astera Labs' validation team. You'll have the opportunity to be a foundational member of this expanding site while collaborating closely with our core team in San Jose. This is a unique chance to help shape the team's culture, processes, and technical direction as we scale our validation capabilities to meet surging demand for AI infrastructure connectivity. 

What Success Looks Like: 

• New silicon and platforms brought up on schedule with reproducible validation results 
• Automated test suites that reduce manual effort and provide clear pass/fail and performance metrics 
• Rapid, data-backed root-cause resolution of system issues and strong customer satisfaction during integration 

Key Responsibilities 

• Validation Planning & Strategy 
• Create comprehensive validation plans for AI fabric switch products covering functionality, performance, reliability, and interoperability 
• Contribute to compliance testing strategies and adapt consortium test cases for execution from x86 and ARM platforms 
• Produce clear, data-driven validation reports and status updates for internal stakeholders and customers 
• Silicon & System Bring-Up 
• Lead silicon and platform bring-up activities, verify boot and runtime behavior on x86 and ARM systems 
• Ensure timely readiness for customer engagements and product launches 
• Debug complex issues across PCIe, CXL, NVMe, Ethernet, firmware, and hardware layers using protocol analyzers, logic analyzers, and CPU-based tool suites 
• Test Automation & Infrastructure 
• Develop robust, repeatable automation for IC and board testing with emphasis on execution efficiency, data collection, analysis, and automated reporting 
• Design experiments to root-cause unexpected behavior and report results and specification compliance in an automated fashion 
• Customer & Cross-Functional Collaboration 
• Collaborate directly with customers to capture system requirements, reproduce customer scenarios, and demonstrate product capabilities 
• Drive cross-functional root-cause analysis with silicon, firmware, hardware, and system teams and document findings and corrective actions 

Basic Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 
• 2-12+ years of experience supporting or developing complex SoC or silicon products for server, storage, or networking domains (level dependent) 
• Working understanding of x86 and ARM architectures and UEFI/Linux boot sequences 
• Solid grasp of high-speed signaling principles 
• Hands-on experience with high-speed protocols such as PCIe, CXL, NVMe, or Ethernet 
• Proven experience in silicon and system bring-up, validation, and debug in lab and customer environments 
• Strong Python automation skills for bench control, test orchestration, data analysis, and reporting 
• Experience with lab equipment including protocol analyzers, logic analyzers, in-circuit debuggers, and CPU-based tool suites 
• Strong prioritization, planning, and independent execution skills with a customer-focused mindset 

Preferred Qualifications 

• Master's degree in Electrical Engineering, Computer Engineering, or related field 
• Working knowledge of C or C++ for embedded firmware and device drivers 
• Familiarity with PCIe compliance standards and experience adapting consortium tests for platform execution 
• Advanced understanding of memory architectures, high-speed signaling, and system boot flows 
• Track record of influencing cross-functional teams and navigating complex matrixed organizations 
• Entrepreneurial, can-do attitude with ability to think and act with the customer in mind 

The base salary range for this role is $125,000 - $290,000 CAD depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 

About The Team 

Cerebras builds wafer-scale AI processors—single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras’ pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE, and NeurIPS) and directly influences the design of next-generation wafer-scale systems. 

About The Role 

We are seeking R&D Engineers to join Cerebras' Advanced Technology Group. You will design and implement workloads that establish new performance benchmarks on wafer-scale hardware, leveraging architectural features that no traditional platform offers. The 
scope ranges from large-scale scientific simulations to emerging AI/ML models, and the work sits at the intersection of algorithm design, compiler co-optimization, and hardware architecture. You will collaborate closely with Cerebras’ ASIC, compiler, kernel, and AI teams as well as external partners at universities and national laboratories. 

What You Will Do 

• Design and implement challenging scientific computing and AI workloads on Cerebras’ Wafer-Scale Engine, targeting performance results that advance the state of the art. 
• Lead algorithm–hardware co-design efforts with internal R&D teams and external research partners, turning architectural capabilities into measurable application-level advantages. 
• Build analytical performance models that quantify bottlenecks, guide optimization, and inform future chip and compiler design decisions. 
• Contribute to Cerebras’ multi-year technology roadmap by identifying high-impact workloads, proposing architectural experiments, and validating them on silicon. 
• Publish findings and present at top-tier conferences and journals; represent Cerebras in the broader HPC and AI research communities. 

What We Are Looking For 

• PhD in Computer Science, Engineering, Applied Mathematics, Physics, or a related quantitative field preferred. Exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply. 
• Deep experience in at least one of the following: computer architecture and accelerator design; parallel, distributed, or high-performance computing; numerical methods and scientific simulation; AI/ML theory and model design at a mathematical level. 
• Strong ability to analytically model and optimize the performance of complex systems and algorithms. 
• Track record of published research or patents in relevant venues. 
• Proficiency in C and Python; comfort working close to hardware. 
• Excellent communication and interpersonal skills: able to present complex technical material to both specialist and cross-functional audiences, and to collaborate effectively in a fast-paced, small-team environment. 

Areas Of Particular Interest 

We are hiring across several focus areas. Exceptional depth in one or more of the following is a strong signal: 

• Computational science: researchers who can bring insights from numerical methods and simulation into AI, or couple simulation and learning into joint computational workflows. Depth in hydrodynamics, solid mechanics, electromagnetics, molecular dynamics, or related PDE-based fields. 
• AI/ML foundations: deep understanding of model architecture, optimization methods, and their statistical underpinnings—the ability to design from first principles, not just apply established recipes. 
• Computer architecture: microarchitecture design, computing paradigms at the circuit and datapath level, memory hierarchy design. 
• Performance engineering: roofline modeling, bandwidth analysis, kernel optimization, communication-computation overlap, and compiler-level tuning for novel hardware. 

Why This Opportunity Is Exciting And Unique 

• Build on a fundamentally different architecture, unconstrained by GPU assumptions. 
• Publish and open-source your research. We present at Supercomputing, SIAM, IEEE, NeurIPS, and beyond. 
• Work on the fastest AI system in the world, with direct access to the hardware your compiler targets. 
• Join at a pivotal moment: Cerebras is pre-IPO with strong commercial traction and rapid growth. 
• Be part of a small, technical team with high autonomy, minimal bureaucracy, and a culture that values depth over hierarchy. 

We are hiring for multiple positions across experience levels. If this work resonates, we encourage you to apply. 

About The Team 

Cerebras builds wafer-scale AI processors—single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras’ pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE, and NeurIPS) and directly influences the design of next-generation wafer-scale systems. 

About The Role 

We are seeking Compiler Engineers to join a small team of specialists working on our emerging Tungsten language compiler. Tungsten is Cerebras’ dataflow programming language, purpose-built for wafer-scale hardware. You will work on the Tungsten compiler from language design through code generation, building the toolchain that translates high-level intent into efficient execution across hundreds of thousands of cores with a memory and interconnect model unlike anything in conventional computing. 

This is not incremental work on an existing backend. The architecture is new, the programming model is new, and the compiler is where those two things meet. You will collaborate closely with Cerebras’ ASIC, kernel, and AI teams, and your design decisions will directly shape both the language and the hardware it targets. Beyond the compiler itself, the broader toolchain—runtime, debugger, simulator—is still being built, and we are equally interested in engineers who want to own those pieces of the developer experience on novel hardware. 

What You Will Do 

• Design and implement compiler passes across the Tungsten toolchain: mid-end optimization, backend code generation, instruction scheduling, register allocation, assembler, and linker. 
• Co-design language constructs that improve expressiveness and performance for dataflow execution on wafer-scale hardware. 
• Develop and iterate on code generation strategies for complex scientific and AI workloads, analyzing performance bottlenecks and closing the gap between peak and achieved throughput. 
• Extend the compiler to support future hardware architectures as they move from design to silicon. 
• Work directly with ASIC architects and application researchers to inform hardware-software co-design decisions. 

What We Are Looking For

• PhD in Computer Science or Computer Engineering preferred; exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply. 
• Substantial experience in compiler development: IR design, optimization passes, code generation, or backend implementation for novel or non-standard architectures. 
• Strong grasp of computer architecture: instruction sets, memory models, dataflow execution, and how hardware constraints shape compilation strategy. 
• Systems-level programming ability in C; comfort reasoning about performance at the instruction and memory-access level. 
• Ability to think about compilation as a design problem, not just an implementation task: you should have opinions about how language semantics, compiler IR, and hardware capabilities interact. 
• Excellent communication and interpersonal skills: able to work effectively in a small, fast-moving team where compiler, architecture, and application concerns are deeply intertwined. 

Valuable Assets 

• Experience with compilers for spatial, dataflow, or CGRA architectures where the compilation model diverges significantly from conventional CPU/GPU targets. 
• Exposure to ML compiler frameworks (MLIR, XLA, TVM) and understanding of how AI workloads map to hardware. 
• Experience with multi-dimensional data representations, tiling strategies, and vectorized operations. 
• Track record of published research or patents in compilers, programming languages, or architecture. 
• Experience building runtime systems, debuggers, or architecture simulators, particularly for non-standard hardware. 
• Understanding of parallel/distributed systems and cluster computing. 

Why This Opportunity Is Exciting And Unique 

• Build a compiler for hardware that doesn’t exist anywhere else. The architecture is the constraint and the opportunity. 
• Publish and open-source your research. We present at Supercomputing, SIAM, IEEE, NeurIPS, and beyond. 
• Work on the fastest AI system in the world, with direct access to the hardware your compiler targets. 
• Join at a pivotal moment: Cerebras is pre-IPO with strong commercial traction and rapid growth. 
• Be part of a small, technical team with high autonomy, minimal bureaucracy, and a culture that values depth over hierarchy. 

We are hiring for multiple positions across experience levels. If this work resonates, we encourage you to apply. 

Synthesis Health

Who We Are

We’re a mission- and values-driven company with tremendous dedication to our customers. Our 100% remote team is dedicated to a common goal – to revolutionize healthcare through innovation, collaboration, and commitment to our core values and behaviors.

About the Opportunity

We are looking for a Staff Platform Engineer to serve as the architect of our edge.

In this critical role, you will own the boundary between the world and our platform. You will own the "Customer Edge"—the mission-critical software gateways that run inside hospital networks, acting as the secure bridge for DICOM and HL7 data into our cloud platform.

You will solve unique distributed systems challenges: How do you buffer terabytes of imaging data on-premise when the hospital's internet goes down? How do you safely auto-update thousands of remote agents behind strict enterprise firewalls? How do you enforce fairness and rate limiting to prevent one tenant from degrading the experience for everyone else?

This is a hands-on leadership role. You will write high-performance code, define the architectural patterns for edge ingestion, and mentor engineers on the nuances of network reliability and secure tunneling.

Key Responsibilities

Customer Gateway Architecture & High Availability (HA)

• On-Premise Gateway Reliability: You will architect our edge gateway software to run reliably within customer data centers. You will implement HA patterns to ensure that a single hardware failure never stops critical patient data flow.
• High-Performance Ingestion: You will optimize the ingestion path for massive DICOM studies and HL7 streams. You will implement local queuing and backpressure mechanisms that protect our core platform from being overwhelmed by "thundering herds" of data when connectivity is restored after an outage.
• Versioning & Fleet Management: You will design the control plane for our distributed fleet of gateways. You will solve the "Day 2" operations challenge: architecting automated, over-the-air (OTA) update mechanisms that allow us to patch, upgrade, and version-manage thousands of remote agents without manual intervention or customer downtime.

Cloud Ingestion & Throughput Protection

• Resilient Ingestion Strategy: You will design the cloud-side ingestion layer (using technologies like Kafka or PubSub) to absorb massive bursts of traffic. You will ensure that our architecture can handle "thundering herds" from reconnected agents without dropping a single packet of patient data.
• Load Shedding & Fairness: You will implement sophisticated fairness algorithms and load shedding strategies at the ingestion point to ensure that no single customer gateway can monopolize cloud resources or degrade the performance of the broader platform.

Network & Connectivity Security

• Secure Tunnels: You will design the secure connectivity patterns (e.g., mutual TLS, reverse tunnels, VPNs) that allow our cloud to communicate with private hospital networks without requiring complex firewall exceptions.
• Mentorship: You will be the subject matter expert (SME) on networking and edge computing. You will mentor the team on TCP/IP mechanics, TLS optimization, and low-level network debugging.

What We’re Looking For

• Deep Edge & Networking Experience: 8+ years of engineering experience, with a focus on Edge Computing or Distributed Agents. You understand the physics of the internet, from TCP congestion control to TLS handshakes.
• Hybrid/On-Prem Expertise: You have shipped software that runs in customer environments (on-prem). You understand the constraints of enterprise firewalls, proxies, and limited bandwidth.
• Language Fluency: Deep expertise in Go (Golang) or TypeScript is required.
• Queuing & Streaming: Expert-level knowledge of asynchronous architectures using Google Cloud Pub/Sub, Dataflow, or Kafka. Given our GCP environment, deep proficiency with Pub/Sub and Dataflow is highly preferred. You understand backpressure and how to design for eventual consistency.
• Containerization: Experience distributing software via Docker/Kubernetes and managing container lifecycles in remote environments.

Preferred Qualifications

• Healthcare Interoperability: Deep, hands-on experience building integrations against DICOM (C-STORE, DIMSE services) or HL7 MLLP protocols. You understand the nuances of the association negotiation, transfer syntaxes, and strict acknowledgment requirements necessary to reliably accept data from legacy hospital systems.

Why You Should Join Us

• Solve Our Toughest Puzzles: This is a high-leverage role. You will be working on the most impactful technical challenges that are critical to the company's success.
• Define the Architecture: You won't just be maintaining a system; you will be a primary author of its future state, with the autonomy to make it happen.
• Lead from the Front: This is a chance to establish yourself as a key technical voice in a rapidly growing company.
• Competitive Compensation & Benefits: We offer a strong salary, a 100% remote culture, and significant opportunities for growth.

We are a values-driven company. Our values:

• Clinical service first.
• Collaborate with our customers.
• Listen, respect, learn.
• Innovate to excel.

The behaviors we look for:

• Be nice.
• Be creative.
• Be honest.
• Be helpful.

Compensation and Benefits

Typical salary range for this position is $120,000 - $150,000 (CAD). However, Synthesis participates in location based hiring and salary ranges can be adjusted based on candidate's residence. 

Other benefits include, but are not limited to: Medical, Dental, Vision, “Use as needed” vacation policy, and participation in our employee option program.